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u-boot
6 years agoarm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC
Ley Foon Tan [Fri, 18 May 2018 14:05:23 +0000 (22:05 +0800)]
arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC

Add Reset Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
6 years agoarm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC
Ley Foon Tan [Fri, 18 May 2018 14:05:22 +0000 (22:05 +0800)]
arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC

Add Clock Manager driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
6 years agoarm: socfpga: stratix10: Add watchdog and firewall base addresses
Ley Foon Tan [Fri, 18 May 2018 14:05:21 +0000 (22:05 +0800)]
arm: socfpga: stratix10: Add watchdog and firewall base addresses

Add the base address for watchdog and firewall.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
6 years agoARM: socfpga: Fix Documentation errors in scu_registers
Ben Kalo [Tue, 15 May 2018 16:45:37 +0000 (19:45 +0300)]
ARM: socfpga: Fix Documentation errors in scu_registers

According to ARM Cortex-A9 MPCore TRM section 2.2 - SCU registers
Access Control register offset is 0x50.

Signed-off-by: Ben Kalo <ben.h.kalo@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
6 years agoARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot
Tien Fong Chee [Tue, 5 Dec 2017 07:58:08 +0000 (15:58 +0800)]
ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot

SoC FPGA info is required in both SPL and U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
6 years agoARM: socfpga: Adding clock frequency info for U-Boot
Tien Fong Chee [Tue, 5 Dec 2017 07:58:07 +0000 (15:58 +0800)]
ARM: socfpga: Adding clock frequency info for U-Boot

Clock frequency info is required in U-Boot because info would be erased
when transition from SPL to U-Boot.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
6 years agoARM: socfpga: Enable SPL memory allocation
Tien Fong Chee [Tue, 5 Dec 2017 07:58:04 +0000 (15:58 +0800)]
ARM: socfpga: Enable SPL memory allocation

Enable memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
6 years agoconfigs: Add DDR Kconfig support for Arria 10
Tien Fong Chee [Tue, 5 Dec 2017 07:58:03 +0000 (15:58 +0800)]
configs: Add DDR Kconfig support for Arria 10

This patch enables DDR Kconfig support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
6 years agoARM: socfpga: Add DDR driver for Arria 10
Tien Fong Chee [Tue, 5 Dec 2017 07:58:02 +0000 (15:58 +0800)]
ARM: socfpga: Add DDR driver for Arria 10

Add DDR driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
6 years agoARM: socfpga: Add DRAM bank size initialization function
Tien Fong Chee [Tue, 5 Dec 2017 07:58:01 +0000 (15:58 +0800)]
ARM: socfpga: Add DRAM bank size initialization function

Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Tested-by: Ley Foon Tan <ley.foon.tan@intel.com>
6 years agoARM: socfpga: Rename the gen5 sdram driver to more specific name
Tien Fong Chee [Tue, 5 Dec 2017 07:58:00 +0000 (15:58 +0800)]
ARM: socfpga: Rename the gen5 sdram driver to more specific name

Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
6 years agoARM: socfpga: Repair A10 EMAC reset handling
Marek Vasut [Mon, 23 Apr 2018 20:49:31 +0000 (22:49 +0200)]
ARM: socfpga: Repair A10 EMAC reset handling

The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agoARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff
Marek Vasut [Sat, 12 May 2018 10:00:47 +0000 (12:00 +0200)]
ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff

Regenerate Altera Arria 10 SoCDK SDMMC handoff file using latest
Quartus to get the new set of clock bindings in.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agoARM: socfpga: Synchronize Arria10 DTs
Marek Vasut [Sun, 22 Apr 2018 23:37:57 +0000 (01:37 +0200)]
ARM: socfpga: Synchronize Arria10 DTs

Synchronize Altera Arria 10 DT sources with Linux 4.16.3 as of commit
ef8216d28a5920022cddcb694d2d75bd1f0035ca

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agoARM: socfpga: Sort the DT Makefile
Marek Vasut [Mon, 7 May 2018 20:29:17 +0000 (22:29 +0200)]
ARM: socfpga: Sort the DT Makefile

Sort the Makefile entries, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agoARM: socfpga: Sync A10 clock manager binding parser
Marek Vasut [Fri, 11 May 2018 22:09:21 +0000 (00:09 +0200)]
ARM: socfpga: Sync A10 clock manager binding parser

The A10 clock manager parsed DT bindings generated by Quartus the
bsp-editor to configure the A10 clocks. Sadly, those DT bindings
changed at some point. The clock manager patch used the old ones,
this patch replaces the bindings parser with one for the new set.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agoARM: socfpga: Convert to DM serial
Marek Vasut [Fri, 11 May 2018 20:26:35 +0000 (22:26 +0200)]
ARM: socfpga: Convert to DM serial

Pull the serial port configuration from DT and use DM serial instead
of having the serial configuration in two places, DT and board config.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agoARM: socfpga: Clean up Kconfig entries
Marek Vasut [Fri, 11 May 2018 20:25:59 +0000 (22:25 +0200)]
ARM: socfpga: Clean up Kconfig entries

Shuffle the default Kconfig entries around so it is not such a mess.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agoARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET
Marek Vasut [Sun, 22 Apr 2018 23:26:10 +0000 (01:26 +0200)]
ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET

This was never used, is not used anywhere and is just in the way
by adding annoying ifdeffery. Get rid of it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agoARM: socfpga: Put stack at the end of SRAM
Marek Vasut [Thu, 26 Apr 2018 20:23:05 +0000 (22:23 +0200)]
ARM: socfpga: Put stack at the end of SRAM

The global data are in the .data section, so there's no point in
reserving any space for it above stack. Put stack at the end of
SRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agofdt: Add another Altera Arria10 clock init compatible
Marek Vasut [Sat, 12 May 2018 09:56:10 +0000 (11:56 +0200)]
fdt: Add another Altera Arria10 clock init compatible

The DT bindings for the Arria10 clock init have changed, add another
compatible to make them work with U-Boot until a proper clock driver
gets written.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
6 years agoMerge git://www.denx.de/git/u-boot-marvell
Tom Rini [Thu, 17 May 2018 16:38:30 +0000 (12:38 -0400)]
Merge git://www.denx.de/git/u-boot-marvell

6 years agonet: MVGBE don't automatically select PHYLIB
Chris Packham [Thu, 17 May 2018 12:12:04 +0000 (00:12 +1200)]
net: MVGBE don't automatically select PHYLIB

When Kconfig support was added for MVGBE it included automatically
selected PHYLIB support. But MVGBE does not need PHYLIB it will build
fine without it. Commit ed52ea507f12 ("net: add Kconfig for MVGBE")
should have been a no-op in terms of build size but because of the
selecting PHYLIB the openrd configs increased in size.

Remove the automatic selection of PHYLIB, boards that need it will have
already enabled it in their config header file.

Fixes: commit ed52ea507f12 ("net: add Kconfig for MVGBE")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for sheevaplug
Chris Packham [Tue, 8 May 2018 10:34:21 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for sheevaplug

Import the dts files from Linux 4.17 and enable device tree control in
u-boot.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for pogo_e02
Chris Packham [Tue, 8 May 2018 10:34:20 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for pogo_e02

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for openrd
Chris Packham [Tue, 8 May 2018 10:34:19 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for openrd

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for nas220
Chris Packham [Tue, 8 May 2018 10:34:17 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for nas220

Import the dts file from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for iconnect
Chris Packham [Tue, 8 May 2018 10:34:16 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for iconnect

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for ib62x0
Chris Packham [Tue, 8 May 2018 10:34:15 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for ib62x0

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for guruplug
Chris Packham [Tue, 8 May 2018 10:34:14 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for guruplug

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for goflexhome
Chris Packham [Tue, 8 May 2018 10:34:13 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for goflexhome

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for dockstar
Chris Packham [Tue, 8 May 2018 10:34:12 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for dockstar

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: kirkwood: Add device-tree for dns325
Chris Packham [Tue, 8 May 2018 10:34:11 +0000 (22:34 +1200)]
ARM: kirkwood: Add device-tree for dns325

Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: add devicetree files for kirkwood SoC
Chris Packham [Tue, 8 May 2018 10:34:10 +0000 (22:34 +1200)]
ARM: add devicetree files for kirkwood SoC

These files are taken verbatim from the Linux kernel 4.17

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Wed, 16 May 2018 21:32:59 +0000 (17:32 -0400)]
Merge git://git.denx.de/u-boot-dm

6 years agoARM: re-enable MVGBE for edminiv2
Chris Packham [Wed, 16 May 2018 08:31:43 +0000 (20:31 +1200)]
ARM: re-enable MVGBE for edminiv2

This was unintentionally disabled when moving MVGBE to Kconfig.

Fixes: commit ed52ea507f12 ("net: add Kconfig for MVGBE")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
6 years agopinctrl: do not set_state for device without valid ofnode
Kever Yang [Wed, 18 Apr 2018 09:54:04 +0000 (17:54 +0800)]
pinctrl: do not set_state for device without valid ofnode

Not all the udevice have a available DT node, eg. rksdmmc@ff500000.blk
which add by mmc_bind(), these device do not have/need set pinctrl
state.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
6 years agotools: buildman: Don't use the working dir as build dir
Lothar Waßmann [Sun, 8 Apr 2018 11:14:11 +0000 (05:14 -0600)]
tools: buildman: Don't use the working dir as build dir

When the U-Boot base directory happens to have the same name as the branch
that buildman is directed to use via the '-b' option and no output
directory is specified with '-o', buildman happily starts removing the
whole U-Boot sources eventually only stopped with the error message:

OSError: [Errno 20] Not a directory: '../<branch-name>/boards.cfg

Add a check to avoid this and also deal with the case where '-o' points
to the source directory, or any subdirectory of it.

Finally, tidy up the confusing logic for removing the old tree when using
-b. This is only done when building a branch.

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
6 years agousb: composite convert __set_bit to generic_set_bit
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:10 +0000 (15:56 +0100)]
usb: composite convert __set_bit to generic_set_bit

Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h

To address that situation we discussed on the list moving to
genetic_set_bit() instead.

Doing a quick grep for similar situations in drivers/usb shows that the
composite device is using __set_bit().

This patch switches over to generic_set_bit to maintain consistency between
the two gadget drivers.

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
6 years agousb: f_mass_storage: Fix set_bit and clear_bit usage
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:09 +0000 (15:56 +0100)]
usb: f_mass_storage: Fix set_bit and clear_bit usage

Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h

Looking at the provenance of the current u-boot code and the git change
history in the kernel, it looks like we have a local copy of set_bit and
clear_bit as a hold-over from porting the Linux driver into u-boot.

These days __set_bit and __clear_bit are optionally provided by an arch and
can be used as inputs to generic_bit_set and generic_bit_clear.

This patch switches over to generic_set_bit and generic_clear_bit to
accommodate.

Tested on i.MX WaRP7 and Intel Edison

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
6 years agonds32: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:08 +0000 (15:56 +0100)]
nds32: Define PLATFORM__CLEAR_BIT for generic_clear_bit()

nds2 bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
nds32 bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Macpaul Lin <macpaul@andestech.com>
6 years agonds32: Define PLATFORM__SET_BIT for generic_set_bit()
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:07 +0000 (15:56 +0100)]
nds32: Define PLATFORM__SET_BIT for generic_set_bit()

nds32 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in nds32
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Macpaul Lin <macpaul@andestech.com>
6 years agonios2: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:06 +0000 (15:56 +0100)]
nios2: Define PLATFORM__CLEAR_BIT for generic_clear_bit()

nios2 bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
nios2 bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Thomas Chou <thomas@wytron.com.tw>
6 years agonios2: Define PLATFORM__SET_BIT for generic_set_bit()
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:05 +0000 (15:56 +0100)]
nios2: Define PLATFORM__SET_BIT for generic_set_bit()

nios2 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in nios2
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Thomas Chou <thomas@wytron.com.tw>
6 years agoriscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:04 +0000 (15:56 +0100)]
riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()

riscv bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().

This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
riscv bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agoriscv: Define PLATFORM__SET_BIT for generic_set_bit()
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:03 +0000 (15:56 +0100)]
riscv: Define PLATFORM__SET_BIT for generic_set_bit()

riscv bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
6 years agox86: Define PLATFORM__SET_BIT for generic_set_bit()
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:02 +0000 (15:56 +0100)]
x86: Define PLATFORM__SET_BIT for generic_set_bit()

x86 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().

This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().

Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
6 years agoARM: mvebu: a38x: Add missing SPDX license identfier
Chris Packham [Tue, 15 May 2018 01:31:11 +0000 (13:31 +1200)]
ARM: mvebu: a38x: Add missing SPDX license identfier

mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code.
When imported into u-boot we need to add the appropriate SPDX tag and
re-format it slightly.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
6 years agoMerge branch 'master' of git://git.denx.de/u-boot-video
Tom Rini [Tue, 15 May 2018 12:29:24 +0000 (08:29 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-video

6 years agodts: sunxi: add PWM node for sun50i
Vasily Khoruzhick [Mon, 14 May 2018 15:16:21 +0000 (08:16 -0700)]
dts: sunxi: add PWM node for sun50i

Add PWM definition to sun50i-a64.dtsi

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
6 years agopwm: sunxi: add support for PWM found on Allwinner A64
Vasily Khoruzhick [Mon, 14 May 2018 15:16:20 +0000 (08:16 -0700)]
pwm: sunxi: add support for PWM found on Allwinner A64

This commit adds basic support for PWM found on Allwinner A64.
It can be used for pwm_backlight driver (e.g. for Pinebook)

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
6 years agovideo: dw_hdmi: fix HSYNC and VSYNC polarity settings
Vasily Khoruzhick [Mon, 14 May 2018 20:49:53 +0000 (13:49 -0700)]
video: dw_hdmi: fix HSYNC and VSYNC polarity settings

Currently dw_hdmi configures HSYNC polarity using VSYNC setting from
EDID and vice versa. Fix it, since it breaks displays where HSYNC
and VSYNC polarity differs

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
6 years agosunxi: video: HDMI: use correct bits for HSYNC and VSYNC polarity.
Vasily Khoruzhick [Mon, 14 May 2018 20:49:52 +0000 (13:49 -0700)]
sunxi: video: HDMI: use correct bits for HSYNC and VSYNC polarity.

HSYNC is bit 8, and VSYNC is bit 9.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
6 years agommc: sdhci: Check that ops are defined
Ramon Fried [Mon, 14 May 2018 12:02:30 +0000 (15:02 +0300)]
mmc: sdhci: Check that ops are defined

The check is necessary to avoid NULL pointer dereference.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
6 years agonet: add Kconfig for MVGBE
Chris Packham [Thu, 3 May 2018 11:00:35 +0000 (23:00 +1200)]
net: add Kconfig for MVGBE

Add Kconfig for MVGBE and update boards to select this.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
6 years agonet: mvgbe: remove CONFIG_DOVE
Chris Packham [Thu, 3 May 2018 11:00:34 +0000 (23:00 +1200)]
net: mvgbe: remove CONFIG_DOVE

Nothing defines CONFIG_DOVE so remove the code that uses it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
6 years agonet: bootp: Fix compile error processing ntpserver option
Chris Packham [Thu, 3 May 2018 08:19:03 +0000 (20:19 +1200)]
net: bootp: Fix compile error processing ntpserver option

When the following configuration is set

  # CONFIG_CMD_DHCP is not set
  CONFIG_CMD_BOOTP=y
  CONFIG_BOOTP_NTPSERVER=y

The following compile error is observed

  error: used struct type value where scalar is required
    if (net_ntp_server)
        ^~~~~~~~~~~~~~

Resolve this by checking net_ntp_server.s_addr instead.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
6 years agonet: Add Kconfig option for BOOTP_NTPSERVER
Chris Packham [Thu, 3 May 2018 08:19:02 +0000 (20:19 +1200)]
net: Add Kconfig option for BOOTP_NTPSERVER

Add a Kconfig option for BOOTP_NTPSERVER to enable the DHCP/BOOTP option
to configure the sntp server address.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
6 years agotreewide: Move CONFIG_PHY_MARVELL to Kconfig
Mario Six [Fri, 27 Apr 2018 12:52:21 +0000 (14:52 +0200)]
treewide: Move CONFIG_PHY_MARVELL to Kconfig

The CONFIG_PHY_MARVELL has already been migrated to Kconfig (some boards
already had it in their Kconfig), but had not been moved for older
boards.

Move it to the defconfigs for all boards.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
6 years agoMerge branch 'master' of git://git.denx.de/u-boot-rockchip
Tom Rini [Mon, 14 May 2018 22:13:59 +0000 (18:13 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-rockchip

6 years agorockchip: clk: rk3288: handle clk_enable requests for GMAC
Jonathan Gray [Tue, 8 May 2018 09:49:05 +0000 (19:49 +1000)]
rockchip: clk: rk3288: handle clk_enable requests for GMAC

Since b0ba1e7e9d9b9441a18048ec67a3b3100c096975
(rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC)
Ethernet no longer probes on RK3288.

Add no-ops for GMAC clocks observed to be requested which match the
clk_enable cases in RK3368 and RK3399.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: Wadim Egorov <w.egorov@phytec.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
6 years agorockchip: set SYS_NS16550_MEM32 for all SoCs
Jonathan Gray [Tue, 8 May 2018 10:43:01 +0000 (20:43 +1000)]
rockchip: set SYS_NS16550_MEM32 for all SoCs

Add back part of patch send out as
'rockchip: enable SYS_NS16550 for all SoCs by default' that seems to have
gotten lost when it got merged to set SYS_NS16550_MEM32.

Allows serial output to work on tinker-rk3288 again after
c3c0331db1fb7b1f4ff41e144fc04353b37c785c.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
6 years agoMerge git://git.denx.de/u-boot-marvell
Tom Rini [Mon, 14 May 2018 12:52:48 +0000 (08:52 -0400)]
Merge git://git.denx.de/u-boot-marvell

6 years agophy: marvell: a3700: Fix compatible string for ehci
Marek Behún [Fri, 11 May 2018 08:03:39 +0000 (10:03 +0200)]
phy: marvell: a3700: Fix compatible string for ehci

The DTS file for armada-37xx uses the string "marvell,armada3700-ehci",
but the code searched for "marvell,armada-3700-ehci".

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: mvebu: a38x: use non-zero size for ddr scrubbing
Chris Packham [Thu, 10 May 2018 01:28:31 +0000 (13:28 +1200)]
ARM: mvebu: a38x: use non-zero size for ddr scrubbing

Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: mvebu: a38x: restore support for setting timing
Chris Packham [Thu, 10 May 2018 01:28:30 +0000 (13:28 +1200)]
ARM: mvebu: a38x: restore support for setting timing

This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit 90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: mvebu: a38x: sync ddr training code with upstream
Chris Packham [Thu, 10 May 2018 01:28:29 +0000 (13:28 +1200)]
ARM: mvebu: a38x: sync ddr training code with upstream

This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdef

  find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
    xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
-UCONFIG_APN806 -UCONFIG_MC_STATIC \
-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_64BIT

INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.

Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: mvebu: a38x: remove some unused code
Chris Packham [Thu, 10 May 2018 01:28:28 +0000 (13:28 +1200)]
ARM: mvebu: a38x: remove some unused code

No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or
STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to
remove unused sections in the rest of the ddr/marvell/a38x code.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: mvebu: a38x: move sys_env_device_rev_get
Chris Packham [Thu, 10 May 2018 01:28:27 +0000 (13:28 +1200)]
ARM: mvebu: a38x: move sys_env_device_rev_get

Move sys_env_device_rev_get() from the ddr training code to
sys_env_lib.c (which currently resides with the serdes code). This
brings sys_env_device_rev_get() into line with sys_env_device_id_get()
and sys_env_model_get().

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESS
Chris Packham [Thu, 10 May 2018 01:28:26 +0000 (13:28 +1200)]
ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESS

PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite
only being used in the serdes code. Move this definition to ctrl_pex.h
where all the other PEX defines are. Also remove the duplicate
definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in
ctrl_pex.h.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoarm64: mvebu: Add basic support for the Turris Mox board
Marek Behún [Tue, 24 Apr 2018 15:21:31 +0000 (17:21 +0200)]
arm64: mvebu: Add basic support for the Turris Mox board

This adds basic support for the Turris Mox board from CZ.NIC, which is
currently being crowdfunded on Indiegogo.

Turris Mox is as modular router based on the Armada 3720 SOC (same as
EspressoBin).

The basic module can be extended by different modules. The device tree
binary for the kernel can be dependent on which modules are connected,
and in what order. Because of this, the board specific code creates
in U-Boot a variable called module_topology, which carries this
information.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agowatchdog: Add support for Armada 37xx CPU watchdog
Marek Behún [Tue, 24 Apr 2018 15:21:30 +0000 (17:21 +0200)]
watchdog: Add support for Armada 37xx CPU watchdog

This adds support for the CPU watchdog found on Marvell Armada 37xx
SoCs.

There are 4 counters which can be set as CPU watchdog counters.
This driver uses the second counter (ID 1, counting from 0)
(Marvell's Linux also uses second counter by default).
In the future it could be adapted to use other counters, with
definition in the device tree.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agonet: mvneta: Fix fault when wrong device tree
Marek Behún [Tue, 24 Apr 2018 15:21:29 +0000 (17:21 +0200)]
net: mvneta: Fix fault when wrong device tree

The driver does not check id phy_connect failed (for example on wrong
property name in device tree). In such a case a fault occurs and the
CPU is restarted.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: core: Cosmetic fixes
Marek Behún [Tue, 24 Apr 2018 15:21:28 +0000 (17:21 +0200)]
phy: marvell: core: Cosmetic fixes

Move the reg_set* functions into comphy.h as static inline functions.
Change return type of get_*_string to const char *.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agoclk: armada-37xx: Support soc_clk_dump
Marek Behún [Tue, 24 Apr 2018 15:21:27 +0000 (17:21 +0200)]
clk: armada-37xx: Support soc_clk_dump

Add support for the clk dump command on Armada 37xx.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agospi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequency
Marek Behún [Tue, 24 Apr 2018 15:21:26 +0000 (17:21 +0200)]
spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequency

Since now we have driver for clocks on Armada 37xx, use it to determine
SQF clock frequency for the SPI driver.

Also change the default config files for Armada 37xx devices so that
the clock driver is enabled by default, otherwise the SPI driver cannot
be enabled.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agodriver: clk: Add support for clocks on Armada 37xx
Marek Behún [Tue, 24 Apr 2018 15:21:25 +0000 (17:21 +0200)]
driver: clk: Add support for clocks on Armada 37xx

The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
  - since setting rate is not supported, the driver computes the rates
    when probing and so subsequent calls to the .get_rate method do not
    read the corresponding registers again

The peripheral clocks support methods .get_rate, .enable and .disable.

  - the .set_parent method theoretically could be supported on some clocks
    (the parent would have to be one of the TBG clocks)

  - the .set_rate method would have to try all the divider values to find
    the best approximation of a given rate, and it doesn't seem like
    this should be needed in U-Boot, therefore not implemented

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Save/restore selector reg in SGMII init
Marek Behún [Tue, 24 Apr 2018 15:21:24 +0000 (17:21 +0200)]
phy: marvell: a3700: Save/restore selector reg in SGMII init

In SGMII initialization PIN_PIPE_SEL has to be zero when resetting
the PHY. Since comphy_mux already set the selector register to
correct values, we have to store it's value before setting it to 0
and restore it after SGMII init.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Use comphy_mux on Armada 37xx.
Marek Behún [Tue, 24 Apr 2018 15:21:23 +0000 (17:21 +0200)]
phy: marvell: a3700: Use comphy_mux on Armada 37xx.

Lane 0 supports SGMII1 and USB3.
Lane 1 supports SGMII0 and PEX0.
Lane 2 supports SATA0 and USB3.

This is needed for Armada 37xx.

This introduces new device tree bindings. AFAIK there is currently no
driver for Armada 37xx comphy in Linux. When such a driver will be
pushed into Linux, this will need to be rewritten accordingly.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Fix SGMII cfg and stat register addresses
Marek Behún [Tue, 24 Apr 2018 15:21:22 +0000 (17:21 +0200)]
phy: marvell: a3700: Fix SGMII cfg and stat register addresses

The register addresses on lanes 0 and 1 are switched, first comes 1 and
then 0.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: mux: Support nontrivial node order in selector register
Marek Behún [Tue, 24 Apr 2018 15:21:21 +0000 (17:21 +0200)]
phy: marvell: mux: Support nontrivial node order in selector register

Currently comphy_mux supports only trivial order of nodes in pin
selector register, that is lane N on position N*bitcount.

Add support for nontrivial order, with map stored in device tree
property mux-lane-order.

This is needed for Armada 37xx.

As far as I know, there is no driver for Armada 37xx comphy in the
kernel. When such a driver comes, this will need to be rewritten to
support the device tree bindings from the kernel.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: revise the USB3 comphy setting during power on
zachary [Tue, 24 Apr 2018 15:21:20 +0000 (17:21 +0200)]
phy: marvell: a3700: revise the USB3 comphy setting during power on

This commit is based on commit d9899826 by
  zachary <zhangzg@marvell.com>
from u-boot-marvell, see
github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826

- According to design specification, the transmitter should be set to high
  impedence mode during electrical idle. Thus transmitter should detect RX
  at high impedence mode also, and delay is needed to accommodate high
  impedence off latency. Otherwise the USB3 will have detection issue that
  most of the time the USB3 device can not be detected at all, or be
  detected as USB2 device sometimes.
  Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1
  Bit 6: set to 1 to let Tx detect Rx at HiZ mode
  Bit [3:4]: set to 2 to be delayed by 2 clock cycles
  Bit 0: set to 1 to set transmitter to high impedance mode during idle.
- USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2
  (emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed
  to select 0x1(3.5dB emphasize). Thus need to override what comes from
  the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the
  overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register
  0x181 and bit0 of register 0x180).
- According to USB3 application note, need to update below comphy
  registers:
  Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1)
  Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF)

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Set USB3 RX wait depending on ref clock
Marek Behún [Tue, 24 Apr 2018 15:21:19 +0000 (17:21 +0200)]
phy: marvell: a3700: Set USB3 RX wait depending on ref clock

According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7
when reference clock is at 25 MHz. The specification (at least the
version I have) does not mentoin the setting for 40 MHz reference
clock, but Marvell's U-Boot sets 0xC in that case.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Access USB3 register indirectly on lane 2
Marek Behún [Tue, 24 Apr 2018 15:21:18 +0000 (17:21 +0200)]
phy: marvell: a3700: Access USB3 register indirectly on lane 2

When USB3 is on comphy lane 2 on the Armada 37xx, the registers
have to be accessed indirectly via SATA indirect access.

This is the case of the Turris Mox board from CZ.NIC.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Use reg_set_indirect istead of 2 reg_sets
Marek Behún [Tue, 24 Apr 2018 15:21:17 +0000 (17:21 +0200)]
phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_sets

Create a special function for indirect register setting,
reg_set_indirect, and use it instead of the two calls to reg_set.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Use (!ret) instead of (ret == 0)
Marek Behún [Tue, 24 Apr 2018 15:21:16 +0000 (17:21 +0200)]
phy: marvell: a3700: Use (!ret) instead of (ret == 0)

In U-Boot it is usually written this way.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Use same timeout for all register polling
Marek Behún [Tue, 24 Apr 2018 15:21:15 +0000 (17:21 +0200)]
phy: marvell: a3700: Use same timeout for all register polling

The timeout is set to PLL_LOCK_TIMEOUT in every call to
comphy_poll_reg. Remove this parameter from the function.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Don't create functional macro for each register
Marek Behún [Tue, 24 Apr 2018 15:21:14 +0000 (17:21 +0200)]
phy: marvell: a3700: Don't create functional macro for each register

Currently there is for each register special functional macro, ie:
  LANE_CFG1_ADDR(u)
  GLOB_CLK_SRC_LO_ADDR(u)
  ...
where can be either PCIE or USB3.

Change this to one function PHY_ADDR(unit, addr). The code becomes:
  phy_addr(PCIE, LANE_CFG1)
  phy_addr(PCIE, GLOB_CLK_SRC_LO)
  ...

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Use reg_set16 instead of phy_write16
Marek Behún [Tue, 24 Apr 2018 15:21:13 +0000 (17:21 +0200)]
phy: marvell: a3700: Use reg_set16 instead of phy_write16

The macro phy_write16 is not used by the rest of the code,
phy_read16 is not used at all.
We also change the macro SGMIIPHY_ADDR to a static inline function.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agophy: marvell: a3700: Change return type of macro MVEBU_REG
Marek Behún [Tue, 24 Apr 2018 15:21:12 +0000 (17:21 +0200)]
phy: marvell: a3700: Change return type of macro MVEBU_REG

All the calls to reg_set and friends have to cast the first argument
to void __iomem *. Lets change the return type of the MVEBU_REG macro
instead.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
6 years agommc: Improve tinification
Marek Vasut [Sat, 14 Apr 2018 22:37:11 +0000 (00:37 +0200)]
mmc: Improve tinification

Drop all the extra content from the MMC core, so that tiny MMC support
is really tiny, no fancy anything. That means the tiny MMC support does
only 1-bit transfers at default speed settings. Moreover, this patch
drops duplicate instance of struct mmc mmc_static, which wasted about
360 bytes. Furthermore, since MMC tiny supports only one controller
at all times, get rid of mallocating the ext csd backup and replace
it with static array. All in all, this patch saves ~4 kiB of bloat
from the MMC core, which on platforms with severe limitations can be
beneficial.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Fixup checkpatch.pl style warnings]
Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoMerge git://git.denx.de/u-boot-tegra
Tom Rini [Fri, 11 May 2018 19:22:36 +0000 (15:22 -0400)]
Merge git://git.denx.de/u-boot-tegra

6 years agoSPDX: Correct SPDX tags from recent xilinx merge
Tom Rini [Fri, 11 May 2018 18:54:57 +0000 (14:54 -0400)]
SPDX: Correct SPDX tags from recent xilinx merge

Correct the SPDX tag format.

Fixes: 3b52847a451a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze")
Signed-off-by: Tom Rini <trini@konsulko.com>
6 years agoMerge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze
Tom Rini [Fri, 11 May 2018 15:45:28 +0000 (11:45 -0400)]
Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING

zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation

mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode

nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params

scsi:
- convert ceva sata to UCLASS_AHCI

timer:
- Add Cadence TTC for ZynqMP r5

watchdog:
- Minor cadence driver cleanup

6 years agoMerge git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Fri, 11 May 2018 11:09:21 +0000 (07:09 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq

6 years agoarm64: zynqmp: Enable UHS support for ZCU102 Rev1.0 board
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:10 +0000 (12:37 +0530)]
arm64: zynqmp: Enable UHS support for ZCU102 Rev1.0 board

This patch enables UHS support for ZynqMP zcu102 rev 1.0
board.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agommc: zynq_sdhci: Add support for SD3.0
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:09 +0000 (12:37 +0530)]
mmc: zynq_sdhci: Add support for SD3.0

This patch adds support of SD3.0 for ZynqMP.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agommc: sdhci: Read capabilities register1 and update host caps
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:08 +0000 (12:37 +0530)]
mmc: sdhci: Read capabilities register1 and update host caps

This patch reads the capabilities register1 and update the host
caps accordingly for mmc layer usage. This patch mainly reads
for UHS capabilities inorder to support SD3.0.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agommc: sdhci: Invoke platform specific tuning and delay routines
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:07 +0000 (12:37 +0530)]
mmc: sdhci: Invoke platform specific tuning and delay routines

This patch adds support to invoke any platform specific tuning
and delay routines if available.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
6 years agosdhci: Add new sdhci ops for platform specific tuning and delays
Siva Durga Prasad Paladugu [Thu, 19 Apr 2018 07:07:06 +0000 (12:37 +0530)]
sdhci: Add new sdhci ops for platform specific tuning and delays

This patch adds new hooks for any platform specific tuning and
tap delays programing. These are needed for supporting
SD3.0.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>