#ifndef __ASSEMBLY__
-unsigned long sdram_calculate_size(void);
-int sdram_mmr_init_full(unsigned int sdr_phy_reg);
-int sdram_calibration_full(void);
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
-
-#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
-
-struct socfpga_sdr_ctrl {
- u32 ctrl_cfg;
- u32 dram_timing1;
- u32 dram_timing2;
- u32 dram_timing3;
- u32 dram_timing4; /* 0x10 */
- u32 lowpwr_timing;
- u32 dram_odt;
- u32 extratime1;
- u32 __padding0[3];
- u32 dram_addrw; /* 0x2c */
- u32 dram_if_width; /* 0x30 */
- u32 dram_dev_width;
- u32 dram_sts;
- u32 dram_intr;
- u32 sbe_count; /* 0x40 */
- u32 dbe_count;
- u32 err_addr;
- u32 drop_count;
- u32 drop_addr; /* 0x50 */
- u32 lowpwr_eq;
- u32 lowpwr_ack;
- u32 static_cfg;
- u32 ctrl_width; /* 0x60 */
- u32 cport_width;
- u32 cport_wmap;
- u32 cport_rmap;
- u32 rfifo_cmap; /* 0x70 */
- u32 wfifo_cmap;
- u32 cport_rdwr;
- u32 port_cfg;
- u32 fpgaport_rst; /* 0x80 */
- u32 __padding1;
- u32 fifo_cfg;
- u32 protport_default;
- u32 prot_rule_addr; /* 0x90 */
- u32 prot_rule_id;
- u32 prot_rule_data;
- u32 prot_rule_rdwr;
- u32 __padding2[3];
- u32 mp_priority; /* 0xac */
- u32 mp_weight0; /* 0xb0 */
- u32 mp_weight1;
- u32 mp_weight2;
- u32 mp_weight3;
- u32 mp_pacing0; /* 0xc0 */
- u32 mp_pacing1;
- u32 mp_pacing2;
- u32 mp_pacing3;
- u32 mp_threshold0; /* 0xd0 */
- u32 mp_threshold1;
- u32 mp_threshold2;
- u32 __padding3[29];
- u32 phy_ctrl0; /* 0x150 */
- u32 phy_ctrl1;
- u32 phy_ctrl2;
-};
-
-/* SDRAM configuration structure for the SPL. */
-struct socfpga_sdram_config {
- u32 ctrl_cfg;
- u32 dram_timing1;
- u32 dram_timing2;
- u32 dram_timing3;
- u32 dram_timing4;
- u32 lowpwr_timing;
- u32 dram_odt;
- u32 extratime1;
- u32 dram_addrw;
- u32 dram_if_width;
- u32 dram_dev_width;
- u32 dram_intr;
- u32 lowpwr_eq;
- u32 static_cfg;
- u32 ctrl_width;
- u32 cport_width;
- u32 cport_wmap;
- u32 cport_rmap;
- u32 rfifo_cmap;
- u32 wfifo_cmap;
- u32 cport_rdwr;
- u32 port_cfg;
- u32 fpgaport_rst;
- u32 fifo_cfg;
- u32 mp_priority;
- u32 mp_weight0;
- u32 mp_weight1;
- u32 mp_weight2;
- u32 mp_weight3;
- u32 mp_pacing0;
- u32 mp_pacing1;
- u32 mp_pacing2;
- u32 mp_pacing3;
- u32 mp_threshold0;
- u32 mp_threshold1;
- u32 mp_threshold2;
- u32 phy_ctrl0;
-};
-
-struct socfpga_sdram_rw_mgr_config {
- u8 activate_0_and_1;
- u8 activate_0_and_1_wait1;
- u8 activate_0_and_1_wait2;
- u8 activate_1;
- u8 clear_dqs_enable;
- u8 guaranteed_read;
- u8 guaranteed_read_cont;
- u8 guaranteed_write;
- u8 guaranteed_write_wait0;
- u8 guaranteed_write_wait1;
- u8 guaranteed_write_wait2;
- u8 guaranteed_write_wait3;
- u8 idle;
- u8 idle_loop1;
- u8 idle_loop2;
- u8 init_reset_0_cke_0;
- u8 init_reset_1_cke_0;
- u8 lfsr_wr_rd_bank_0;
- u8 lfsr_wr_rd_bank_0_data;
- u8 lfsr_wr_rd_bank_0_dqs;
- u8 lfsr_wr_rd_bank_0_nop;
- u8 lfsr_wr_rd_bank_0_wait;
- u8 lfsr_wr_rd_bank_0_wl_1;
- u8 lfsr_wr_rd_dm_bank_0;
- u8 lfsr_wr_rd_dm_bank_0_data;
- u8 lfsr_wr_rd_dm_bank_0_dqs;
- u8 lfsr_wr_rd_dm_bank_0_nop;
- u8 lfsr_wr_rd_dm_bank_0_wait;
- u8 lfsr_wr_rd_dm_bank_0_wl_1;
- u8 mrs0_dll_reset;
- u8 mrs0_dll_reset_mirr;
- u8 mrs0_user;
- u8 mrs0_user_mirr;
- u8 mrs1;
- u8 mrs1_mirr;
- u8 mrs2;
- u8 mrs2_mirr;
- u8 mrs3;
- u8 mrs3_mirr;
- u8 precharge_all;
- u8 read_b2b;
- u8 read_b2b_wait1;
- u8 read_b2b_wait2;
- u8 refresh_all;
- u8 rreturn;
- u8 sgle_read;
- u8 zqcl;
-
- u8 true_mem_data_mask_width;
- u8 mem_address_mirroring;
- u8 mem_data_mask_width;
- u8 mem_data_width;
- u8 mem_dq_per_read_dqs;
- u8 mem_dq_per_write_dqs;
- u8 mem_if_read_dqs_width;
- u8 mem_if_write_dqs_width;
- u8 mem_number_of_cs_per_dimm;
- u8 mem_number_of_ranks;
- u8 mem_virtual_groups_per_read_dqs;
- u8 mem_virtual_groups_per_write_dqs;
-};
-
-struct socfpga_sdram_io_config {
- u16 delay_per_opa_tap;
- u8 delay_per_dchain_tap;
- u8 delay_per_dqs_en_dchain_tap;
- u8 dll_chain_length;
- u8 dqdqs_out_phase_max;
- u8 dqs_en_delay_max;
- u8 dqs_en_delay_offset;
- u8 dqs_en_phase_max;
- u8 dqs_in_delay_max;
- u8 dqs_in_reserve;
- u8 dqs_out_reserve;
- u8 io_in_delay_max;
- u8 io_out1_delay_max;
- u8 io_out2_delay_max;
- u8 shift_dqs_en_when_shift_dqs;
-};
-
-struct socfpga_sdram_misc_config {
- u32 reg_file_init_seq_signature;
- u8 afi_rate_ratio;
- u8 calib_lfifo_offset;
- u8 calib_vfifo_offset;
- u8 enable_super_quick_calibration;
- u8 max_latency_count_width;
- u8 read_valid_fifo_size;
- u8 tinit_cntr0_val;
- u8 tinit_cntr1_val;
- u8 tinit_cntr2_val;
- u8 treset_cntr0_val;
- u8 treset_cntr1_val;
- u8 treset_cntr2_val;
-};
-
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
-#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
-#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
-#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
-#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
-#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
-#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
-#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
-#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
-#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
-/* Register template: sdr::ctrlgrp::dramtiming1 */
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
-#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
-#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming2 */
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
-#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
-#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
-#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
-/* Register template: sdr::ctrlgrp::dramtiming3 */
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
-#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
-#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
-#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramtiming4 */
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
-#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
-#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::lowpwrtiming */
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
-#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
-/* Register template: sdr::ctrlgrp::dramaddrw */
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
-#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
-#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
-#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
-/* Register template: sdr::ctrlgrp::dramifwidth */
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::dramdevwidth */
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
-/* Register template: sdr::ctrlgrp::dramintr */
-#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
-#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
-#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
-/* Register template: sdr::ctrlgrp::staticcfg */
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
-#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
-#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
-#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::ctrlwidth */
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
-/* Register template: sdr::ctrlgrp::cportwidth */
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::cportwmap */
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::cportrmap */
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::rfifocmap */
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::wfifocmap */
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::cportrdwr */
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
-/* Register template: sdr::ctrlgrp::portcfg */
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
-#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::fifocfg */
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
-#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
-/* Register template: sdr::ctrlgrp::mppriority */
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
-/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
-0xffffffff
-/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
-#define \
-SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
-0x0000ffff
-/* Register template: sdr::ctrlgrp::remappriority */
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
- (((x) << 10) & 0x00000c00)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
- (((x) << 6) & 0x000000c0)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
- (((x) << 8) & 0x00000100)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
- (((x) << 9) & 0x00000200)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
- (((x) << 4) & 0x00000030)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
- (((x) << 2) & 0x0000000c)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
- (((x) << 0) & 0x00000003)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
- (((x) << 12) & 0xfffff000)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
- (((x) << 0) & 0x00000fff)
-/* Register template: sdr::ctrlgrp::dramodt */
-#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
-#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
-#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
-#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
-/* Field instance: sdr::ctrlgrp::dramsts */
-#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
-#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
-/* Register template: sdr::ctrlgrp::extratime1 */
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
-
-/* SDRAM width macro for configuration with ECC */
-#define SDRAM_WIDTH_32BIT_WITH_ECC 40
-#define SDRAM_WIDTH_16BIT_WITH_ECC 24
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/sdram_gen5.h>
+#endif
#endif
#endif /* _SDRAM_H_ */
--- /dev/null
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _SOCFPGA_SDRAM_GEN5_H_
+#define _SOCFPGA_SDRAM_GEN5_H_
+
+#ifndef __ASSEMBLY__
+
+unsigned long sdram_calculate_size(void);
+int sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
+
+void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
+void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
+const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
+
+#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
+
+struct socfpga_sdr_ctrl {
+ u32 ctrl_cfg;
+ u32 dram_timing1;
+ u32 dram_timing2;
+ u32 dram_timing3;
+ u32 dram_timing4; /* 0x10 */
+ u32 lowpwr_timing;
+ u32 dram_odt;
+ u32 extratime1;
+ u32 __padding0[3];
+ u32 dram_addrw; /* 0x2c */
+ u32 dram_if_width; /* 0x30 */
+ u32 dram_dev_width;
+ u32 dram_sts;
+ u32 dram_intr;
+ u32 sbe_count; /* 0x40 */
+ u32 dbe_count;
+ u32 err_addr;
+ u32 drop_count;
+ u32 drop_addr; /* 0x50 */
+ u32 lowpwr_eq;
+ u32 lowpwr_ack;
+ u32 static_cfg;
+ u32 ctrl_width; /* 0x60 */
+ u32 cport_width;
+ u32 cport_wmap;
+ u32 cport_rmap;
+ u32 rfifo_cmap; /* 0x70 */
+ u32 wfifo_cmap;
+ u32 cport_rdwr;
+ u32 port_cfg;
+ u32 fpgaport_rst; /* 0x80 */
+ u32 __padding1;
+ u32 fifo_cfg;
+ u32 protport_default;
+ u32 prot_rule_addr; /* 0x90 */
+ u32 prot_rule_id;
+ u32 prot_rule_data;
+ u32 prot_rule_rdwr;
+ u32 __padding2[3];
+ u32 mp_priority; /* 0xac */
+ u32 mp_weight0; /* 0xb0 */
+ u32 mp_weight1;
+ u32 mp_weight2;
+ u32 mp_weight3;
+ u32 mp_pacing0; /* 0xc0 */
+ u32 mp_pacing1;
+ u32 mp_pacing2;
+ u32 mp_pacing3;
+ u32 mp_threshold0; /* 0xd0 */
+ u32 mp_threshold1;
+ u32 mp_threshold2;
+ u32 __padding3[29];
+ u32 phy_ctrl0; /* 0x150 */
+ u32 phy_ctrl1;
+ u32 phy_ctrl2;
+};
+
+/* SDRAM configuration structure for the SPL. */
+struct socfpga_sdram_config {
+ u32 ctrl_cfg;
+ u32 dram_timing1;
+ u32 dram_timing2;
+ u32 dram_timing3;
+ u32 dram_timing4;
+ u32 lowpwr_timing;
+ u32 dram_odt;
+ u32 extratime1;
+ u32 dram_addrw;
+ u32 dram_if_width;
+ u32 dram_dev_width;
+ u32 dram_intr;
+ u32 lowpwr_eq;
+ u32 static_cfg;
+ u32 ctrl_width;
+ u32 cport_width;
+ u32 cport_wmap;
+ u32 cport_rmap;
+ u32 rfifo_cmap;
+ u32 wfifo_cmap;
+ u32 cport_rdwr;
+ u32 port_cfg;
+ u32 fpgaport_rst;
+ u32 fifo_cfg;
+ u32 mp_priority;
+ u32 mp_weight0;
+ u32 mp_weight1;
+ u32 mp_weight2;
+ u32 mp_weight3;
+ u32 mp_pacing0;
+ u32 mp_pacing1;
+ u32 mp_pacing2;
+ u32 mp_pacing3;
+ u32 mp_threshold0;
+ u32 mp_threshold1;
+ u32 mp_threshold2;
+ u32 phy_ctrl0;
+};
+
+struct socfpga_sdram_rw_mgr_config {
+ u8 activate_0_and_1;
+ u8 activate_0_and_1_wait1;
+ u8 activate_0_and_1_wait2;
+ u8 activate_1;
+ u8 clear_dqs_enable;
+ u8 guaranteed_read;
+ u8 guaranteed_read_cont;
+ u8 guaranteed_write;
+ u8 guaranteed_write_wait0;
+ u8 guaranteed_write_wait1;
+ u8 guaranteed_write_wait2;
+ u8 guaranteed_write_wait3;
+ u8 idle;
+ u8 idle_loop1;
+ u8 idle_loop2;
+ u8 init_reset_0_cke_0;
+ u8 init_reset_1_cke_0;
+ u8 lfsr_wr_rd_bank_0;
+ u8 lfsr_wr_rd_bank_0_data;
+ u8 lfsr_wr_rd_bank_0_dqs;
+ u8 lfsr_wr_rd_bank_0_nop;
+ u8 lfsr_wr_rd_bank_0_wait;
+ u8 lfsr_wr_rd_bank_0_wl_1;
+ u8 lfsr_wr_rd_dm_bank_0;
+ u8 lfsr_wr_rd_dm_bank_0_data;
+ u8 lfsr_wr_rd_dm_bank_0_dqs;
+ u8 lfsr_wr_rd_dm_bank_0_nop;
+ u8 lfsr_wr_rd_dm_bank_0_wait;
+ u8 lfsr_wr_rd_dm_bank_0_wl_1;
+ u8 mrs0_dll_reset;
+ u8 mrs0_dll_reset_mirr;
+ u8 mrs0_user;
+ u8 mrs0_user_mirr;
+ u8 mrs1;
+ u8 mrs1_mirr;
+ u8 mrs2;
+ u8 mrs2_mirr;
+ u8 mrs3;
+ u8 mrs3_mirr;
+ u8 precharge_all;
+ u8 read_b2b;
+ u8 read_b2b_wait1;
+ u8 read_b2b_wait2;
+ u8 refresh_all;
+ u8 rreturn;
+ u8 sgle_read;
+ u8 zqcl;
+
+ u8 true_mem_data_mask_width;
+ u8 mem_address_mirroring;
+ u8 mem_data_mask_width;
+ u8 mem_data_width;
+ u8 mem_dq_per_read_dqs;
+ u8 mem_dq_per_write_dqs;
+ u8 mem_if_read_dqs_width;
+ u8 mem_if_write_dqs_width;
+ u8 mem_number_of_cs_per_dimm;
+ u8 mem_number_of_ranks;
+ u8 mem_virtual_groups_per_read_dqs;
+ u8 mem_virtual_groups_per_write_dqs;
+};
+
+struct socfpga_sdram_io_config {
+ u16 delay_per_opa_tap;
+ u8 delay_per_dchain_tap;
+ u8 delay_per_dqs_en_dchain_tap;
+ u8 dll_chain_length;
+ u8 dqdqs_out_phase_max;
+ u8 dqs_en_delay_max;
+ u8 dqs_en_delay_offset;
+ u8 dqs_en_phase_max;
+ u8 dqs_in_delay_max;
+ u8 dqs_in_reserve;
+ u8 dqs_out_reserve;
+ u8 io_in_delay_max;
+ u8 io_out1_delay_max;
+ u8 io_out2_delay_max;
+ u8 shift_dqs_en_when_shift_dqs;
+};
+
+struct socfpga_sdram_misc_config {
+ u32 reg_file_init_seq_signature;
+ u8 afi_rate_ratio;
+ u8 calib_lfifo_offset;
+ u8 calib_vfifo_offset;
+ u8 enable_super_quick_calibration;
+ u8 max_latency_count_width;
+ u8 read_valid_fifo_size;
+ u8 tinit_cntr0_val;
+ u8 tinit_cntr1_val;
+ u8 tinit_cntr2_val;
+ u8 treset_cntr0_val;
+ u8 treset_cntr1_val;
+ u8 treset_cntr2_val;
+};
+
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
+/* Register template: sdr::ctrlgrp::dramtiming1 */
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming2 */
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
+/* Register template: sdr::ctrlgrp::dramtiming3 */
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming4 */
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::lowpwrtiming */
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
+/* Register template: sdr::ctrlgrp::dramaddrw */
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
+/* Register template: sdr::ctrlgrp::dramifwidth */
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::dramdevwidth */
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramintr */
+#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
+#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
+/* Register template: sdr::ctrlgrp::staticcfg */
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
+#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
+#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::ctrlwidth */
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::cportwidth */
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::cportwmap */
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::cportrmap */
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::rfifocmap */
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::wfifocmap */
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::cportrdwr */
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::portcfg */
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::fifocfg */
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::mppriority */
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
+0x0000ffff
+/* Register template: sdr::ctrlgrp::remappriority */
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
+ (((x) << 10) & 0x00000c00)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
+ (((x) << 6) & 0x000000c0)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
+ (((x) << 8) & 0x00000100)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
+ (((x) << 9) & 0x00000200)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
+ (((x) << 4) & 0x00000030)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
+ (((x) << 2) & 0x0000000c)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
+ (((x) << 0) & 0x00000003)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::dramodt */
+#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
+#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
+#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
+#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
+/* Field instance: sdr::ctrlgrp::dramsts */
+#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
+#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
+
+/* SDRAM width macro for configuration with ECC */
+#define SDRAM_WIDTH_32BIT_WITH_ECC 40
+#define SDRAM_WIDTH_16BIT_WITH_ECC 24
+
+#endif
+#endif /* _SOCFPGA_SDRAM_GEN5_H_ */
# Copyright (C) 2014 Altera Corporation <www.altera.com>
ifdef CONFIG_ALTERA_SDRAM
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright Altera Corporation (C) 2014-2015
- */
-#include <common.h>
-#include <errno.h>
-#include <div64.h>
-#include <watchdog.h>
-#include <asm/arch/fpga_manager.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/system_manager.h>
-#include <asm/io.h>
-
-struct sdram_prot_rule {
- u32 sdram_start; /* SDRAM start address */
- u32 sdram_end; /* SDRAM end address */
- u32 rule; /* SDRAM protection rule number: 0-19 */
- int valid; /* Rule valid or not? 1 - valid, 0 not*/
-
- u32 security;
- u32 portmask;
- u32 result;
- u32 lo_prot_id;
- u32 hi_prot_id;
-};
-
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-static struct socfpga_sdr_ctrl *sdr_ctrl =
- (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
-
-/**
- * get_errata_rows() - Up the number of DRAM rows to cover entire address space
- * @cfg: SDRAM controller configuration data
- *
- * SDRAM Failure happens when accessing non-existent memory. Artificially
- * increase the number of rows so that the memory controller thinks it has
- * 4GB of RAM. This function returns such amount of rows.
- */
-static int get_errata_rows(const struct socfpga_sdram_config *cfg)
-{
- /* Define constant for 4G memory - used for SDRAM errata workaround */
-#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
- const unsigned long long memsize = MEMSIZE_4G;
- const unsigned int cs =
- ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
- const unsigned int rows =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
- const unsigned int banks =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
- const unsigned int cols =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
- const unsigned int width = 8;
-
- unsigned long long newrows;
- int bits, inewrowslog2;
-
- debug("workaround rows - memsize %lld\n", memsize);
- debug("workaround rows - cs %d\n", cs);
- debug("workaround rows - width %d\n", width);
- debug("workaround rows - rows %d\n", rows);
- debug("workaround rows - banks %d\n", banks);
- debug("workaround rows - cols %d\n", cols);
-
- newrows = lldiv(memsize, cs * (width / 8));
- debug("rows workaround - term1 %lld\n", newrows);
-
- newrows = lldiv(newrows, (1 << banks) * (1 << cols));
- debug("rows workaround - term2 %lld\n", newrows);
-
- /*
- * Compute the hamming weight - same as number of bits set.
- * Need to see if result is ordinal power of 2 before
- * attempting log2 of result.
- */
- bits = generic_hweight32(newrows);
-
- debug("rows workaround - bits %d\n", bits);
-
- if (bits != 1) {
- printf("SDRAM workaround failed, bits set %d\n", bits);
- return rows;
- }
-
- if (newrows > UINT_MAX) {
- printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
- return rows;
- }
-
- inewrowslog2 = __ilog2(newrows);
-
- debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
-
- if (inewrowslog2 == -1) {
- printf("SDRAM workaround failed, newrows %lld\n", newrows);
- return rows;
- }
-
- return inewrowslog2;
-}
-
-/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
-static void sdram_set_rule(struct sdram_prot_rule *prule)
-{
- u32 lo_addr_bits;
- u32 hi_addr_bits;
- int ruleno = prule->rule;
-
- /* Select the rule */
- writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
-
- /* Obtain the address bits */
- lo_addr_bits = prule->sdram_start >> 20ULL;
- hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
-
- debug("sdram set rule start %x, %d\n", lo_addr_bits,
- prule->sdram_start);
- debug("sdram set rule end %x, %d\n", hi_addr_bits,
- prule->sdram_end);
-
- /* Set rule addresses */
- writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
-
- /* Set rule protection ids */
- writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
- &sdr_ctrl->prot_rule_id);
-
- /* Set the rule data */
- writel(prule->security | (prule->valid << 2) |
- (prule->portmask << 3) | (prule->result << 13),
- &sdr_ctrl->prot_rule_data);
-
- /* write the rule */
- writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
-
- /* Set rule number to 0 by default */
- writel(0, &sdr_ctrl->prot_rule_rdwr);
-}
-
-static void sdram_get_rule(struct sdram_prot_rule *prule)
-{
- u32 addr;
- u32 id;
- u32 data;
- int ruleno = prule->rule;
-
- /* Read the rule */
- writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
- writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
-
- /* Get the addresses */
- addr = readl(&sdr_ctrl->prot_rule_addr);
- prule->sdram_start = (addr & 0xFFF) << 20;
- prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
-
- /* Get the configured protection IDs */
- id = readl(&sdr_ctrl->prot_rule_id);
- prule->lo_prot_id = id & 0xFFF;
- prule->hi_prot_id = (id >> 12) & 0xFFF;
-
- /* Get protection data */
- data = readl(&sdr_ctrl->prot_rule_data);
-
- prule->security = data & 0x3;
- prule->valid = (data >> 2) & 0x1;
- prule->portmask = (data >> 3) & 0x3FF;
- prule->result = (data >> 13) & 0x1;
-}
-
-static void
-sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
-{
- struct sdram_prot_rule rule;
- int rules;
-
- /* Start with accepting all SDRAM transaction */
- writel(0x0, &sdr_ctrl->protport_default);
-
- /* Clear all protection rules for warm boot case */
- memset(&rule, 0, sizeof(rule));
-
- for (rules = 0; rules < 20; rules++) {
- rule.rule = rules;
- sdram_set_rule(&rule);
- }
-
- /* new rule: accept SDRAM */
- rule.sdram_start = sdram_start;
- rule.sdram_end = sdram_end;
- rule.lo_prot_id = 0x0;
- rule.hi_prot_id = 0xFFF;
- rule.portmask = 0x3FF;
- rule.security = 0x3;
- rule.result = 0;
- rule.valid = 1;
- rule.rule = 0;
-
- /* set new rule */
- sdram_set_rule(&rule);
-
- /* default rule: reject everything */
- writel(0x3ff, &sdr_ctrl->protport_default);
-}
-
-static void sdram_dump_protection_config(void)
-{
- struct sdram_prot_rule rule;
- int rules;
-
- debug("SDRAM Prot rule, default %x\n",
- readl(&sdr_ctrl->protport_default));
-
- for (rules = 0; rules < 20; rules++) {
- rule.rule = rules;
- sdram_get_rule(&rule);
- debug("Rule %d, rules ...\n", rules);
- debug(" sdram start %x\n", rule.sdram_start);
- debug(" sdram end %x\n", rule.sdram_end);
- debug(" low prot id %d, hi prot id %d\n",
- rule.lo_prot_id,
- rule.hi_prot_id);
- debug(" portmask %x\n", rule.portmask);
- debug(" security %d\n", rule.security);
- debug(" result %d\n", rule.result);
- debug(" valid %d\n", rule.valid);
- }
-}
-
-/**
- * sdram_write_verify() - write to register and verify the write.
- * @addr: Register address
- * @val: Value to be written and verified
- *
- * This function writes to a register, reads back the value and compares
- * the result with the written value to check if the data match.
- */
-static unsigned sdram_write_verify(const u32 *addr, const u32 val)
-{
- u32 rval;
-
- debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
- writel(val, addr);
-
- debug(" Read and verify...");
- rval = readl(addr);
- if (rval != val) {
- debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
- addr, val, rval);
- return -EINVAL;
- }
-
- debug("correct!\n");
- return 0;
-}
-
-/**
- * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
- * @cfg: SDRAM controller configuration data
- *
- * Return the value of DRAM CTRLCFG register.
- */
-static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
-{
- const u32 csbits =
- ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
- u32 addrorder =
- (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
- SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
-
- u32 ctrl_cfg = cfg->ctrl_cfg;
-
- /*
- * SDRAM Failure When Accessing Non-Existent Memory
- * Set the addrorder field of the SDRAM control register
- * based on the CSBITs setting.
- */
- if (csbits == 1) {
- if (addrorder != 0)
- debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
- addrorder = 0;
- } else if (csbits == 2) {
- if (addrorder != 2)
- debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
- addrorder = 2;
- }
-
- ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
- ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
-
- return ctrl_cfg;
-}
-
-/**
- * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
- * @cfg: SDRAM controller configuration data
- *
- * Return the value of DRAM ADDRW register.
- */
-static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
-{
- /*
- * SDRAM Failure When Accessing Non-Existent Memory
- * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
- * log2(number of chip select bits). Since there's only
- * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
- * which is the same as "chip selects" - 1.
- */
- const int rows = get_errata_rows(cfg);
- u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
-
- return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
-}
-
-/**
- * sdr_load_regs() - Load SDRAM controller registers
- * @cfg: SDRAM controller configuration data
- *
- * This function loads the register values into the SDRAM controller block.
- */
-static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
-{
- const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
- const u32 dram_addrw = sdr_get_addr_rw(cfg);
-
- debug("\nConfiguring CTRLCFG\n");
- writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
-
- debug("Configuring DRAMTIMING1\n");
- writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
-
- debug("Configuring DRAMTIMING2\n");
- writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
-
- debug("Configuring DRAMTIMING3\n");
- writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
-
- debug("Configuring DRAMTIMING4\n");
- writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
-
- debug("Configuring LOWPWRTIMING\n");
- writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
-
- debug("Configuring DRAMADDRW\n");
- writel(dram_addrw, &sdr_ctrl->dram_addrw);
-
- debug("Configuring DRAMIFWIDTH\n");
- writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
-
- debug("Configuring DRAMDEVWIDTH\n");
- writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
-
- debug("Configuring LOWPWREQ\n");
- writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
-
- debug("Configuring DRAMINTR\n");
- writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
-
- debug("Configuring STATICCFG\n");
- writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
-
- debug("Configuring CTRLWIDTH\n");
- writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
-
- debug("Configuring PORTCFG\n");
- writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
-
- debug("Configuring FIFOCFG\n");
- writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
-
- debug("Configuring MPPRIORITY\n");
- writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
-
- debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
- writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
- writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
- writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
- writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
-
- debug("Configuring MPPACING_MPPACING_0\n");
- writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
- writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
- writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
- writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
-
- debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
- writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
- writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
- writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
-
- debug("Configuring PHYCTRL_PHYCTRL_0\n");
- writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
-
- debug("Configuring CPORTWIDTH\n");
- writel(cfg->cport_width, &sdr_ctrl->cport_width);
-
- debug("Configuring CPORTWMAP\n");
- writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
-
- debug("Configuring CPORTRMAP\n");
- writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
-
- debug("Configuring RFIFOCMAP\n");
- writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
-
- debug("Configuring WFIFOCMAP\n");
- writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
-
- debug("Configuring CPORTRDWR\n");
- writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
-
- debug("Configuring DRAMODT\n");
- writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
-
- debug("Configuring EXTRATIME1\n");
- writel(cfg->extratime1, &sdr_ctrl->extratime1);
-}
-
-/**
- * sdram_mmr_init_full() - Function to initialize SDRAM MMR
- * @sdr_phy_reg: Value of the PHY control register 0
- *
- * Initialize the SDRAM MMR.
- */
-int sdram_mmr_init_full(unsigned int sdr_phy_reg)
-{
- const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
- const unsigned int rows =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
- int ret;
-
- writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
-
- sdr_load_regs(cfg);
-
- /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
- writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
-
- /* only enable if the FPGA is programmed */
- if (fpgamgr_test_fpga_ready()) {
- ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
- cfg->fpgaport_rst);
- if (ret)
- return ret;
- }
-
- /* Restore the SDR PHY Register if valid */
- if (sdr_phy_reg != 0xffffffff)
- writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
-
- /* Final step - apply configuration changes */
- debug("Configuring STATICCFG\n");
- clrsetbits_le32(&sdr_ctrl->static_cfg,
- SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
- 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
-
- sdram_set_protection_config(0, sdram_calculate_size() - 1);
-
- sdram_dump_protection_config();
-
- return 0;
-}
-
-/**
- * sdram_calculate_size() - Calculate SDRAM size
- *
- * Calculate SDRAM device size based on SDRAM controller parameters.
- * Size is specified in bytes.
- */
-unsigned long sdram_calculate_size(void)
-{
- unsigned long temp;
- unsigned long row, bank, col, cs, width;
- const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
- const unsigned int csbits =
- ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
- const unsigned int rowbits =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
-
- temp = readl(&sdr_ctrl->dram_addrw);
- col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
-
- /*
- * SDRAM Failure When Accessing Non-Existent Memory
- * Use ROWBITS from Quartus/QSys to calculate SDRAM size
- * since the FB specifies we modify ROWBITs to work around SDRAM
- * controller issue.
- */
- row = readl(&sysmgr_regs->iswgrp_handoff[4]);
- if (row == 0)
- row = rowbits;
- /*
- * If the stored handoff value for rows is greater than
- * the field width in the sdr.dramaddrw register then
- * something is very wrong. Revert to using the the #define
- * value handed off by the SOCEDS tool chain instead of
- * using a broken value.
- */
- if (row > 31)
- row = rowbits;
-
- bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
-
- /*
- * SDRAM Failure When Accessing Non-Existent Memory
- * Use CSBITs from Quartus/QSys to calculate SDRAM size
- * since the FB specifies we modify CSBITs to work around SDRAM
- * controller issue.
- */
- cs = csbits;
-
- width = readl(&sdr_ctrl->dram_if_width);
-
- /* ECC would not be calculated as its not addressible */
- if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
- width = 32;
- if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
- width = 16;
-
- /* calculate the SDRAM size base on this info */
- temp = 1 << (row + bank + col);
- temp = temp * cs * (width / 8);
-
- debug("%s returns %ld\n", __func__, temp);
-
- return temp;
-}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ */
+#include <common.h>
+#include <errno.h>
+#include <div64.h>
+#include <watchdog.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+
+struct sdram_prot_rule {
+ u32 sdram_start; /* SDRAM start address */
+ u32 sdram_end; /* SDRAM end address */
+ u32 rule; /* SDRAM protection rule number: 0-19 */
+ int valid; /* Rule valid or not? 1 - valid, 0 not*/
+
+ u32 security;
+ u32 portmask;
+ u32 result;
+ u32 lo_prot_id;
+ u32 hi_prot_id;
+};
+
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+ (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
+/**
+ * get_errata_rows() - Up the number of DRAM rows to cover entire address space
+ * @cfg: SDRAM controller configuration data
+ *
+ * SDRAM Failure happens when accessing non-existent memory. Artificially
+ * increase the number of rows so that the memory controller thinks it has
+ * 4GB of RAM. This function returns such amount of rows.
+ */
+static int get_errata_rows(const struct socfpga_sdram_config *cfg)
+{
+ /* Define constant for 4G memory - used for SDRAM errata workaround */
+#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
+ const unsigned long long memsize = MEMSIZE_4G;
+ const unsigned int cs =
+ ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
+ const unsigned int rows =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+ const unsigned int banks =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
+ const unsigned int cols =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
+ const unsigned int width = 8;
+
+ unsigned long long newrows;
+ int bits, inewrowslog2;
+
+ debug("workaround rows - memsize %lld\n", memsize);
+ debug("workaround rows - cs %d\n", cs);
+ debug("workaround rows - width %d\n", width);
+ debug("workaround rows - rows %d\n", rows);
+ debug("workaround rows - banks %d\n", banks);
+ debug("workaround rows - cols %d\n", cols);
+
+ newrows = lldiv(memsize, cs * (width / 8));
+ debug("rows workaround - term1 %lld\n", newrows);
+
+ newrows = lldiv(newrows, (1 << banks) * (1 << cols));
+ debug("rows workaround - term2 %lld\n", newrows);
+
+ /*
+ * Compute the hamming weight - same as number of bits set.
+ * Need to see if result is ordinal power of 2 before
+ * attempting log2 of result.
+ */
+ bits = generic_hweight32(newrows);
+
+ debug("rows workaround - bits %d\n", bits);
+
+ if (bits != 1) {
+ printf("SDRAM workaround failed, bits set %d\n", bits);
+ return rows;
+ }
+
+ if (newrows > UINT_MAX) {
+ printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
+ return rows;
+ }
+
+ inewrowslog2 = __ilog2(newrows);
+
+ debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
+
+ if (inewrowslog2 == -1) {
+ printf("SDRAM workaround failed, newrows %lld\n", newrows);
+ return rows;
+ }
+
+ return inewrowslog2;
+}
+
+/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
+static void sdram_set_rule(struct sdram_prot_rule *prule)
+{
+ u32 lo_addr_bits;
+ u32 hi_addr_bits;
+ int ruleno = prule->rule;
+
+ /* Select the rule */
+ writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
+
+ /* Obtain the address bits */
+ lo_addr_bits = prule->sdram_start >> 20ULL;
+ hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
+
+ debug("sdram set rule start %x, %d\n", lo_addr_bits,
+ prule->sdram_start);
+ debug("sdram set rule end %x, %d\n", hi_addr_bits,
+ prule->sdram_end);
+
+ /* Set rule addresses */
+ writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
+
+ /* Set rule protection ids */
+ writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
+ &sdr_ctrl->prot_rule_id);
+
+ /* Set the rule data */
+ writel(prule->security | (prule->valid << 2) |
+ (prule->portmask << 3) | (prule->result << 13),
+ &sdr_ctrl->prot_rule_data);
+
+ /* write the rule */
+ writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
+
+ /* Set rule number to 0 by default */
+ writel(0, &sdr_ctrl->prot_rule_rdwr);
+}
+
+static void sdram_get_rule(struct sdram_prot_rule *prule)
+{
+ u32 addr;
+ u32 id;
+ u32 data;
+ int ruleno = prule->rule;
+
+ /* Read the rule */
+ writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
+ writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
+
+ /* Get the addresses */
+ addr = readl(&sdr_ctrl->prot_rule_addr);
+ prule->sdram_start = (addr & 0xFFF) << 20;
+ prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
+
+ /* Get the configured protection IDs */
+ id = readl(&sdr_ctrl->prot_rule_id);
+ prule->lo_prot_id = id & 0xFFF;
+ prule->hi_prot_id = (id >> 12) & 0xFFF;
+
+ /* Get protection data */
+ data = readl(&sdr_ctrl->prot_rule_data);
+
+ prule->security = data & 0x3;
+ prule->valid = (data >> 2) & 0x1;
+ prule->portmask = (data >> 3) & 0x3FF;
+ prule->result = (data >> 13) & 0x1;
+}
+
+static void
+sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
+{
+ struct sdram_prot_rule rule;
+ int rules;
+
+ /* Start with accepting all SDRAM transaction */
+ writel(0x0, &sdr_ctrl->protport_default);
+
+ /* Clear all protection rules for warm boot case */
+ memset(&rule, 0, sizeof(rule));
+
+ for (rules = 0; rules < 20; rules++) {
+ rule.rule = rules;
+ sdram_set_rule(&rule);
+ }
+
+ /* new rule: accept SDRAM */
+ rule.sdram_start = sdram_start;
+ rule.sdram_end = sdram_end;
+ rule.lo_prot_id = 0x0;
+ rule.hi_prot_id = 0xFFF;
+ rule.portmask = 0x3FF;
+ rule.security = 0x3;
+ rule.result = 0;
+ rule.valid = 1;
+ rule.rule = 0;
+
+ /* set new rule */
+ sdram_set_rule(&rule);
+
+ /* default rule: reject everything */
+ writel(0x3ff, &sdr_ctrl->protport_default);
+}
+
+static void sdram_dump_protection_config(void)
+{
+ struct sdram_prot_rule rule;
+ int rules;
+
+ debug("SDRAM Prot rule, default %x\n",
+ readl(&sdr_ctrl->protport_default));
+
+ for (rules = 0; rules < 20; rules++) {
+ rule.rule = rules;
+ sdram_get_rule(&rule);
+ debug("Rule %d, rules ...\n", rules);
+ debug(" sdram start %x\n", rule.sdram_start);
+ debug(" sdram end %x\n", rule.sdram_end);
+ debug(" low prot id %d, hi prot id %d\n",
+ rule.lo_prot_id,
+ rule.hi_prot_id);
+ debug(" portmask %x\n", rule.portmask);
+ debug(" security %d\n", rule.security);
+ debug(" result %d\n", rule.result);
+ debug(" valid %d\n", rule.valid);
+ }
+}
+
+/**
+ * sdram_write_verify() - write to register and verify the write.
+ * @addr: Register address
+ * @val: Value to be written and verified
+ *
+ * This function writes to a register, reads back the value and compares
+ * the result with the written value to check if the data match.
+ */
+static unsigned sdram_write_verify(const u32 *addr, const u32 val)
+{
+ u32 rval;
+
+ debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
+ writel(val, addr);
+
+ debug(" Read and verify...");
+ rval = readl(addr);
+ if (rval != val) {
+ debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
+ addr, val, rval);
+ return -EINVAL;
+ }
+
+ debug("correct!\n");
+ return 0;
+}
+
+/**
+ * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
+ * @cfg: SDRAM controller configuration data
+ *
+ * Return the value of DRAM CTRLCFG register.
+ */
+static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
+{
+ const u32 csbits =
+ ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
+ u32 addrorder =
+ (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
+ SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
+
+ u32 ctrl_cfg = cfg->ctrl_cfg;
+
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
+ * Set the addrorder field of the SDRAM control register
+ * based on the CSBITs setting.
+ */
+ if (csbits == 1) {
+ if (addrorder != 0)
+ debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
+ addrorder = 0;
+ } else if (csbits == 2) {
+ if (addrorder != 2)
+ debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
+ addrorder = 2;
+ }
+
+ ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
+ ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
+
+ return ctrl_cfg;
+}
+
+/**
+ * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
+ * @cfg: SDRAM controller configuration data
+ *
+ * Return the value of DRAM ADDRW register.
+ */
+static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
+{
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
+ * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
+ * log2(number of chip select bits). Since there's only
+ * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
+ * which is the same as "chip selects" - 1.
+ */
+ const int rows = get_errata_rows(cfg);
+ u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
+
+ return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
+}
+
+/**
+ * sdr_load_regs() - Load SDRAM controller registers
+ * @cfg: SDRAM controller configuration data
+ *
+ * This function loads the register values into the SDRAM controller block.
+ */
+static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
+{
+ const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
+ const u32 dram_addrw = sdr_get_addr_rw(cfg);
+
+ debug("\nConfiguring CTRLCFG\n");
+ writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
+
+ debug("Configuring DRAMTIMING1\n");
+ writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
+
+ debug("Configuring DRAMTIMING2\n");
+ writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
+
+ debug("Configuring DRAMTIMING3\n");
+ writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
+
+ debug("Configuring DRAMTIMING4\n");
+ writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
+
+ debug("Configuring LOWPWRTIMING\n");
+ writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
+
+ debug("Configuring DRAMADDRW\n");
+ writel(dram_addrw, &sdr_ctrl->dram_addrw);
+
+ debug("Configuring DRAMIFWIDTH\n");
+ writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
+
+ debug("Configuring DRAMDEVWIDTH\n");
+ writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
+
+ debug("Configuring LOWPWREQ\n");
+ writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
+
+ debug("Configuring DRAMINTR\n");
+ writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
+
+ debug("Configuring STATICCFG\n");
+ writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
+
+ debug("Configuring CTRLWIDTH\n");
+ writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
+
+ debug("Configuring PORTCFG\n");
+ writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
+
+ debug("Configuring FIFOCFG\n");
+ writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
+
+ debug("Configuring MPPRIORITY\n");
+ writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
+
+ debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
+ writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
+ writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
+ writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
+ writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
+
+ debug("Configuring MPPACING_MPPACING_0\n");
+ writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
+ writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
+ writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
+ writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
+
+ debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
+ writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
+ writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
+ writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
+
+ debug("Configuring PHYCTRL_PHYCTRL_0\n");
+ writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
+
+ debug("Configuring CPORTWIDTH\n");
+ writel(cfg->cport_width, &sdr_ctrl->cport_width);
+
+ debug("Configuring CPORTWMAP\n");
+ writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
+
+ debug("Configuring CPORTRMAP\n");
+ writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
+
+ debug("Configuring RFIFOCMAP\n");
+ writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
+
+ debug("Configuring WFIFOCMAP\n");
+ writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
+
+ debug("Configuring CPORTRDWR\n");
+ writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
+
+ debug("Configuring DRAMODT\n");
+ writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
+
+ debug("Configuring EXTRATIME1\n");
+ writel(cfg->extratime1, &sdr_ctrl->extratime1);
+}
+
+/**
+ * sdram_mmr_init_full() - Function to initialize SDRAM MMR
+ * @sdr_phy_reg: Value of the PHY control register 0
+ *
+ * Initialize the SDRAM MMR.
+ */
+int sdram_mmr_init_full(unsigned int sdr_phy_reg)
+{
+ const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
+ const unsigned int rows =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+ int ret;
+
+ writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
+
+ sdr_load_regs(cfg);
+
+ /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
+ writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
+
+ /* only enable if the FPGA is programmed */
+ if (fpgamgr_test_fpga_ready()) {
+ ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
+ cfg->fpgaport_rst);
+ if (ret)
+ return ret;
+ }
+
+ /* Restore the SDR PHY Register if valid */
+ if (sdr_phy_reg != 0xffffffff)
+ writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
+
+ /* Final step - apply configuration changes */
+ debug("Configuring STATICCFG\n");
+ clrsetbits_le32(&sdr_ctrl->static_cfg,
+ SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
+ 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
+
+ sdram_set_protection_config(0, sdram_calculate_size() - 1);
+
+ sdram_dump_protection_config();
+
+ return 0;
+}
+
+/**
+ * sdram_calculate_size() - Calculate SDRAM size
+ *
+ * Calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ */
+unsigned long sdram_calculate_size(void)
+{
+ unsigned long temp;
+ unsigned long row, bank, col, cs, width;
+ const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
+ const unsigned int csbits =
+ ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
+ const unsigned int rowbits =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+
+ temp = readl(&sdr_ctrl->dram_addrw);
+ col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
+
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
+ * Use ROWBITS from Quartus/QSys to calculate SDRAM size
+ * since the FB specifies we modify ROWBITs to work around SDRAM
+ * controller issue.
+ */
+ row = readl(&sysmgr_regs->iswgrp_handoff[4]);
+ if (row == 0)
+ row = rowbits;
+ /*
+ * If the stored handoff value for rows is greater than
+ * the field width in the sdr.dramaddrw register then
+ * something is very wrong. Revert to using the the #define
+ * value handed off by the SOCEDS tool chain instead of
+ * using a broken value.
+ */
+ if (row > 31)
+ row = rowbits;
+
+ bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
+
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
+ * Use CSBITs from Quartus/QSys to calculate SDRAM size
+ * since the FB specifies we modify CSBITs to work around SDRAM
+ * controller issue.
+ */
+ cs = csbits;
+
+ width = readl(&sdr_ctrl->dram_if_width);
+
+ /* ECC would not be calculated as its not addressible */
+ if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
+ width = 32;
+ if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
+ width = 16;
+
+ /* calculate the SDRAM size base on this info */
+ temp = 1 << (row + bank + col);
+ temp = temp * cs * (width / 8);
+
+ debug("%s returns %ld\n", __func__, temp);
+
+ return temp;
+}
projects / u-boot / commitdiff