David Brownell [Fri, 18 Jan 2008 20:55:00 +0000 (12:55 -0800)]
use correct at91rm9200 register name
This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2. This
makes code use the register name from chip datasheets.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Timur Tabi [Fri, 14 Mar 2008 22:45:29 +0000 (17:45 -0500)]
Add support for setting the I2C bus speed in fsl_i2c.c
Add support to the Freescale I2C driver (fsl_i2c.c) for setting and querying
the I2C bus speed. Current 8[356]xx boards define the CFG_I2C_SPEED macro,
but fsl_i2c.c ignores it and uses conservative value when programming the
I2C bus speed.
Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
Dave Liu [Wed, 26 Mar 2008 14:55:32 +0000 (22:55 +0800)]
drivers: add the support for Freescale SATA controller
Add the Freescale on-chip SATA controller driver to u-boot,
The SATA controller is used on the 837x and 8315 targets,
The driver can be used to load kernel, fs and dtb.
The features list:
- 1.5/3 Gbps link speed
- LBA48, LBA28 support
- DMA and FPDMA support
- Two ports support
Dave Liu [Wed, 26 Mar 2008 14:50:45 +0000 (22:50 +0800)]
ata: make the ata_piix driver using new SATA framework
original ata_piix driver is using IDE framework, not real
SATA framework. For now, the ata_piix driver is only used
by x86 sc520_cdp board. This patch makes the ata_piix driver
use the new SATA framework, so
- remove the duplicated command stuff
- remove the CONFIG_CMD_IDE define in the sc520_cdp.h
- add the CONFIG_CMD_SATA define to sc520_cdp.h
Dave Liu [Wed, 26 Mar 2008 14:47:06 +0000 (22:47 +0800)]
ata: merge the ata_piix driver
move the cmd_sata.c from common/ to drivers/ata_piix.c,
the cmd_sata.c have some part of ata_piix controller drivers.
consolidate the driver to have better framework.
USB, Storage: fix a bug introduced in commit f6b44e0e4d18fe507833a0f76d24a9aa72c123f1 that will cause usb_stor_info
to only print only information on one storage device, but not for
multiple.
Kumar Gala [Wed, 26 Mar 2008 13:34:25 +0000 (08:34 -0500)]
85xx: Update multicore boot mechanism to ePAPR v0.81 spec
The following changes are needed to be inline with ePAPR v0.81:
* r4, r5 and now always set to 0 on boot release
* r7 is used to pass the size of the initial map area (IMA)
* EPAPR_MAGIC value changed for book-e processors
* changes in the spin table layout
* spin table supports a 64-bit physical release address
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jon Loeliger [Wed, 19 Mar 2008 20:02:07 +0000 (15:02 -0500)]
FSL: Clean up board/freescale/common/Makefile
Each file that can be built here now follows some
CONFIG_ option so that they are appropriately built
or not, as needed. And CONFIG_ defines were added
to various board config files to make sure that happens.
The other board/freescale/*/Makefiles no longer need
to reach up and over into ../common to build their
individually needed files any more.
Boards that are CDS specific were renamed with cds_ prefix.
James Yang [Tue, 12 Feb 2008 22:35:07 +0000 (16:35 -0600)]
85xx: Expand CCSR space with more DDR controller registers.
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
James Yang [Sat, 9 Feb 2008 00:05:08 +0000 (18:05 -0600)]
85xx: Speed up get_ddr_freq() and get_bus_freq()
get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were
called. However, get_sys_info() recalculates extraneous information when
called each time. Have get_ddr_freq() and get_bus_freq() return memoized
values from global_data instead.
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
James Yang [Fri, 8 Feb 2008 22:44:53 +0000 (16:44 -0600)]
85xx: get_tbclk() speed up and rounding fix
Speed up get_tbclk() by referencing pre-computed bus clock
frequency value from global data instead of sys_info_t. Fix
rounding of result to nearest; previously it was rounding
upwards.
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Andy Fleming [Wed, 6 Feb 2008 07:19:40 +0000 (01:19 -0600)]
Update SVR numbers to expand support
FSL has taken to using SVR[16:23] as an SOC sub-version field. This
is used to distinguish certain variants within an SOC family. To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value. We also add SVR numbers for all
of the current variants. Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Anton Vorontsov [Fri, 14 Mar 2008 20:20:18 +0000 (23:20 +0300)]
83xx/fdt_support: let user specifiy FSL USB Dual-Role controller role
Linux understands "host" (default), "peripheral" and "otg" (broken).
Though, U-Boot doesn't restrict dr_mode variable to these values (think
of renames in future).
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Joe D'Abbraccio [Mon, 24 Mar 2008 17:00:59 +0000 (13:00 -0400)]
Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock
With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.
Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
The following changes are based on kernel UCC ethernet performance:
1. Make the CSB bus pipeline depth as 4, and enable the repeat mode
2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT
switch to enable this setting.
The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:
3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting
previously.
5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on
Twr=15ns, and this was already the setting in DDR_MODE)
6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
Trp=15ns)
7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
Tras=40ns)
8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
Trcd=15ns)
9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on
Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based
on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
on CL=3 and WL=2).
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
Timur Tabi [Fri, 8 Feb 2008 19:15:55 +0000 (13:15 -0600)]
83xx: Add Vitesse VSC7385 firmware uploading
Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
Cleaned up the board header files to make selecting the VSC7385 easier to
control.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Timur Tabi [Fri, 8 Feb 2008 19:15:54 +0000 (13:15 -0600)]
NET: Add Vitesse VSC7385 firmware uploading
The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX
and other boards. A small firwmare must be uploaded to its on-board memory
before it can be enabled. This patch adds the code which uploads firmware
(but not the firmware itself).
Previously, this feature was provided by a U-Boot application that was
made available only on Freescale BSPs. The VSC7385 firmware must still
be obtained separately, but at least there is no longer a need for a separate
application.
Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
Jerry Van Baren [Sat, 22 Mar 2008 18:23:49 +0000 (14:23 -0400)]
Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_T
These defines embedded the u-boot env variables and/or the bd_t structure
in the fdt blob. The conclusion of discussion on the u-boot email list
was that embedding these in the fdt blob is not useful: there are better
ways of passing the data (in fact, the fdt blob itself replaces the
bd_t struct).
The only board that enables these is the stxxtc and they don't appear
to be used by linux.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
Kyungmin Park [Sun, 16 Mar 2008 23:54:06 +0000 (08:54 +0900)]
Add Flex-OneNAND booting support
Flex-OneNAND is a monolithic integrated circuit with a NAND Flash array
using a NOR Flash interface. This on-chip integration enables system designers
to reduce external system logic and use high-density NAND Flash
in applications that would otherwise have to use more NOR components.
Flex-OneNAND enables users to configure to partition it into SLC and MLC areas
in more flexible way. While MLC area of Flex-OneNAND can be used to store data
that require low reliability and high density, SLC area of Flex-OneNAND
to store data that need high reliability and high performance. Flex-OneNAND
can let users take advantage of storing these two different types of data
into one chip, which is making Flex-OneNAND more cost- and space-effective.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
goda.yusuke [Wed, 5 Mar 2008 08:08:20 +0000 (17:08 +0900)]
net: Divided code of NE2000 ethernet driver
There are more devices of the NE2000 base.
A present code is difficult for us to support more devices.
To support more NE2000 clone devices, separated the function.
Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Mike Frysinger [Mon, 25 Feb 2008 04:58:13 +0000 (23:58 -0500)]
net/Blackfin: move on-chip MAC driver into drivers/net/
The Blackfin on-chip MAC driver was being managed in the BF537-STAMP board
directory, but it is not board specific, so relocate it to the drivers dir
so that other Blackfin ports can utilize it.
Mike Frysinger [Mon, 25 Feb 2008 04:52:35 +0000 (23:52 -0500)]
smc91111: use SSYNC() rather than asm(ssync) for Blackfin
Since the "ssync" instruction may have hardware anomalies associated with
it, have the smc91111 driver use the SSYNC macro rather than invoking it
directly. We workaround all the anomalies via this macro.
Kumar Gala [Fri, 15 Feb 2008 21:16:18 +0000 (15:16 -0600)]
ppc: Allow boards to specify how much memory they can map
For historical reasons we limited the stack to 256M because some boards
could only map that much via BATS. However newer boards are capable of
mapping more memory (for example 85xx is capble of doing up to 2G).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 15 Feb 2008 02:44:42 +0000 (20:44 -0600)]
Add setexpr command
Add a simple expr style command that will set an env variable as the result
of the command. This allows us to do simple math in shell. The following
operations are supported: &, |, ^, +, -, *, /.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add setup_c0_status from Linux. For the moment we disable interrupts, set
CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for
reset-time configuration and will work well across most processors.
We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you
don't need to do Hit_Invalidate_I, but flush_cache() needs it since this
function is used not only in U-Boot specfic programs but also at loading
target binaries.
Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I
again per a loop for I-cache initialization. But according to 'See MIPS
Run', we're encouraged to use three separate loops rather than combining
them *for both I- and D-cache*. This patch tries to fix this.
In accordance with fixing above, mips_init_[id]cache are separated from
mips_cache_reset(), and rewrite cache loops are completely rewritten with
useful macros.
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