Bin Meng [Thu, 12 Apr 2018 05:02:15 +0000 (22:02 -0700)]
bios: vesa: Guard setting vesa mode with CONFIG_FRAMEBUFFER_SET_VESA_MODE
If CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set, don't switch
graphics card to VESA mode. This applies to both native mode
and emulator mode of running the VGA BIOS.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 12 Apr 2018 05:02:12 +0000 (22:02 -0700)]
elf: Clean up the ELF header file
Fix various style violations in elf.h
- use correct comment format if the comment fits in just one line
- remove the ending period for the one-line comment
- use tab for the indention instead of space
- put the opening brace at the same line of a typedef/union
- remove <name> in a 'typedef struct' for consistency
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Bin Meng [Thu, 12 Apr 2018 05:02:08 +0000 (22:02 -0700)]
bootvx: x86: Explicitly clear the bootloader image size
VxWorks bootloader stores its size at a pre-defined offset @ 0x5004.
Later when VxWorks kernel boots up and system memory information is
retrieved from the E820 table, the bootloader size will be subtracted
from the total system memory size to calculate the size of available
memory for the OS.
Explicitly clear the bootloader image size otherwise if memory
at this offset happens to contain some garbage data, the final
available memory size for the kernel is insane.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 12 Apr 2018 05:02:07 +0000 (22:02 -0700)]
bootvx: x86: Prepare e820 related stuff from the given kernel memory base address
At present two environment variables 'e820data'/'e820info' are required
to boot a VxWorks x86 kernel, but this is superfluous. The offset of
these two tables are actually at a fixed offset from the kernel memory
base address and we can provide the kernel memory base address to U-Boot
via only one variable 'vx_phys_mem_base'.
Note as it name indicates, the physical address should be provided.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Ivan Gorinov [Fri, 6 Apr 2018 21:43:04 +0000 (14:43 -0700)]
x86: Add 64-bit memory-mapped I/O functions
Add readq() and writeq() definitions for x86.
Please note: in 32-bit code readq/writeq will generate two 32-bit
memory access instructions instead of one atomic 64-bit operation.
Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Each imx image is created by a separate sub-make and during this process
the mkimage config file is run though cpp.
The cpp output is to the same file no matter what imx image is being
created.
This means if two imx images are generated in parallel they will attempt
to independently produce the same pre-processed mkimage config file at
the same time.
Avoid the problem by making the pre-processed config file name unique
based on the imx image it will be used in. This way each image will
create a unique config file and they won't clobber each other when run
in parallel.
This should fixed the build bug referenced in b5b0e4e3 ("imximage:
Remove failure when no IVT offset is found").
Cc: Breno Lima <breno.lima@nxp.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Working with HAB on the i.MX7 we've encountered a case where a board that
successfully authenticates u-boot when booting Linux via OPTEE subsequently
fails to properly bring up the RTC.
The RTC registers live in the low-power block of the Secure Non-Volatile
Storage (SNVS) block.
The root cause of the error has been traced to the HAB handing off the
SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the
Non-Privileged Software Access Enable bit is zero. In ordinary
circumstances this is OK since we typically do not run in TZ mode, however
when we boot via HAB and enablng TrustZone, it is required to set
HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have
sufficient permissions to manipulate the SNVS-LP block.
On our reference board it is the difference between Linux doing this:
root@imx7s-warp-mbl:~# dmesg | grep rtc
snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034
snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038
snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000
snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004
snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered 30370000.snvs:snvs-rtc-lp as rtc0
snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864)
and doing this:
root@imx7s-warp-mbl:~# dmesg | grep rtc
snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034
snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038
snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000
snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004
snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110
snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110
hctosys: unable to open rtc device (rtc0)
Note bit 1 of LPCR is not set in the second case and is set in the first
case and that bit 31 of HPCOMR is set in the second case but not in the
first.
Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone
and continue onto the kernel. The kernel then has the necessary permissions
to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in
contrast - in the failing case the non-privileged kernel cannot do so.
This patch adds a simple init_snvs() call which sets the permission-bit
called from soc.c for the i.MX7. It may be possible, safe and desirable to
perform this on other i.MX processors but for now this is only tested on
i.MX7 as working.
Bryan O'Donoghue [Mon, 26 Mar 2018 14:36:46 +0000 (15:36 +0100)]
imx: hab: Provide hab_auth_img_or_fail command
This patch adds hab_auth_img_or_fail() a command line function that
encapsulates a common usage of authenticate and failover, namely if
authenticate image fails, then drop to BootROM USB recovery mode.
For secure-boot systems, this type of locked down behavior is important to
ensure no unsigned images can be run.
It's possible to script this logic but, when done over and over again the
environment starts get very complex and repetitive, reducing that script
repetition down to a command line function makes sense.
Bryan O'Donoghue [Mon, 26 Mar 2018 14:36:45 +0000 (15:36 +0100)]
imximage: Encase majority of header in __ASSEMBLY__ declaration
Subsequent patches will want to include imageimage.h but in doing so
include it on an assembly compile path causing a range of compile errors.
Fix the errors pre-emptively by encasing the majority of the declarations
in imximage.h inside an ifdef __ASSEMBLY__ block.
Bryan O'Donoghue [Mon, 26 Mar 2018 14:27:34 +0000 (15:27 +0100)]
warp7: Set u-boot serial# based on OTP value
u-boot has a standard "serial#" environment variable that is suitable
for storing the iSerial number we will supply via the USB device
descriptor. serial# is automatically picked up by the disk subsystem in
u-boot - thus providing a handy unique identifier in /dev/disk/by-id as
detailed below.
Storing the hardware serial identifier in serial# means we can change the
serial# if we want before USB enumeration - thus making iSerial automatic
via OTP but overridable if necessary.
This patch reads the defined OTP fuse and sets environment variable
"serial#" to the value read.
With this patch in place the USB mass storage device will appear in
/dev/disk/by-id with a unique name based on the OTP value. For example
Bryan O'Donoghue [Mon, 26 Mar 2018 14:27:33 +0000 (15:27 +0100)]
imx: mx7: Add comment to describe OTP TESTER registers
The tester registers provide a unique chip-level identifier which
get_board_serial() returns in a "struct tag_serialnr".
This patch documents the properties of the registers; in summary.
31:0 OCOTP_TESTER0 (most significant)
- FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
OCOTP_TESTER1 (least significant)
31:24
- The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique
ID
23:16
- The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique
ID
15:11
- The wafer number of the wafer on which the device was fabricated/SJC
CHALLENGE/ Unique ID
10:0
- FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
The 64 bits of data generate a unique serial number per-chip.
Marek Vasut [Fri, 30 Mar 2018 01:04:43 +0000 (03:04 +0200)]
ARM: mx6: ddr: Add write leveling correction code
When the DDR calibration is enabled, a situation may happen that it
will fail on a few select boards out of a whole production lot. In
particular, after the first write leveling stage, the MPWLDECTRLx
registers will contain a value 0x1nn , for nn usually being 0x7f or
slightly lower.
What this means is that the HW write leveling detected that the DQS
rising edge on one or more bundles arrives slightly _after_ CLK and
therefore when the DDR DRAM samples CLK on the DQS rising edge, the
CLK signal is already high (cfr. AN4467 rev2 Figure 7 on page 18).
The HW write leveling then ends up adding almost an entire cycle (thus
the 0x17f) to the DQS delay, which indeed aligns it, but also triggers
subsequent calibration failure in DQS gating due to this massive offset.
There are two observations here:
- If the MPWLDECTRLx value is corrected from 0x17f to 0x0 , then the
DQS gating passes, the entire calibration passes as well and the
DRAM is perfectly stable even under massive load.
- When using the NXP DRAM calibrator for iMX6/7, the value 0x17f or so
in MPWLDECTRx register is not there, but it is replaced by 0x0 as one
would expect.
Someone from NXP finally explains why, quoting [1]:
"
Having said all that, the DDR Stress Test does something that we
do not advertise to the users. The Stress Test iself looks at the
values of the MPWLDECTRL0/1 fields before reporting results, and
if it sees any filed with a value greater than 200/256 delay
(reported as half-cycle = 0x1 and ABS_OFFSET > 0x48), the DDR
Stress test will reset the Write Leveling delay for this lane
to 0x000 and not report it in the log.
The reason that the DDR Stress test does this is because a delay
of more than 78% a clock cycle means that the DQS edge is arriving
within the JEDEC tolerence of 25% of the clock edge. In most cases,
DQS is arriving < 5% tCK of the SDCLK edge in the early case, and
it does not make sense to delay the DQS strobe almost a full clock
cycle and add extra latency to each Write burst just to make the
two edges align exactly. In this case, we are guilty of making a
decision for the customer without telling them we are doing it so
that we don't have to provide the above explanation to every customer.
They don't need to know it.
"
This patch adds the correction described above, that is if the MPWLDECTRx
value is over 0x148, the value is corrected back to 0x0.
[1] https://community.nxp.com/thread/456246
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
Rasmus Villemoes [Fri, 23 Mar 2018 11:08:03 +0000 (12:08 +0100)]
tools/imximage: use 0x prefix in HAB Blocks line
The u-boot-ivt.img.log file contains 0x prefixes in the HAB Blocks line,
while the SPL.log does not. For consistency, and to make it easier to
extract and put into a .csf file for use with NXP's code signing tool,
add 0x prefixes here.
Rasmus Villemoes [Fri, 23 Mar 2018 11:08:02 +0000 (12:08 +0100)]
Makefile: always preserve output for images that can contain HAB Blocks
The current makefile logic disables creation of the
SPL.log/u-boot-ivt.img.log etc. files when V=1 is given on the command
line, the rationale presumably being that the user wants and gets the
information on the console.
However, from general principles, I don't think a higher V= level
should affect which build artifacts get generated (and certainly
shouldn't produce fewer). Concretely, it's also a problem that when
doing a V=1 build in a terminal, the relevant HAB blocks lines easily
drown in all the other V=1 output.
Moreover, build systems such as Yocto by default pass V=1, so in that
case the information gets hidden away in the do_compile log file, making
it nigh impossible to create a recipe for creating signed U-boot images
- I don't want to disable V=1, because having verbose output in the log
file is valuable when things go wrong, but OTOH trying to go digging in
the do_compile log file (and getting exactly the right lines) is not
pleasant to even think about.
So change the logic so that for V=0, the mkimage output is redirected
to MKIMAGEOUTPUT (which is also the current behaviour), while for any
other value of V, we _additionally_ write the information to make's
stdout, whatever that might be.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Tested-by: Breno Lima <breno.lima@nxp.com>
Marek Vasut [Fri, 13 Apr 2018 22:01:19 +0000 (00:01 +0200)]
ARM: rmobile: Zap CONFIG_MMC_RENESAS_TUNING
Drop the CONFIG_MMC_RENESAS_TUNING symbol from Gen3 configs.
This symbol is no longer used after the Matsushita SDHI driver,
instead the renesas-sdhi driver uses CONFIG_MMC_HS200_SUPPORT
to discern whether the tuning support should be compiled in.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
--
V2: Submit this on top of configs which are actually in mainline
Marek Vasut [Fri, 13 Apr 2018 21:13:00 +0000 (23:13 +0200)]
ARM: rmobile: Convert TPL to SPL
There is currently no use for building the SPL anymore, since the
SPI loader can easily be replaced by TPL and TPL does load U-Boot
directly. Upgrade TPL to SPL and replace what used to be SPL with
it. This way we build the U-Boot sources only twice, not thrice.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Fri, 13 Apr 2018 13:51:13 +0000 (15:51 +0200)]
ARM: rmobile: Shrink the TPL
Shrink the TPL by using tiny printf and tiny memset by default.
This removes the biggest symbol -- vsnprintf_internal -- from
the TPL and reduces the text segment by about 2 kiB.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Thu, 12 Apr 2018 13:23:46 +0000 (15:23 +0200)]
ARM: rmobile: Update H2 Stout
The H2 Stout port was broken since some time. This patch updates
the H2 Stout port to use modern frameworks, DM, DT probing, SPL
and TPL for the preloading and puts it on par with the M2 Porter
board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tom Rini [Tue, 10 Apr 2018 15:51:53 +0000 (11:51 -0400)]
configs: Fixup some CPSW-related items
- For am335x_pdu001 we do not want the CPSW driver, drop it
- Re-sync the defconfig for am43xx_evm_rtconly as it came in after the
patch that converted CPSW to Kconfig was posted but before it was
applied.
- Drop empty section / comments from pengwyn
- Drop empty section / comments from baltos and drop unused
CONFIG_SPL_NET_VCI_STRING (it does not enable CONFIG_SPL_NET_SUPPORT
currently and SPL_NET_VCI_STRING has been migrated already).
Cc: Felix Brack <fb@ltec.ch> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Lothar Felten <lothar.felten@gmail.com> Fixes: f02b8d17619f ("Migrate CONFIG_DRIVER_TI_CPSW to Kconfig") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Felix Brack <fb@ltec.ch> Tested-by: Felix Brack <fb@ltec.ch>
Joe Hershberger [Fri, 30 Mar 2018 16:52:16 +0000 (11:52 -0500)]
net: phy: Don't limit phy addresses by default
Some boards expect to find more than one phy while other boards are old
and need to be limited to a specific phy address. Only limit the phy
address for boards that opt in.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Joe Hershberger [Fri, 13 Apr 2018 20:26:40 +0000 (15:26 -0500)]
xilinx: Only enable dist boot pxe when DHCP is enabled
Otherwise, we see this:
In file included from include/configs/zynq-common.h:183:0,
from include/config.h:5,
from include/common.h:21,
from env/common.c:11:
include/config_distro_bootcmd.h:319:2: error: expected ?}? before ?BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE?
BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
^
include/config_distro_bootcmd.h:319:2: note: in definition of macro ?BOOTENV_DEV_NAME_PXE?
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Joe Hershberger [Fri, 13 Apr 2018 20:26:37 +0000 (15:26 -0500)]
net: Make the BOOTP options default
The BOOTP options used to be and should still be default for all boards
with CMD_NET enabled. One should not be forced to use DISTRO_DEFAULTS to
get them.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Duncan Hare <dh@synoia.com>
Joe Hershberger [Fri, 13 Apr 2018 20:26:35 +0000 (15:26 -0500)]
net: Add the BOOTP_DNS2 option to Kconfig
Commit 3b3ea2c56ec4bc5 ("Kconfig: cmd: Make networking command dependent on NET")
removed the help documentation from the README but didn't add it back to Kconfig.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Duncan Hare <dh@synoia.com>
Joe Hershberger [Fri, 13 Apr 2018 20:26:30 +0000 (15:26 -0500)]
net: Make CMD_NET a menuconfig
Previously, CMD_NET was an alias for 2 commands (bootp and tftpboot) and
they we not able to be disabled. Separate out those 2 commands and move
CMD_NET up to the menu level, which more accurately represents the code.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Duncan Hare <dh@synoia.com>
Ye Li [Wed, 28 Mar 2018 12:54:16 +0000 (20:54 +0800)]
net: fec: Fix issue in DM probe timeout
Since the probe function has changed to reset FEC controller prior than
setup PHY. If reset FEC controller timeout, the priv->phydev is not
initialized, so can't free it.
Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Peng Fan [Wed, 28 Mar 2018 12:54:14 +0000 (20:54 +0800)]
net: fec: sharing MDIO for two enet controllers
On i.MX6SX, 6UL and 7D, there are two enet controllers each has a
MDIO port. But Some boards share one MDIO port for the two enets. So
introduce a configuration CONFIG_FEC_MXC_MDIO_BASE to indicate
the MDIO port for sharing.
In Kconfig, user needs enable CONFIG_FEC_MXC_SHARE_MDIO first to enter
the CONFIG_FEC_MXC_MDIO_BASE.
To i.MX28, adapt to use the new config
Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Fabio Estevam <fabio.estevam@nxp.com>
Peng Fan [Wed, 28 Mar 2018 12:54:13 +0000 (20:54 +0800)]
net: fec: set dev->seq to priv->dev_id
To platforms has two enet interface, using dev->seq could
avoid conflict.
i.MX6UL/ULL evk board net get the wrong MAC address from fuse,
eth1 get MAC0 address, eth0 get MAC1 address from fuse. Set the
priv->dev_id to device->seq as the real net interface alias id then
.fec_get_hwaddr() read the related MAC address from fuse.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Ye Li [Wed, 28 Mar 2018 12:54:11 +0000 (20:54 +0800)]
net: fec_mxc: Fix DM driver issue in recv
When using ethernet DM driver, the recv interface has a
change with non-DM interface, that driver needs to set
the packet pointer and provide it to upper layer to process.
In fec driver, the fecmxc_recv functions does not handle the
packet pointer parameter. This may cause crash in upper layer
processing because the packet pointer is not set.
This patch allocates a buffer for the packet pointer and free it
through free_pkt interface.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Matt Pelland [Tue, 27 Mar 2018 17:18:25 +0000 (13:18 -0400)]
net: mvneta: support setting hardware address
mvneta already supports setting the MAC address but this was only done
internally when some other part of U-Boot tries to actually use the
interface. This commit exposes this functionality to the ethernet core
code so that the MAC addresses of all interfaces are configured
correctly even if they are not used before loading Linux.
Signed-off-by: Matt Pelland <mpelland@starry.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Thu, 15 Feb 2018 12:19:33 +0000 (13:19 +0100)]
ARM: rmobile: Fix the memory map on Gen3
Fix up the memory map on Gen3 to match datasheet properly.
This simplifies the memory map setup as well, since we do
no longer need this massive complexity.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Tue, 10 Apr 2018 14:43:47 +0000 (16:43 +0200)]
spi: sh_qspi: Make use of the 32byte FIFO
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing
the SPI transmission 1 byte at time, if there is a 32byte chunk of
data to be transferred, fill the FIFO completely and then transfer
the data to/from the FIFO. This increases the SPI NOR access speed
significantly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Marek Vasut [Tue, 10 Apr 2018 14:58:46 +0000 (16:58 +0200)]
spi: sh_qspi: Replace ad hoc waiting with wait_for_bit
Replace the ad-hoc endless loops with wait_for_bit() with
reasonable timeout. Note that the loops had internal 10uS
delays, although there is no reason for those on this HW,
so they are dropped.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Marek Vasut [Wed, 29 Nov 2017 05:29:46 +0000 (06:29 +0100)]
mtd: spi: Add Renesas RPC SPI-flash driver
Add driver for the RPC block in SPI-flash mode. This driver allows
access to a SPI NOR flash attached to the RPC block and does not
support RPC in Hyperflash mode. Note that this block is extremely
selective when communicating with the SPI NOR.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sat, 19 Aug 2017 21:24:08 +0000 (23:24 +0200)]
mtd: rpc: Add Renesas RPC Hyperflash driver
Add driver for the RPC block in Hyperflash mode. This driver allows
access to a CFI Hyperflash attached to the RPC block and does not
support RPC in SPI mode.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Mon, 9 Apr 2018 18:47:31 +0000 (20:47 +0200)]
mmc: matsushita-common: Wait for command completion
Make sure to wait for the command to complete altogether, including
the trailing 8 clock cycles. This prevents the driver for accidentally
writing the CMD register too fast before the previous command fully
completed.
Marek Vasut [Mon, 9 Apr 2018 18:47:31 +0000 (20:47 +0200)]
mmc: matsushita-common: Special case only select registers in 16bit
There are only a few registerse used in the 16bit mode which are
32bit internally. Special-case only those in the IO accessors and
always write both halves. Any other register access is protected
from accidentally overwriting neighboring register.
Marek Vasut [Sat, 23 Sep 2017 11:01:20 +0000 (13:01 +0200)]
mmc: matsushita-common: Always check controller version
Handle the controller version even if quirks are set. The controller in
Renesas Gen3 SoCs does provide the version register, which indicates a
controller v10 and the controller does support internal DMA and /1024
divider.
Marek Vasut [Tue, 2 Jan 2018 18:40:49 +0000 (19:40 +0100)]
mmc: matsushita-common: Handle DMA completion flag differences
The DMA READ completion flag position differs on Socionext and Renesas
SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug
and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on
them.
Marek Vasut [Tue, 26 Sep 2017 18:34:35 +0000 (20:34 +0200)]
mmc: matsushita-common: Handle Renesas div-by-1
On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Marek Vasut [Sun, 8 Apr 2018 16:49:52 +0000 (18:49 +0200)]
mmc: matsushita-common: Add Renesas RCar quirks
Add a quirk to identify that the controller is Renesas RCar variant
of the Matsushita SD IP and another quirk indicating it can support
Renesas RCar HS200/HS400/SDR104 modes.
Marek Vasut [Sun, 8 Apr 2018 16:14:22 +0000 (18:14 +0200)]
mmc: renesas-sdhi: Handle 16bit IP
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants
of the IP. There is no DT property which allows discerning those,
so what Linux does is it checks the size of the register area and
if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle
the distinction the same way.
Marek Vasut [Sun, 8 Apr 2018 15:45:23 +0000 (17:45 +0200)]
mmc: uniphier: Allow passing quirks to the probe function
Certain instances of the SD IP require more elaborate digging
in the DT to figure out which variant of the SD IP is in use.
Allow explicit passing of the quirks into the probe function.
Marek Vasut [Sun, 8 Apr 2018 15:41:14 +0000 (17:41 +0200)]
mmc: uniphier: Add support for 16bit variant
Add support for 16bit mutation of the Matsushita SD IP. Since some
registers are internally 32bit, the matsu_sd_{read,write}l() has
to special-case this 16bit variant a bit.
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