]> git.sur5r.net Git - u-boot/commitdiff
ARM: rmobile: Update H2 Stout
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Thu, 12 Apr 2018 13:23:46 +0000 (15:23 +0200)
committerMarek Vasut <marex@denx.de>
Fri, 13 Apr 2018 21:41:45 +0000 (23:41 +0200)
The H2 Stout port was broken since some time. This patch updates
the H2 Stout port to use modern frameworks, DM, DT probing, SPL
and TPL for the preloading and puts it on par with the M2 Porter
board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
arch/arm/mach-rmobile/Kconfig.32
board/renesas/stout/Makefile
board/renesas/stout/cpld.c
board/renesas/stout/stout.c
board/renesas/stout/stout_spl.c [new file with mode: 0644]
configs/stout_defconfig
include/configs/stout.h

index 97260dfefb98a35c5aedb47a18a5a8591b29d64f..37e0cbab79fa6577b8dbeedeaa803198bc208dd1 100644 (file)
@@ -78,6 +78,9 @@ config TARGET_STOUT
        bool "Stout board"
        select DM
        select DM_SERIAL
+       select SUPPORT_TPL
+       select SUPPORT_SPL
+       select SPL_DM if SPL
 
 endchoice
 
index cb7c61d0203133d76934b56951c359cd3a33a6f1..b8875bb7b98a7e8afe71696e0b811b60905246ff 100644 (file)
@@ -8,4 +8,8 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y  := stout.o cpld.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y  := stout_spl.o
+else
+obj-y  := stout.o cpld.o qos.o
+endif
index 5640e1d28e487b3cfd6f888e6f5fdd3537b2372b..fc1e30ca578fb2a1ddee6d714e045f4a44d2fcc0 100644 (file)
 #include <asm/gpio.h>
 #include "cpld.h"
 
-#define SCLK                   GPIO_GP_3_24
-#define SSTBZ                  GPIO_GP_3_25
-#define MOSI                   GPIO_GP_3_26
-#define MISO                   GPIO_GP_3_27
+#define SCLK                   (92 + 24)
+#define SSTBZ                  (92 + 25)
+#define MOSI                   (92 + 26)
+#define MISO                   (92 + 27)
 
 #define CPLD_ADDR_MODE         0x00 /* RW */
 #define CPLD_ADDR_MUX          0x01 /* RW */
@@ -91,10 +91,10 @@ void cpld_init(void)
        val |= PUPR3_SD3_DAT1;
        writel(val, PUPR3);
 
-       gpio_request(SCLK, NULL);
-       gpio_request(SSTBZ, NULL);
-       gpio_request(MOSI, NULL);
-       gpio_request(MISO, NULL);
+       gpio_request(SCLK, "SCLK");
+       gpio_request(SSTBZ, "SSTBZ");
+       gpio_request(MOSI, "MOSI");
+       gpio_request(MISO, "MISO");
 
        gpio_direction_output(SCLK, 0);
        gpio_direction_output(SSTBZ, 1);
index 3cb16db10f422372e925c912a060a3520dc2c673..d7e81292a0e2aece4c41403317b6178e8d11ddbd 100644 (file)
@@ -59,14 +59,7 @@ void s_init(void)
        qos_init();
 }
 
-#define TMU0_MSTP125   (1 << 25)
-#define SCIFA0_MSTP204 (1 << 4)
-#define SDHI0_MSTP314  (1 << 14)
-#define SDHI2_MSTP312  (1 << 12)
-#define ETHER_MSTP813  (1 << 13)
-
-#define MSTPSR3                0xE6150048
-#define SMSTPCR3       0xE615013C
+#define TMU0_MSTP125   BIT(25)
 
 #define SD2CKCR                0xE6150078
 #define SD2_97500KHZ   0x7
@@ -75,12 +68,6 @@ int board_early_init_f(void)
 {
        /* TMU0 */
        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-       /* SCIFA0 */
-       mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
-       /* ETHER */
-       mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-       /* SDHI0,2 */
-       mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
 
        /*
         * SD0 clock is set to 97.5MHz by default.
@@ -91,66 +78,37 @@ int board_early_init_f(void)
        return 0;
 }
 
+#define ETHERNET_PHY_RESET     123     /* GPIO 3 31 */
+
 int board_init(void)
 {
        /* adress of boot parameters */
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-       /* Init PFC controller */
-       r8a7790_pinmux_init();
-
        cpld_init();
 
-#ifdef CONFIG_SH_ETHER
-       /* ETHER Enable */
-       gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
-       gpio_request(GPIO_FN_ETH_RX_ER, NULL);
-       gpio_request(GPIO_FN_ETH_RXD0, NULL);
-       gpio_request(GPIO_FN_ETH_RXD1, NULL);
-       gpio_request(GPIO_FN_ETH_LINK, NULL);
-       gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
-       gpio_request(GPIO_FN_ETH_MDIO, NULL);
-       gpio_request(GPIO_FN_ETH_TXD1, NULL);
-       gpio_request(GPIO_FN_ETH_TX_EN, NULL);
-       gpio_request(GPIO_FN_ETH_MAGIC, NULL);
-       gpio_request(GPIO_FN_ETH_TXD0, NULL);
-       gpio_request(GPIO_FN_ETH_MDC, NULL);
-       gpio_request(GPIO_FN_IRQ1, NULL);
-
-       gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */
-       gpio_direction_output(GPIO_GP_3_31, 0);
+       /* Force ethernet PHY out of reset */
+       gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+       gpio_direction_output(ETHERNET_PHY_RESET, 0);
        mdelay(20);
-       gpio_set_value(GPIO_GP_3_31, 1);
-       udelay(1);
-#endif
+       gpio_direction_output(ETHERNET_PHY_RESET, 1);
 
        return 0;
 }
 
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
 {
-       int ret = -ENODEV;
-
-#ifdef CONFIG_SH_ETHER
-       u32 val;
-       unsigned char enetaddr[6];
-
-       ret = sh_eth_initialize(bis);
-       if (!eth_env_get_enetaddr("ethaddr", enetaddr))
-               return ret;
+       if (fdtdec_setup_memory_size() != 0)
+               return -EINVAL;
 
-       /* Set Mac address */
-       val = enetaddr[0] << 24 | enetaddr[1] << 16 |
-             enetaddr[2] << 8 | enetaddr[3];
-       writel(val, CXR24);
+       return 0;
+}
 
-       val = enetaddr[4] << 8 | enetaddr[5];
-       writel(val, CXR25);
-#endif
+int dram_init_banksize(void)
+{
+       fdtdec_setup_memory_banksize();
 
-       return ret;
+       return 0;
 }
 
 /* Stout has KSZ8041NL/RNL */
@@ -167,67 +125,6 @@ int board_phy_config(struct phy_device *phydev)
        return 0;
 }
 
-int board_mmc_init(bd_t *bis)
-{
-       int ret = -ENODEV;
-
-#ifdef CONFIG_SH_SDHI
-       gpio_request(GPIO_FN_SD0_DAT0, NULL);
-       gpio_request(GPIO_FN_SD0_DAT1, NULL);
-       gpio_request(GPIO_FN_SD0_DAT2, NULL);
-       gpio_request(GPIO_FN_SD0_DAT3, NULL);
-       gpio_request(GPIO_FN_SD0_CLK, NULL);
-       gpio_request(GPIO_FN_SD0_CMD, NULL);
-       gpio_request(GPIO_FN_SD0_CD, NULL);
-       gpio_request(GPIO_FN_SD2_DAT0, NULL);
-       gpio_request(GPIO_FN_SD2_DAT1, NULL);
-       gpio_request(GPIO_FN_SD2_DAT2, NULL);
-       gpio_request(GPIO_FN_SD2_DAT3, NULL);
-       gpio_request(GPIO_FN_SD2_CLK, NULL);
-       gpio_request(GPIO_FN_SD2_CMD, NULL);
-       gpio_request(GPIO_FN_SD2_CD, NULL);
-
-       /* SDHI0 - needs CPLD mux setup */
-       gpio_request(GPIO_GP_3_30, NULL);
-       gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */
-       gpio_request(GPIO_GP_5_24, NULL);
-       gpio_direction_output(GPIO_GP_5_24, 1); /* power on */
-
-       ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
-                          SH_SDHI_QUIRK_16BIT_BUF);
-       if (ret)
-               return ret;
-
-       /* SDHI2 - needs CPLD mux setup */
-       gpio_request(GPIO_GP_3_29, NULL);
-       gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */
-       gpio_request(GPIO_GP_5_25, NULL);
-       gpio_direction_output(GPIO_GP_5_25, 1); /* power on */
-
-       ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
-       return ret;
-}
-
-
-int dram_init(void)
-{
-       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
-       return 0;
-}
-
 const struct rmobile_sysinfo sysinfo = {
        CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
-
-static const struct sh_serial_platdata serial_platdata = {
-       .base = SCIFA0_BASE,
-       .type = PORT_SCIFA,
-       .clk = CONFIG_MP_CLK_FREQ,
-};
-
-U_BOOT_DEVICE(stout_serials) = {
-       .name = "serial_sh",
-       .platdata = &serial_platdata,
-};
diff --git a/board/renesas/stout/stout_spl.c b/board/renesas/stout/stout_spl.c
new file mode 100644 (file)
index 0000000..1b06175
--- /dev/null
@@ -0,0 +1,481 @@
+/*
+ * board/renesas/stout/stout_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125   BIT(25)
+#define SCIFA0_MSTP204 BIT(4)
+#define QSPI_MSTP917   BIT(17)
+
+#define SD2CKCR                0xE615026C
+#define SD_97500KHZ    0x7
+
+#ifdef CONFIG_TPL_BUILD
+struct reg_config {
+       u16     off;
+       u32     val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+       static const u32 dbsc3_0_base = DBSC3_0_BASE;
+       static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+
+       while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+               ;
+
+       while (!(readl(dbsc3_1_base + reg) & BIT(0)))
+               ;
+}
+
+static void tpl_init_sys(void)
+{
+       u32 r0 = 0;
+
+       writel(0xa5a5a500, 0xe6020004);
+       writel(0xa5a5a500, 0xe6030004);
+
+       asm volatile(
+               /* ICIALLU - Invalidate I$ to PoU */
+               "mcr    15, 0, %0, cr7, cr5, 0  \n"
+               /* BPIALL - Invalidate branch predictors */
+               "mcr    15, 0, %0, cr7, cr5, 6  \n"
+               /* Set SCTLR[IZ] */
+               "mrc    15, 0, %0, cr1, cr0, 0  \n"
+               "orr    %0, #0x1800             \n"
+               "mcr    15, 0, %0, cr1, cr0, 0  \n"
+               "isb    sy                      \n"
+               :"=r"(r0));
+}
+
+static void tpl_init_pfc(void)
+{
+       static const struct reg_config pfc_with_unlock[] = {
+               { 0x0090, 0x00140300 },
+               { 0x0094, 0x09500000 },
+               { 0x0098, 0xc0000084 },
+               { 0x0020, 0x01a33492 },
+               { 0x0024, 0x10000000 },
+               { 0x0028, 0x08449252 },
+               { 0x002c, 0x2925b322 },
+               { 0x0030, 0x0c311249 },
+               { 0x0034, 0x10124000 },
+               { 0x0038, 0x00001295 },
+               { 0x003c, 0x50890000 },
+               { 0x0040, 0x0eaa56aa },
+               { 0x0044, 0x55550000 },
+               { 0x0048, 0x00000005 },
+               { 0x004c, 0x54800000 },
+               { 0x0050, 0x3736db55 },
+               { 0x0054, 0x29148da3 },
+               { 0x0058, 0x48c446e1 },
+               { 0x005c, 0x2a3a54dc },
+               { 0x0160, 0x00000023 },
+               { 0x0004, 0xfca0ffff },
+               { 0x0008, 0x3fbffbf0 },
+               { 0x000c, 0x3ffdffff },
+               { 0x0010, 0x00ffffff },
+               { 0x0014, 0xfc3ffff3 },
+               { 0x0018, 0xe4fdfff7 },
+       };
+
+       static const struct reg_config pfc_without_unlock[] = {
+               { 0x0104, 0xffffbfff },
+               { 0x0108, 0xb1ffffe1 },
+               { 0x010c, 0xffffffff },
+               { 0x0110, 0xffffffff },
+               { 0x0114, 0xe047beab },
+               { 0x0118, 0x00000203 },
+       };
+
+       static const u32 pfc_base = 0xe6060000;
+
+       unsigned int i;
+
+       for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+               writel(~pfc_with_unlock[i].val, pfc_base);
+               writel(pfc_with_unlock[i].val,
+                      pfc_base | pfc_with_unlock[i].off);
+       }
+
+       for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+               writel(pfc_without_unlock[i].val,
+                      pfc_base | pfc_without_unlock[i].off);
+}
+
+static void tpl_init_gpio(void)
+{
+       static const u16 gpio_offs[] = {
+               0x1000, 0x3000, 0x4000, 0x5000
+       };
+
+       static const struct reg_config gpio_set[] = {
+               { 0x4000, 0x00c00000 },
+               { 0x5000, 0x63020000 },
+       };
+
+       static const struct reg_config gpio_clr[] = {
+               { 0x1000, 0x00000000 },
+               { 0x3000, 0x00000000 },
+               { 0x4000, 0x00c00000 },
+               { 0x5000, 0xe3020000 },
+       };
+
+       static const u32 gpio_base = 0xe6050000;
+
+       unsigned int i;
+
+       for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+               writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+       for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+               writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+       for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+               writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+       for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+               writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void tpl_init_lbsc(void)
+{
+       static const struct reg_config lbsc_config[] = {
+               { 0x00, 0x00000020 },
+               { 0x08, 0x00002020 },
+               { 0x30, 0x02150326 },
+               { 0x38, 0x077f077f },
+       };
+
+       static const u16 lbsc_offs[] = {
+               0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+       };
+
+       static const u32 lbsc_base = 0xfec00200;
+
+       unsigned int i;
+
+       for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+               writel(lbsc_config[i].val,
+                      lbsc_base | lbsc_config[i].off);
+               writel(lbsc_config[i].val,
+                      lbsc_base | (lbsc_config[i].off + 4));
+       }
+
+       for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+               writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void tpl_init_dbsc(void)
+{
+       static const struct reg_config dbsc_config1[] = {
+               { 0x0280, 0x0000a55a },
+               { 0x0018, 0x21000000 },
+               { 0x0018, 0x11000000 },
+               { 0x0018, 0x10000000 },
+               { 0x0290, 0x00000001 },
+               { 0x02a0, 0x80000000 },
+               { 0x0290, 0x00000004 },
+       };
+
+       static const struct reg_config dbsc_config2[] = {
+               { 0x0290, 0x00000006 },
+               { 0x02a0, 0x0001c000 },
+       };
+
+       static const struct reg_config dbsc_config3r0d0[] = {
+               { 0x0290, 0x0000000f },
+               { 0x02a0, 0x00181885 },
+               { 0x0290, 0x00000070 },
+               { 0x02a0, 0x7c000887 },
+               { 0x0290, 0x00000080 },
+               { 0x02a0, 0x7c000887 },
+               { 0x0290, 0x00000090 },
+               { 0x02a0, 0x7c000887 },
+               { 0x0290, 0x000000a0 },
+               { 0x02a0, 0x7c000887 },
+               { 0x0290, 0x000000b0 },
+               { 0x02a0, 0x7c000880 },
+               { 0x0290, 0x000000c0 },
+               { 0x02a0, 0x7c000880 },
+               { 0x0290, 0x000000d0 },
+               { 0x02a0, 0x7c000880 },
+               { 0x0290, 0x000000e0 },
+               { 0x02a0, 0x7c000880 },
+       };
+
+       static const struct reg_config dbsc_config3r0d1[] = {
+               { 0x0290, 0x0000000f },
+               { 0x02a0, 0x00181885 },
+               { 0x0290, 0x00000070 },
+               { 0x02a0, 0x7c000887 },
+               { 0x0290, 0x00000080 },
+               { 0x02a0, 0x7c000887 },
+               { 0x0290, 0x00000090 },
+               { 0x02a0, 0x7c000887 },
+               { 0x0290, 0x000000a0 },
+               { 0x02a0, 0x7c000887 },
+       };
+
+       static const struct reg_config dbsc_config3r2[] = {
+               { 0x0290, 0x0000000f },
+               { 0x02a0, 0x00181224 },
+       };
+
+       static const struct reg_config dbsc_config4[] = {
+               { 0x0290, 0x00000010 },
+               { 0x02a0, 0xf004649b },
+               { 0x0290, 0x00000061 },
+               { 0x02a0, 0x0000006d },
+               { 0x0290, 0x00000001 },
+               { 0x02a0, 0x00000073 },
+               { 0x0020, 0x00000007 },
+               { 0x0024, 0x0f030a02 },
+               { 0x0030, 0x00000001 },
+               { 0x00b0, 0x00000000 },
+               { 0x0040, 0x0000000b },
+               { 0x0044, 0x00000008 },
+               { 0x0048, 0x00000000 },
+               { 0x0050, 0x0000000b },
+               { 0x0054, 0x000c000b },
+               { 0x0058, 0x00000027 },
+               { 0x005c, 0x0000001c },
+               { 0x0060, 0x00000006 },
+               { 0x0064, 0x00000020 },
+               { 0x0068, 0x00000008 },
+               { 0x006c, 0x0000000c },
+               { 0x0070, 0x00000009 },
+               { 0x0074, 0x00000012 },
+               { 0x0078, 0x000000d0 },
+               { 0x007c, 0x00140005 },
+               { 0x0080, 0x00050004 },
+               { 0x0084, 0x70233005 },
+               { 0x0088, 0x000c0000 },
+               { 0x008c, 0x00000200 },
+               { 0x0090, 0x00000040 },
+               { 0x0100, 0x00000001 },
+               { 0x00c0, 0x00020001 },
+               { 0x00c8, 0x20042004 },
+               { 0x0380, 0x00020002 },
+               { 0x0390, 0x0000001f },
+       };
+
+       static const struct reg_config dbsc_config5[] = {
+               { 0x0244, 0x00000011 },
+               { 0x0290, 0x00000003 },
+               { 0x02a0, 0x0300c4e1 },
+               { 0x0290, 0x00000023 },
+               { 0x02a0, 0x00fcdb60 },
+               { 0x0290, 0x00000011 },
+               { 0x02a0, 0x1000040b },
+               { 0x0290, 0x00000012 },
+               { 0x02a0, 0x9d9cbb66 },
+               { 0x0290, 0x00000013 },
+               { 0x02a0, 0x1a868400 },
+               { 0x0290, 0x00000014 },
+               { 0x02a0, 0x300214d8 },
+               { 0x0290, 0x00000015 },
+               { 0x02a0, 0x00000d70 },
+               { 0x0290, 0x00000016 },
+               { 0x02a0, 0x00000006 },
+               { 0x0290, 0x00000017 },
+               { 0x02a0, 0x00000018 },
+               { 0x0290, 0x0000001a },
+               { 0x02a0, 0x910035c7 },
+               { 0x0290, 0x00000004 },
+       };
+
+       static const struct reg_config dbsc_config6[] = {
+               { 0x0290, 0x00000001 },
+               { 0x02a0, 0x00000181 },
+               { 0x0018, 0x11000000 },
+               { 0x0290, 0x00000004 },
+       };
+
+       static const struct reg_config dbsc_config7[] = {
+               { 0x0290, 0x00000001 },
+               { 0x02a0, 0x0000fe01 },
+               { 0x0304, 0x00000000 },
+               { 0x00f4, 0x01004c20 },
+               { 0x00f8, 0x014000aa },
+               { 0x00e0, 0x00000140 },
+               { 0x00e4, 0x00081860 },
+               { 0x00e8, 0x00010000 },
+               { 0x0290, 0x00000004 },
+       };
+
+       static const struct reg_config dbsc_config8[] = {
+               { 0x0014, 0x00000001 },
+               { 0x0010, 0x00000001 },
+               { 0x0280, 0x00000000 },
+       };
+
+       static const u32 dbsc3_0_base = DBSC3_0_BASE;
+       static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
+       static const u32 prr_base = 0xff000044;
+       const u16 prr_rev = readl(prr_base) & 0x7fff;
+       unsigned int i;
+
+       for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
+               writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+               writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
+       }
+
+       dbsc_wait(0x2a0);
+
+       for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
+               writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+               writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
+       }
+
+       if (prr_rev == 0x4500) {
+               for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
+                       writel(dbsc_config3r0d0[i].val,
+                               dbsc3_0_base | dbsc_config3r0d0[i].off);
+               }
+               for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
+                       writel(dbsc_config3r0d1[i].val,
+                               dbsc3_1_base | dbsc_config3r0d1[i].off);
+               }
+       } else if (prr_rev != 0x4510) {
+               for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
+                       writel(dbsc_config3r2[i].val,
+                               dbsc3_0_base | dbsc_config3r2[i].off);
+                       writel(dbsc_config3r2[i].val,
+                               dbsc3_1_base | dbsc_config3r2[i].off);
+               }
+       }
+
+       for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
+               writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+               writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
+       }
+
+       dbsc_wait(0x240);
+
+       for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
+               writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+               writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
+       }
+
+       dbsc_wait(0x2a0);
+
+       for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
+               writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+               writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
+       }
+
+       dbsc_wait(0x2a0);
+
+       for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
+               writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+               writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
+       }
+
+       dbsc_wait(0x2a0);
+
+       for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
+               writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+               writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
+       }
+
+}
+
+static void tpl_init_qspi(void)
+{
+       mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+       static const u32 qspi_base = 0xe6b10000;
+
+       writeb(0x08, qspi_base + 0x00);
+       writeb(0x00, qspi_base + 0x01);
+       writeb(0x06, qspi_base + 0x02);
+       writeb(0x01, qspi_base + 0x0a);
+       writeb(0x00, qspi_base + 0x0b);
+       writeb(0x00, qspi_base + 0x0c);
+       writeb(0x00, qspi_base + 0x0d);
+       writeb(0x00, qspi_base + 0x0e);
+
+       writew(0xe080, qspi_base + 0x10);
+
+       writeb(0xc0, qspi_base + 0x18);
+       writeb(0x00, qspi_base + 0x18);
+       writeb(0x00, qspi_base + 0x08);
+       writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+       mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+       mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
+
+       /*
+        * SD0 clock is set to 97.5MHz by default.
+        * Set SD2 to the 97.5MHz as well.
+        */
+       writel(SD_97500KHZ, SD2CKCR);
+
+       tpl_init_sys();
+       tpl_init_pfc();
+       tpl_init_gpio();
+       tpl_init_lbsc();
+       tpl_init_dbsc();
+       tpl_init_qspi();
+}
+#endif
+
+void spl_board_init(void)
+{
+       /* UART clocks enabled and gd valid - init serial console */
+       preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+#ifdef CONFIG_TPL_BUILD
+       const u32 jtag_magic = 0x1337c0de;
+       const u32 load_magic = 0xb33fc0de;
+
+       /*
+        * If JTAG probe sets special word at 0xe6300020, then it must
+        * put U-Boot into RAM and TPL will start it from RAM.
+        */
+       if (readl(CONFIG_TPL_TEXT_BASE + 0x20) == jtag_magic) {
+               printf("JTAG boot detected!\n");
+
+               while (readl(CONFIG_TPL_TEXT_BASE + 0x24) != load_magic)
+                       ;
+
+               spl_boot_list[0] = BOOT_DEVICE_RAM;
+               spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+               return;
+       }
+#endif
+
+       /* Boot from SPI NOR with YMODEM UART fallback. */
+       spl_boot_list[0] = BOOT_DEVICE_SPI;
+       spl_boot_list[1] = BOOT_DEVICE_UART;
+       spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
index fd7e2dc45358fd02670267ee4f8a91953e72b4c9..bc5c561c214adcb7458b7b5ed4d03fea88f99a22 100644 (file)
@@ -1,17 +1,50 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE8080000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_R8A7790=y
 CONFIG_TARGET_STOUT=y
+CONFIG_TPL_TEXT_BASE=0xe6300000
+CONFIG_TPL_MAX_SIZE=16384
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
 CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot"
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
 CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_TPL=y
+CONFIG_TPL_BOARD_INIT=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_RAM_SUPPORT=y
+CONFIG_TPL_RAM_DEVICE=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SPI_FLASH_SUPPORT=y
+CONFIG_TPL_SPI_LOAD=y
+CONFIG_TPL_SPI_SUPPORT=y
+CONFIG_TPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SDRAM=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
@@ -19,21 +52,50 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas power-domains"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_RENESAS_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
 CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+# CONFIG_TPL_DM_SERIAL is not set
 CONFIG_SCIF_CONSOLE=y
 CONFIG_SH_QSPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_STORAGE=y
+CONFIG_TPL_TINY_MEMSET=y
index b81103e8a72dc248334f348ba8b9782bde6c9d9d..226bea814001a6f19c4c339187c0d831f8d0fbbb 100644 (file)
 
 #include "rcar-gen2-common.h"
 
-/* STACK */
-#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR                0xB003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR                0xE827FFFC
-#endif
-#define STACK_AREA_SIZE                        0xC000
-#define LOW_LEVEL_MERAM_STACK  \
+#define CONFIG_SYS_INIT_SP_ADDR                0x4f000000
+#define STACK_AREA_SIZE                        0x00100000
+#define LOW_LEVEL_MERAM_STACK \
                (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
 
 /* MEMORY */
 #define CONFIG_SH_ETHER_USE_PORT       0
 #define CONFIG_SH_ETHER_PHY_ADDR       0x1
 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SH_ETHER_ALIGNE_SIZE    64
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE    64
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
 
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_RCAR
-#define CONFIG_SYS_RCAR_I2C0_SPEED     400000
-#define CONFIG_SYS_RCAR_I2C1_SPEED     400000
-#define CONFIG_SYS_RCAR_I2C2_SPEED     400000
-#define CONFIG_SYS_RCAR_I2C3_SPEED     400000
-#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS    4
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
 /* Board Clock */
 #define RMOBILE_XTAL_CLK       20000000u
 #define CONFIG_SYS_CLK_FREQ    RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ   (CONFIG_SYS_CLK_FREQ * 156 / 2)
-#define CONFIG_PLL1_DIV2_CLK_FREQ      (CONFIG_PLL1_CLK_FREQ / 2)
-#define CONFIG_MP_CLK_FREQ     (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
-#define CONFIG_HP_CLK_FREQ     (CONFIG_PLL1_CLK_FREQ / 12)
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
 
 #define CONFIG_SYS_TMU_CLK_DIV 4
 
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        3
+#define CONFIG_EXTRA_ENV_SETTINGS      \
+       "fdt_high=0xffffffff\0"         \
+       "initrd_high=0xffffffff\0"
 
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA      0x00400000
-/* MSIF, SCIFA0 */
-#define CONFIG_SMSTP2_ENA      0x00002010
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA      0x00000180
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE           0xe6304000
+#define CONFIG_SPL_STACK               0xe6340000
+#define CONFIG_SPL_MAX_SIZE            0x40000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x140000
 
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ    97500000
+/* TPL support */
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_CONS_SCIFA0
+#define CONFIG_SH_SCIF_CLK_FREQ                52000000
+#endif
 
 #endif /* __STOUT_H */