Marek Vasut [Mon, 21 Mar 2016 12:38:11 +0000 (13:38 +0100)]
arm: socfpga: Handle phy-mode OF property for GMACs
Thus far, the socfpga init code had hard-coded the configuration
of the ethernet PHY interface to RGMII in the ethernet registers
in sysmgr space, so PHYs connected in another modes did not work.
This patch fixes support for configurations where the ethernet PHYs
are connected over MII/GMII/RMII interfaces by parsing the phy-mode
OF property of the GMACs and configuring the ethernet registers in
sysmgr space accordingly.
York Sun [Mon, 4 Apr 2016 18:41:26 +0000 (11:41 -0700)]
armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Ed Swarthout [Mon, 28 Mar 2016 21:16:01 +0000 (16:16 -0500)]
armv8: LSCH2 early and final mmu needs matching NS attribute
When switching between the early and final mmu tables, the stack will
get corrupted if the Non-Secure attribute is different. For ls1043a,
this issue is currently masked because flush_dcache_all is called
before the switch when CONFIG_SYS_DPAA_FMAN is defined.
Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
drivers: net: vsc9953: Fix bug when PVID is shown for disabled ports only
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
drivers: net: vsc9953: Do not configure disabled ports
Some SerDes protocols might not enable all l2switch ports. In this case,
these ports should not be configured to perform Rx/Tx operations.
This also fixes an issue when flooded frames were also switched to
disabled ports and frames start to accumulate, consuming memory
and eventually causing head-of-line blocking for other frames.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Fan [Tue, 15 Mar 2016 09:57:50 +0000 (17:57 +0800)]
fsl: esdhc: consolidate fsl_esdhc_cfg structure
We can use phys_addr_to for esdhc_base to discard
the #ifdef.
Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Eric Nelson <eric@nelint.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Fan [Fri, 25 Mar 2016 06:16:56 +0000 (14:16 +0800)]
fsl: esdhc: support driver model
Support Driver Model for fsl esdhc driver.
1. Introduce a new structure struct fsl_esdhc_priv
2. Refactor fsl_esdhc_initialize which is originally used by board code.
- Introduce fsl_esdhc_init to be common usage for DM and non-DM
- Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part.
- The original API for board code is still there, but we use
'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it.
3. All the functions are changed to use 'struct fsl_esdhc_priv', except
fsl_esdhc_initialize.
4. Since clk driver is not implemented, use mxc_get_clock to geth
the clk and fill 'priv->sdhc_clk'.
Has been tested on i.MX6UL 14X14 EVK board:
"
=>dm tree
....
simple_bus [ + ] | `-- aips-bus@02100000
mmc [ + ] | |-- usdhc@02190000
mmc [ + ] | |-- usdhc@02194000
....
=> mmc list
FSL_SDHC: 0 (SD)
FSL_SDHC: 1 (SD)
"
Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Hector Palacios <hector.palacios@digi.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Tested-By: Eric Nelson <eric@nelint.com> Reviewed-by: York Sun <york.sun@nxp.com>
Chris Packham [Mon, 1 Feb 2016 23:35:09 +0000 (12:35 +1300)]
kirkwood_nand: claim MPP pins on the fly
Claim the MPP pins for the NAND flash controller only when it's actually
being used. This allows the pins to be shared with the SPI interface
which already supports an equivalent on-access MPP reconfiguration.
Reviewed-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Thu, 11 Feb 2016 10:37:38 +0000 (11:37 +0100)]
spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU
Currently only chip-select 0 is supported by the kirkwood SPI driver.
The Armada XP / 38x SoCs also use this driver and support multiple chip
selects. This patch adds support for multiple CS on MVEBU.
The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jteki@openedev.com>
Michal Simek [Fri, 18 Mar 2016 22:43:39 +0000 (23:43 +0100)]
ARM: zynq: Add uEnv.txt support
preboot macro load the uEnv.txt from mmc 0 when bootmode is mmc. uenvcmd is
executed after load of uEnv.txt if it is defined in the uEnv.txt env text
file.
The default importbootenv macro reads the uEnv.txt from mmc.
Additional to this, usb_loadbootenv is added to support loading uEnv.txt
from usb dev 0.
Signed-off-by: Jason Wu <jason.wu.misc@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 8 Feb 2016 08:34:53 +0000 (09:34 +0100)]
ARM64: zynqmp: Read RAM information from DT
Read information about memory from DT. This patch simplify life with
synchronization between DT and board files.
dram_init() only needs maximum RAM size below 4GB that's why please sort
banks in memory node.
dram_init_banksize() copies memory setup to bi_dram[].
This will avoid reading information from DT twice.
Memory test start/end were changed to DDR location to let memtest still
compiled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 18 Mar 2016 17:21:36 +0000 (18:21 +0100)]
ARM64: zynqmp: Select SYS_CONFIG_NAME via Kconfig
This option enable adding new platform suport just by adding defconfig
and DTS file which will target generic configuration for SoC.
Make no sense to extend Kconfig just create a pointer between DTS and
configuration file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Joe Hershberger [Tue, 26 Jan 2016 17:57:03 +0000 (11:57 -0600)]
net: gem: Allow to set the MAC from an EEPROM
Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.
Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Patch f8bb6964 (Drop command-processing code when CONFIG_CMDLINE is
disabled) introduced a small typo. This patch fixes it and unbreaks
all boards again that don't have the Hush parser enabled.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
Stefan Roese [Fri, 29 Jan 2016 08:14:54 +0000 (09:14 +0100)]
arm: mvebu: Add basic support for Armada 375 eval board db-88f6720
This patch adds basic support for the Marvell A375 eval board. Tested
are the following interfaces:
- I2C
- SPI
- SPI NOR
- Ethernet (mvpp2), port 0 & 1
Currently the A375 SerDes and DDR3 init code is not intergrated. So
the SPL U-Boot is not fully functional.
Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:
Stefan Roese [Wed, 10 Feb 2016 06:23:00 +0000 (07:23 +0100)]
arm: mvebu: Add basic support for the Marvell Armada 375 SoC
This patch adds basic support for the Armada 375. Please note that
currently the SerDes and DDR3 init code for the A375 is not
included / enabled. This will be done in a later, follow-up patch.
Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:
Stefan Roese [Wed, 10 Feb 2016 06:22:10 +0000 (07:22 +0100)]
net: mvpp2.c: Add Marvell mvpp2 network driver for Armada 375
This patch adds support for the mvpp2 ethernet controller which is integrated
in the Marvell Armada 375 SoC. This port is based on the Linux driver (v4.4),
which has been stripped of the in U-Boot unused portions.
Tested on the Marvell Armada 375 eval board db-88f6720.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
Karsten Merker [Mon, 21 Mar 2016 19:29:07 +0000 (20:29 +0100)]
net: phy: Realtek RTL8211B/C PHY ID fix
The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a
wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.
The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F)
of the RTL8211 and the code originally applied a mask of 0xfffff0 to
the PHY ID, so that matching the PHY ID to the appropriate driver code
was only done on the chip type (RTL8211), but not on a specific
revision.
After introduction of support for the RTL8211E, which needed another
startup function than the older chip revisions, commit 42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff
to make the chip revision relevant for the match, but didn't provide
the now-relevant lower bits of the uid field for the RTL8211B/C.
Fix this by setting the full PHY ID in the RTL8211B_driver uid field.
Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected") Signed-off-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Eric Nelson [Mon, 28 Mar 2016 17:05:44 +0000 (10:05 -0700)]
drivers: block: add block device cache
Add a block device cache to speed up repeated reads of block devices by
various filesystems.
This small amount of cache can dramatically speed up filesystem
operations by skipping repeated reads of common areas of a block
device (typically directory structures).
This has shown to have some benefit on FAT filesystem operations of
loading a kernel and RAM disk, but more dramatic benefits on ext4
filesystems when the kernel and/or RAM disk are spread across
multiple extent header structures as described in commit fc0fc50.
The cache is implemented through a minimal list (block_cache) maintained
in most-recently-used order and count of the current number of entries
(cache_count). It uses a maximum block count setting to prevent copies
of large block reads and an upper bound on the number of cached areas.
The maximum number of entries in the cache defaults to 32 and the maximum
number of blocks per cache entry has a default of 2, which has shown to
produce the best results on testing of ext4 and FAT filesystems.
The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows
changing these values and can be used to tune for a particular filesystem
layout.
This commit add support for 96Boards Dragonboard410C.
It is board based on APQ8016 Qualcomm SoC, complying with
96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC
U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
First supported chip is APQ8016 (that is compatible with MSM8916).
Drivers in SoC code:
- Reset controller (PSHOLD)
- Clock controller (very simple clock configuration for MMC and UART)
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
This driver supports GPIOs present on PM8916 PMIC.
There are 2 device drivers inside:
- GPIO driver (4 "generic" GPIOs)
- Keypad driver that presents itself as GPIO with 2 inputs (power and reset)
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Qualcom processors use proprietary bus to talk with PMIC devices -
SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's
multi-master and has simple autodetection capabilities.
This commit adds simple uclass that provides bus read/write interface.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
This driver is able to reconfigure OTG controller into HOST mode.
Board can add board-specific initialization as board_prepare_usb().
It requires USB_ULPI_VIEWPORT enabled in board configuration.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
usb: ulpi: Fix compile warning in read/write on 64-bit machines.
ulpi_read and ulpi_write are used to read/write registers via ULPI bus.
Code generates compilation warnings on 64-bit machines where pointer
is cast to u32.
This patch drops all but last 8 bits of register address.
It is possible, because addresses on ULPI bus are 6- or 8-bit.
It is not possible (according to ULPI 1.1 spec) to have more
than 8-bit addressing.
This patch should not cause regressions as all calls to
ulpi_read/write use either structure pointer (@ address 0) or integer
offsets cast to pointer - addresses requested are way below 8-bit range.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it.
Also - add CONFIG_USB where necesarry - all boards use it,
but some are not defining it explicitly.
Some host controllers need addidional initialization after ehci_reset()
In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET.
This patch adds similar option to ehci drivers using dm.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Add support for SD/eMMC controller present on some Qualcomm Snapdragon
devices. This controller implements SDHCI 2.0 interface but requires
vendor-specific initialization.
Driver works in PIO mode as ADMA is not supported by U-Boot (yet).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Add support for gpio controllers on Qualcomm Snapdragon devices.
This devices are usually called Top Level Mode Multiplexing in
Qualcomm documentation.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Dan Murphy [Wed, 30 Mar 2016 17:58:37 +0000 (12:58 -0500)]
board: ti: DRA7: Add DP83867 TI phy for rev c
Enable the TI DP83867 Giga bit phy on the
dra7 rev c board. The rx and tx internal
delays are need for this board so the usage
of RGMII_ID is required.
Signed-off-by: Dan Murphy <dmurphy@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
kc1: Proper reboot mode and boot reason validation
With the previous implementation, rebooting without registering a recognized
reboot mode would end up with U-Boot checking for a valid power-on reason, which
might result in the device turning off (e.g. with no USB cable attached and no
buttons pressed).
Since this approach is not viable (breaks reboot in most cases), the validity of
the reboot reason is checked (in turn, by checking that a warm reset happened,
as there is no magic) to detect a reboot and the 'o' char is recognized to
indicate that power-off is required. Still, that might be overridden by the
detection of usual power-on reasons, on purpose.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
sniper: Proper reboot mode and boot reason validation
With the previous implementation, rebooting without registering a recognized
reboot mode (despite registering the magic) would end up with U-Boot checking
for a valid power-on reason, which might result in the device turning off (e.g.
with no USB cable attached and no buttons pressed).
This was designed to catch reboots that are actually intended to be power-off,
something that old Android kernels do, instead of properly turning the device
off using the TWL4030.
However, since this approach is not viable (breaks reboot in most cases), the
validity of the reboot mode magic is checked to detect a reboot and the 'o' char
is recognized to indicate that power-off is required. Still, that might be
overridden by the detection of usual power-on reasons, on purpose.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Masahiro Yamada [Tue, 29 Mar 2016 10:51:57 +0000 (19:51 +0900)]
arm64: booti: add missing unmap_sysmem()
Make sure to call unmap_sysmem() for address allocated by map_sysmem()
before leaving the function; however this patch gives no impact on
the behavior because map_sysmem()/unmap_sysmem() does nothing except
on Sandbox. Sandbox never runs this code because "booti" is a command
for booting ARM64 kernel image.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Vitaly Andrianov [Mon, 28 Mar 2016 19:15:59 +0000 (15:15 -0400)]
configs: ti_armv7_keystone2: make SYS_TEXT_BASE configurable at build time
U-boot for general purpose KS2 devices is loaded to the beginning of the
internal memory (0x0c000000). Secure devices uses this memory and
CONFIG_SYS_TEXT_BASE has to be different for those devices.
This commit make this configurable at build time by giving
CONFIG_SYS_TEXT_BASE as a command line definition to make command.
arm: spl: Align default board_init_f comment with code
The default board_init_f() implementation performs a call to
board_init_r() as the last step of the sequence. Fix the comment
for this function to reflect the actual execution flow.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Peng Fan [Mon, 28 Mar 2016 09:26:27 +0000 (17:26 +0800)]
common: env_sf: Add exclamation mark
Add exclamation mark to the errmsg, when error and set_default_env.
Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Mario Schuknecht <mario.schuknecht@dresearch-fe.de> Cc: Vignesh R <vigneshr@ti.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Ravi Babu <ravibabu@ti.com> Cc: York Sun <york.sun@nxp.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
In case of #define DEBUG 1 (fordebugging SPL). A bug in
spl_nand_load_image() will be triggered, because it prints
using hw ecc regardless of soft ecc configurations and
initializations.
Signed-off-by: Ahmed Samir <engkhalil86@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Fri, 25 Mar 2016 04:15:20 +0000 (22:15 -0600)]
rpi: BCM2837 and Raspberry Pi 3 32-bit support
The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with
the CPU complex swapped out for a quad-core ARMv8. This can operate in 32-
or 64-bit mode. 32-bit mode is the current default selected by the
VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of
U-Boot for the Raspberry Pi 3.
>From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a
change in usage of the SoC UARTs. On all previous Pis, the PL011 was the
only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a
UART to connect to the SoC. By default, the PL011 is used for this purpose
since it has larger FIFOs than the other "mini" UART. However, this can
be configured via the VideoCore firmware's config.txt file. This patch
hard-codes use of the mini UART in the RPi 3 port. If your system uses the
PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot
port instead. A future change might determine which UART to use at
run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed
together.
The mini UART has some limitations. One externally visible issue in the
BCM2837 integration is that the UART divides the SoC's "core clock" to
generate the baud rate. The core clock is typically variable, and under
control of the VideoCore firmware for thermal management reasons. If the
VC FW does modify the core clock rate, UART communication will be
corrupted since the baud rate will vary from the expected value. This was
not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To
work around this, the VideoCore firmware can be told not to modify the SoC
core clock. However, the only way this can happen and be thermally safe is
to limit the core clock to a low/minimum frequency. This leaves
performance on the table for use-cases that don't care about a UART
console. Consequently, use of the mini UART console must be explicitly
requested by entering the following line into config.txt:
enable_uart=1
A recent version of the VC firmware is required to ensure that the mini
UART is fully and correctly initialized by the VC FW; at least
firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on
core clock See: https://github.com/raspberrypi/firmware/issues/572".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Fri, 25 Mar 2016 04:15:18 +0000 (22:15 -0600)]
rpi: add Raspberry Pi 3 board ID
This allows U-Boot to known the name of the board.
The existing rpi_2_defconfig can operate correctly on the Raspberry Pi 3
in 32-bit mode /if/ you have configured the firmware to use the PL011 UART
as the console UART (the default is the mini UART). This requires two
things:
a) config.txt should contain dtoverlay=pi3-miniuart-bt
b) You should run the following to tell the VC FW to process DT when
booting, and copy u-boot.bin.img (rather than u-boot.bin) to the SD card
as the kernel image:
This works as of firmware.git commit 046effa13ebc "firmware: arm_loader:
emmc clock depends on core clock See:
https://github.com/raspberrypi/firmware/issues/572".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Fri, 25 Mar 2016 04:15:17 +0000 (22:15 -0600)]
rpi: use constant "unknown board" DT filename
To simplify support for new SoCs, just use a constant filename
for the unknown case. In practice this case shouldn't be hit anyway, so
the filename isn't relevant, and certainly doesn't need to differentiate
between SoCs. If a user has an as-yet-unknown board, they can override
this value in the environment anyway.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
doc: clarify openssl-based key and certificate generation process
Add some basic clarification that the dev.key file generated by OpenSSL
contains both the public and private key, and further highlight that
the certificate generated here contains the public key only.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
projects / u-boot / log