Stephen Warren [Mon, 8 Aug 2016 15:41:34 +0000 (09:41 -0600)]
misc: add Tegra BPMP driver
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core low-level communication path by
which feature-specific drivers (such as clock) can make requests to the
BPMP. This driver is similar to an MFD driver in the Linux kernel. It is
unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186
build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 8 Aug 2016 15:41:33 +0000 (09:41 -0600)]
misc: add "call" uclass op
The call op requests that the callee pass a message to the underlying HW
or device, wait for a response, and then pass back the response error code
and message to the callee. It is useful for drivers that represent some
kind of messaging or IPC channel to a remote device.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
John Keeping [Sun, 7 Aug 2016 11:55:39 +0000 (12:55 +0100)]
power: regulator: act8846: fix reading values
The voltage and control registers need to be looked up from the value in
driver_data. Adjust the get_value and get_enable functions to match the
corresponding set_* functions.
Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Fri, 5 Aug 2016 15:47:51 +0000 (09:47 -0600)]
fdt: allow fdtdec_get_addr_size_*() to translate addresses
Some code may want to read reg values from DT, but from nodes that aren't
associated with DM devices, so using dev_get_addr_index() isn't
appropriate. In this case, fdtdec_get_addr_size_*() are the functions to
use. However, "translation" (via the chain of ranges properties in parent
nodes) may still be desirable. Add a function parameter to request that,
and implement it. Update all call sites to default to the original
behaviour.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Squashed in build fix from Stephen: Signed-off-by: Simon Glass <sjg@chromium.org>
The next patch will call fdt_translate_address() from somewhere with a
"const void *blob" rather than a "void *blob", so fdt_translate_address()
must accept a const pointer too. Constify the minimum number of function
parameters to achieve this.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
Squashed in build fix from Stephen: Signed-off-by: Simon Glass <sjg@chromium.org>
Vignesh R [Wed, 10 Aug 2016 09:47:20 +0000 (15:17 +0530)]
ARM: dts: dra7xx-evm: add evm_3v3_sd regulator
Add a node for evm_3v3_sd using onboard PCF GPIO expander which feeds
on to mmc vdd.
Update mapping for vmmc-supply and vmmc_aux-supply.
evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
common: image: Add support for post-processing of images
This commit allows injecting a board/platform/device-specific post-
processing function into the FIT image data loading process, which can
include modifying the size and altering the starting source address of
an image data artifact. This might be desired to do things like strip
headers or footers attached to the images before they were packaged into
the FIT, or to perform operations such as decryption or authentication.
Introduce new configuration option CONFIG_FIT_IMAGE_POST_PROCESS to
allow controlling this feature. If enabled, a platform-specific post-
process function must be provided.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Agner [Wed, 3 Aug 2016 20:08:55 +0000 (13:08 -0700)]
ARM: non-sec: flush code cacheline aligned
Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Simon Glass [Sat, 6 Aug 2016 03:35:27 +0000 (21:35 -0600)]
i2c: Drop redundant platform data setting in drivers
The i2c uclass has a default setting for per_child_platdata_auto_alloc_size
so drivers do not need to set it. Remove this from drivers to avoid
confusion.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM. The functions for turning on/off it
is necessary whether the L2 cache is enabled or not.
As the sLD3 Boot ROM has a complex page table, it is difficult to
set up the debug UART with enabling it. It will be much easier to
initialize the UART port after switching over to the straight-mapped
page table.
Masahiro Yamada [Wed, 10 Aug 2016 07:08:40 +0000 (16:08 +0900)]
ARM: uniphier: fix ROM boot mode for PH1-sLD3
Commit 4b50369fb535 ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table creation requires the outer cache register
access but the page table in the sLD3 Boot ROM does not straight-map
virtual/physical addresses.
The idea here is to check the current page table to determine if
it is a straight map table. If not, adjust the outer cache register
base.
Masahiro Yamada [Wed, 10 Aug 2016 07:08:38 +0000 (16:08 +0900)]
ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled
If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable(). The weak
stub avoids the compile error anyway.
Dirk Eibach [Mon, 1 Aug 2016 14:34:49 +0000 (16:34 +0200)]
ppc4xx: Fix platform support
Commit "ecc3066 Fix board init code to respect the C runtime environment"
broke platform support for ppc4xx.
start.S prepares a stackframe that is later rendered unusable by appending
the reserved space for global data.
Instead the reserved space has to be put first. Then the stackframe can
be pushed.
I can only test the 405EP OCM case. At least all other ppc4xx boards still
build.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
Vignesh R [Mon, 25 Jul 2016 10:56:45 +0000 (16:26 +0530)]
i2c: i2c-uclass-compat: avoid any BSS usage
As I2C can be used before DRAM initialization for reading EEPROM,
avoid using static variables stored in BSS, since BSS is in DRAM, which
may not have been initialised yet. Explicitly mark "static global"
variables as belonging to the .data section.
Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Heiko Schocher<hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Mugunthan V N [Tue, 2 Aug 2016 06:31:12 +0000 (12:01 +0530)]
drivers: net: keystone_net: add support for multi slave ethernet
Keystone net can have multiple ethernet slaves, currently only
slave 1 is supported by the driver. Register multiple slaves as
individual ethernets to network framework.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Vignesh R [Tue, 2 Aug 2016 04:44:28 +0000 (10:14 +0530)]
ARM: dts: dra72-evm: Add mode-gpios entry for mac node
On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw
slave0 for ethernet. This is controlled by pcf gpio line. Add
appropriate mode-gpios DT entry so that driver can select the required
slave.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Tue, 2 Aug 2016 04:44:27 +0000 (10:14 +0530)]
net: cpsw: Add support to drive gpios for ethernet to be functional
On DRA72 EVM, cpsw slaves may be muxed with other modules. This
selection is controlled by a pcf gpio line. Add support for cpsw driver
to acquire mode-gpios and select the appropriate slave using gpio APIs.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Tue, 2 Aug 2016 04:44:26 +0000 (10:14 +0530)]
ARM: dts: dra7xx: Add u-boot specific property for PCF8575 nodes
PCF8575 does not have any registers hence, offset field needs to be
ignored for i2c read/write. Therefore populate u-boot,i2c-offset-len
with 0 in PCF8575 DT nodes.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Vignesh R [Tue, 2 Aug 2016 04:44:24 +0000 (10:14 +0530)]
gpio: Add driver for TI PCF8575 I2C GPIO expander
TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a
16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can
be used as an input or output without the use of a data-direction
control signal. The I/Os should be high before being used as inputs.
Read the device documentation for more details[1].
This driver is based on pcf857x driver available in Linux v4.7 kernel.
It supports basic reading and writing of gpio pins.
[1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Mike Looijmans [Tue, 26 Jul 2016 05:34:07 +0000 (07:34 +0200)]
spl_nor.c: Support devicetree sizes different from 16k
The devicetrees for various platforms already exceed 16k. Add a define
CONFIG_SYS_FDT_SIZE to specify the FDT size, and set to 16k for the
two boards that define this CONFIG_SYS_FDT_BASE parameter. This
allows platforms with larger devicetree blobs to boot from NOR.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Alban Bedel [Wed, 3 Aug 2016 06:14:41 +0000 (08:14 +0200)]
eth: asix88179: Fix receiving on big endian system
In asix_recv() the call to convert the endianess of the receive header
was applied on the wrong variable. Instead of converting rx_hdr it
converted pkt_hdr which is a pointer, and not yet initialiazed at this
point.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
The meaning of CONFIG_USB in U-Boot is different from that in Linux.
As you see in drivers/usb/Kconfig of Linux, CONFIG_USB enables the
USB host controller support, while CONFIG_USB_SUPPORT is used to
enable the whole of the USB sub-system.
When I added CONFIG_USB into Kconfig by commit 6e7e9294d321 ("usb:
add basic USB configs in Kconfig"), I planned to follow the Linux's
convention, i.e. CONFIG_USB to enable/disable the USB host support.
Then, commit 68f7c5db2d1e ("usb: Generic USB Kconfig option, that
fits both host and gadget and comments") changed the logic of the
CONFIG_USB to point to the whole of the USB sub-system. As a result,
currently we do not have an option for USB host.
This commit adds CONFIG_USB_HOST, which will be useful to compile
in the USB host support code.
CONFIG_USB_HOST is not referenced at all, but strangely some boards
define it in board headers. I removed them because USB_HOST will be
selected in Kconfig going forward.
There is no UHCI driver entry in Kconfig for now, but we have some
UHCI drivers, for example, LEON. This is a placeholder in case we
want to move them to Kconfig in the future.
Add this option as a common config for all OHCI controllers. Its
help message was copied from Linux. Also, I moved it below EHCI
to respect the order in Linux's Kconfig.
Add CONFIG_USB_OHCI_HCD=y to axs103_defconfig, which is the only
user of OHCI_GENERIC.
Stefan Roese [Wed, 29 Jun 2016 05:58:05 +0000 (07:58 +0200)]
net: usb: r8152: Add DM support
Add support for driver model, so that CONFIG_DM_ETH can be defined and
used with this driver.
This patch also adds the read_rom_hwaddr() callback so that the ROM MAC
address will be used to the DM part of this driver.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com> Cc: Ted Chen <tedchen@realtek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
Peng Fan [Fri, 17 Jun 2016 06:19:27 +0000 (14:19 +0800)]
dm: ehci-mx6: support driver model
Support driver model for ehci mx6 driver.
Consolidate code to be shared between DM and non-DM, such as
introducing ehci_mx6_common_init.
For simplicity, some old fasion code are keeped for DM usage,
such as board_ehci_power and board_usb_phy_mode. And 'dr-mode',
usbphy and vbus handling code for DM is not added now.
These will be added in future patches.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Marek Vasut <marex@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Simon Glass <sjg@chromium.org>
Chin Liang See [Sun, 7 Aug 2016 14:50:40 +0000 (22:50 +0800)]
spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value
Ensuring the baudrate divisor value doesn't exceed the max value
in the calculation.It will be capped at max value to ensure the
correct value being written into the register.
Example of the existing bug is when calculated div = 16. After and
with the mask, the value written to register is actually 0 (register
field for baudrate divisor). With this fix, the value written is now
15 which is max value for baudrate divisor.
Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jteki@openedev.com> Cc: Dinh Nguyen <dinguyen@altera.com>
This option controls how long it should be paused before entering
the auto-boot mode. The default value from Kconfig should be fine
except socfpga_vining_fpga_defconfig.
Simon Glass [Sun, 31 Jul 2016 23:35:03 +0000 (17:35 -0600)]
test: Check exit status in run_and_log_expect_exception()
This check was missed. Add it and make the message more verbose.
Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Tom Rini <trini@konsulko.com> Fixes: 9e17b034 (test/py: Provide a way to check that a command fails)
Alexander Graf [Sat, 30 Jul 2016 21:13:03 +0000 (23:13 +0200)]
armv8: mmu: Detect page table overflow in emergency pt creation
We create 2 sets of page tables: One for normal operation, one for
emergency (used while modifying the former).
Because the page tables grow dynamically, we have code that checks
for overflow. Unfortunately we didn't adjust the available space
variable while creating the emergency tables, so potentially someone
might run into an overflow there (not seen in real world yet though!).
Fix it by properly adjusting the size as well as the base offset in
emergency page table creation.
Reported-by: York Sun <york.sun@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
Kever Yang [Fri, 29 Jul 2016 03:12:18 +0000 (11:12 +0800)]
cmd: gpt: fix the wrong size parse for the last partition
The calculation of "dev_desc->lba - 34 - 1 - offset" is not correct for
size '-', because both fist_usable_lba and last_usable_lba will remain
34 sectors.
We can simply use 0 for size '-' because the part_efi module will decode
the size and auto extend the size to maximum available size.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Thu, 28 Jul 2016 02:29:42 +0000 (22:29 -0400)]
omap3: Drop omap3_evm_quick_* targets
These config targets were added well before the Kconfig migration began
as a way to demonstrate how to make these platforms work with cut down
features. At this point in time they no longer serve a good purpose so
remove them.
rockchip: remove log2 reimplementation from clock drivers
The already available ilog2 function does exactly the same in the common
case than the log2 function the current clock-driver reimplement.
So, simply move to that one.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 4 Aug 2016 03:44:58 +0000 (11:44 +0800)]
clock: rk3399: add support for dwmmc 400K
MMC core will use 400KHz for card initialize first and then switch to
higher frequency like 50MHz, we need to support both 400KHz and about
50MHz for dwmmc controller.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
move: rockchip: move clock drivers into a subdirectory
With the number of Rockchip clock drivers increasing, don't clutter up
the core drivers/clk directory with them and instead move them out of
the way into a separate subdirectory.
Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Updated for rk3399: Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 28 Jul 2016 02:29:41 +0000 (22:29 -0400)]
omap3, omap4: Enable USE_TINY_PRINTF for all
In the case of omap3 we have a number of platforms that are close to
exceeding SRAM limits, depending on compiler. Move to USE_TINY_PRINTF
to give them more room. OMAP4 will soon enough be in a similar place,
so enable that now.
Max Filippov [Thu, 28 Jul 2016 00:57:24 +0000 (03:57 +0300)]
cmd/bdinfo: extract print_std_bdinfo
print_std_bdinfo outputs typical set of board information entries:
boot params location, memory and flash addresses and sizes, network
interfaces information and configured serial baud rate.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / u-boot / log