Zied Guermazi [Sun, 2 Jun 2013 20:21:20 +0000 (22:21 +0200)]
keep gdb aware of threads if RTOS is set but no threads are created
if gdb server (openocd) answers qfThreadInfo with an empty string during boot,
gdb will not request thread info anymore. to keep thread awareness in gdb,
we have to answer with a non empty string, 'l' indicates an end of list,
and is a valid answer here.
Change-Id: I7870a5db1090c786f306db16a25871e69b8a9760 Signed-off-by: Zied Guermazi <guermazi.zied@gmail.com>
Reviewed-on: http://openocd.zylin.com/1432 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Spencer Oliver [Wed, 12 Jun 2013 16:26:13 +0000 (17:26 +0100)]
cortex_m: deprecate soft_reset_halt
soft_reset_halt was only really intended for the older arm arch, eg. armv4/5.
Newer arch such as armv7m/mips do not need this as they have better alternatives.
Change-Id: Ifb360680b7e4bfa5365f3c79d82574bded952b45 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1442 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Robert Jarzmik [Sun, 16 Jun 2013 18:22:30 +0000 (20:22 +0200)]
drivers/jtag: usb_blaster add pin controls
Add pin controls (pin6 and pin8). These pins can be
controled either :
- with a fixed value (0 or 1)
- by TRST or SRST reset signal (driven low when signal
activated).
Change-Id: Ie6a3e57fc6ba6a38fdb9a009c976e3febab8f578 Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-on: http://openocd.zylin.com/1448 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
R. Diez [Sat, 8 Jun 2013 14:07:28 +0000 (16:07 +0200)]
Bus Pirate driver: Small assorted fixes.
Fixes are:
- Discard any stale data from the previous connection.
- Disable CR/LF translation on the (virtual USB) serial port.
- Increase the average USB packet size. The 1 KiB buffer was underutilised.
- Option "buspirate_speed fast" now works out of the box.
- Some extra comments, error checking, etc.
Change-Id: I72c49d943a8ce9c5e5d1644ef90cb1482f93c618 Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/1437 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
[RFC] mips: Enable bulk write optimization for all writes
mips_m4k_bulk_write_memory was only called from target_write_buffer as an
optimization when the word count was large enough.
Remove mips_m4k_bulk_write_memory from the target type, causing the default
implementation to call the regular mips_m4k_write_memory instead.
Perform the dispatch to bulk write in mips_m4k_write_memory, enabling the
optimization for target_write_memory() writes with size 4, in addition to
target_write_buffer() writes.
It also enables making the choice of bulk write vs regular write
specifically for the architecture and not relying on the generic target
code to make a sensible decision.
Change-Id: I295f21a67ceaa195802403f2518ea2e0a025c1c7 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1215 Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Tested-by: jenkins
Spencer Oliver [Thu, 30 May 2013 09:54:54 +0000 (10:54 +0100)]
cfg: add stm32 flash driver alias
This will enable the user to use either name when calling flash driver cmds.
For example the stm32f3x family use the same flash driver as the stm32f1x, so
the user has to use 'stm32f1x mass_erase 0' which can be confusing.
Now the user can also use 'stm32f3x mass_erase 0' with the same result.
Change-Id: I14280674c8dfa2ce1c01e327af7f38e36150462c Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1428 Tested-by: jenkins
This makes libusb handling more consistent: if any driver requires
libusb, first check for libusb-1 availability, if not found and
libusb0 is ok for this case, try libusb0.
A user-visible bug fixed by this is that when a user was selecting a
driver that required libusb-1 but was lacking the necessary dev files
or libraries, configure didn't complain (but the build was failing of
course).
--enable-stlink doesn't really require libusb-1 but since it's using the
same automake symbol HLAADAPTER, ti_icdi is getting built too which needs
libusb1 unconditionally. Since using libusb-0.1 makes little sense anyway,
leave that as is.
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Change-Id: I630a4ad9e4583743d45b2233bf5d8f4e5c0aab82
Reviewed-on: http://openocd.zylin.com/1434 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Sun, 22 Jul 2012 13:28:02 +0000 (17:28 +0400)]
Add BCM2835 (as found in Raspberry Pi) interface driver
This adds support for JTAG programming by bitbanging GPIOs exposed on
the RaspberryPi's expansion header.
Tested by connecting directly to an STM32VLDiscovery board, without any
additional circuity. I observed maximum about 4MHz on the TCK pin with an
old analogue 'scope and about 100kHz when setting the speed to 100kHz.
Busyloop waiting is needed because even with a single 0ns nanosleep call
(with FIFO priority) it lowers the TCK speed to ~30kHz which is way too low
to be useful.
The speed testing with adapter_khz 2000 gave the following results:
sudo chrt -f 1 nice -n -19 ./src/openocd \
-f interface/raspberrypi-native.cfg \
-c "set WORKAREASIZE 0x2000" \
-f target/stm32f1x.cfg -c "adapter_khz 2000"
wrote 131072 bytes from file random.bin in 3.973677s (32.212 KiB/s)
dumped 131072 bytes in 1.445699s (88.538 KiB/s)
This is 3.7 times faster for writing and 14.3 times faster for reading
compared to the generic sysfsgpio driver; probably the writing speed is
limited by the target itself here and reading speed might be considerably
higher too with appropriate connection and a capable target.
BCM2835 name is choosen over BCM2708 because the published peripherals
datasheet uses the particular model name and not family name.
Change-Id: Ib78168be27f53c2a3c88c3dd8154d1190c318c78 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/758 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Hsiangkai Wang [Tue, 5 Feb 2013 01:34:18 +0000 (09:34 +0800)]
aice: add Andes AICE support
Andes AICE uses USB to transfer packets between OpenOCD and AICE.
It uses high-level USB commands to control targets instead of using
JTAG signals. I define an interface as aice_port_api_s. It contains
all basic operations needed by target-dependent code.
Change-Id: I117bc4f938fab2732e44c509ea68b30172d6fdb9 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1256 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Robert Jarzmik [Sun, 14 Apr 2013 20:23:18 +0000 (22:23 +0200)]
drivers/jtag: rewrite usb_blaster driver
Rewrite the Altera USB Blaster dongle driver :
- make extensive use of byte-shift mode, to improve JTAG
speed.
This is the main reason of the rewrite. It improves the
memory dumps with a factor 3 at least, and upload 100
times, from 1 kBytes/sec to 100 kBytes/sec with a
USB-Blaster connected to an Altera Virtual JTAG TAP +
OpenRISC CPU.
- split the low level API part (between FTDI and FTD2xx)
from core driver, so that in the future, if both libftdi
and ftd2xx can coexist, the driver will be able to switch
dynamically from one access to the other.
Change-Id: I2ee9cedf4a5eb27501f337993ee0cdee52517e7c Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Marek Czerski <ma.czerski@gmail.com> Tested-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/467 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Alexandre Becoulet <alexandre.becoulet@free.fr> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Native compilation on RaspberryPi with
gcc (Debian 4.6.3-1) 4.6.3
Target: arm-linux-gnueabi
ends with error:
cortex_a.c: In function 'cortex_a8_read_apb_ab_memory':
cortex_a.c:2063:40: error: cast increases required alignment of target type [-Werror=cast-align]
cc1: all warnings being treated as errors
Also check for malloc failure.
This patch is compile-tested only.
Change-Id: I580c505424d03ac3a565de54182db22277c52ac1 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1369 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Sun, 2 Jun 2013 09:28:37 +0000 (13:28 +0400)]
rlink: fix speed table generation
The speed table generation (by using explicit
make -f Makefile.rlink) was broken since 865efd828a267992db0f2a92a731c5ce23a34236 Dec 2 2009 which did a bunch of
renaming and included hand-editing of a generated rlink_speed_table.c file.
This patch is compile-tested, i.e. the new generated rlink_speed_table.c
links fine with the rlink driver.
Change-Id: I1789a2f2f5bf20183b772d55c55fe68a0bd05cf5 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1431 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
As per request from Peter at Ultimate Solutions, updated the
description of the ZY100 Stand-alone JTAG probe.
Signed-off-by: Bill Traynor <wmat@alphatroop.com>
Change-Id: Ia5c0b9a7261becd524a02aba1b22a98a2e09a4c9 Signed-off-by: William M.A. Traynor <wmat@alphatroop.com>
Reviewed-on: http://openocd.zylin.com/1357 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Sat, 11 May 2013 11:55:20 +0000 (15:55 +0400)]
cortex_m, hla_target: do not try asserting SRST if it's not present
This should cover all the cases when RESET_SRST_NO_GATING is set
without RESET_HAS_SRST. This might happen when RESET_SRST_NO_GATING is
automatically set by a target code (and not from tcl).
However, there're some other places (mips_m4k, arm7_9_common) where
adding RESET_SRST_PULLS_TRST would lead to trying to use SRST even if
it's not present. Currently it's impossible for the user to enable
that flag without enabling SRST.
Change-Id: Ib1c6f68feed0b8057d55afd5f260bb22ab332ced Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1405 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Paul Fertser [Thu, 23 May 2013 11:20:45 +0000 (15:20 +0400)]
targets: fix target_type name for Cortex-A targets
Commit d9ba56c295f057e716519a798bf9cdb4898c24f4 did a bunch of
renaming of cortex_a8 to cortex_a, including the names in config
files. However that introduced a regression as the name in target_type
struct remained unchanged.
This adds the last missing bit: actual renaming of the target name as
understood by OpenOCD.
Also change the (hopefully) last instance of using it in the supplied
config files, namely from imx6.cfg.
Change-Id: Ib9289fc6d946630133ec6e36c20015ccb50acf61 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1420 Tested-by: jenkins Reviewed-by: Chris Johns <chrisj@rtems.org> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Since gethostbyname() is deprecated and inconvenient, rewrite to use
getaddrinfo() using an implementation more or less copied from its man
page. This automatically enables support for IPv6.
This also fixes a FTBFS on ARM due to alignment issues.
Change-Id: I990a49506cac4b26faf77587937e506138371f7c Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/1379 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Added functionality to the SYS_SYSTEM semihosting call.
There seems to be a few missing semihosting calls. I
am not sure why this one is actually missing, since it
seems simple enough to implement. It was tested using
an HTC HD7 connected to openocd through a "home brew"
ftdi 4232H board.
Paul Fertser [Mon, 29 Apr 2013 19:31:50 +0000 (23:31 +0400)]
efm32: fix FTBFS on ARM due to alignment issues
The following warnings prevent OpenOCD from building:
efm32.c: In function 'efm32x_read_lock_data':
efm32.c:373:8: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c:386:9: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c:394:9: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c:402:9: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c: In function 'efm32x_get_page_lock':
efm32.c:430:17: error: cast increases required alignment of target type [-Werror=cast-align]
efm32.c: In function 'efm32x_set_page_lock':
efm32.c:441:19: error: cast increases required alignment of target type [-Werror=cast-align]
cc1: all warnings being treated as errors
This patch is compile-tested only.
Change-Id: Ia3a8f342e0f5e30c8ea4de9435c5c7a80bc100e3 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1370 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Hsiangkai Wang [Wed, 1 May 2013 02:23:38 +0000 (10:23 +0800)]
gdb_server: remove target_handle_event from gdb event callback
In target_call_event_callbacks(), it will execute
1. target_handle_event (use Jim_EvalObj() to evaluate event
statements in config files)
2. call user registered callbacks
Before calling user registered callbacks, target_handle_event has
been executed. So, there is no need to call target_handle_event()
in gdb event callback. It will execute event statements in config
files twice.
Change-Id: I84629e324fa3eb909907badf2319b4138ba89f07 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1372 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Spencer Oliver [Fri, 1 Feb 2013 15:43:21 +0000 (15:43 +0000)]
target: rename cortex_a8 to cortex_a
Rename cortex_a8 target to use a more correct cortex_a name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Spencer Oliver [Fri, 1 Feb 2013 15:34:51 +0000 (15:34 +0000)]
target: rename cortex_m3 to cortex_m
Rename cortex_m3 target to use a more correct cortex_m name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Ensure FlexRAM usage is limited to half the FlexRAM size when programming.
Assume the FlexNVM sector size is equal to half the FlexRAM.
Fix sector erase checking which had an error introduced when the
kinetis_ftfx_command( ) signature was changed.
Spencer Oliver [Mon, 22 Apr 2013 14:10:56 +0000 (15:10 +0100)]
build: fix libftd2xx regression
Fix build when targeting closed src ftd2xx drivers.
configure is unable to find the dynamic linking loader lib (dl) as it
is included before ftd2xx library.
Change-Id: Ibe7308b66ed846288a31f7a27ff549b6f39baeec Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1355 Tested-by: jenkins Reviewed-by: Luca Bruno <lucab@debian.org> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Spencer Oliver [Tue, 23 Apr 2013 11:15:07 +0000 (12:15 +0100)]
arm: fix arm reg regression
Seems commit fc2abe63fd3cea7497da7be2955d333bd3f800b9 caused a regression
in that the arm reg cmd no longer worked. The issue was caused because we
changed the value of ARM_MODE_THREAD which was being checked in arm_init_arch_info.
Change-Id: Id571d4ab336d1b0e2b93363147af245d24b65ca5 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1362 Tested-by: jenkins Reviewed-by: Luca Bruno <lucab@debian.org> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Hsiangkai Wang [Tue, 23 Apr 2013 10:42:07 +0000 (18:42 +0800)]
gdb server: Fix bug. Parse 'M' packet error.
The format of 'M' packet is 'M addr,length:XX...'. The data
follows ':' immediately. No need to '+2' to SEPARATOR in
unhexify(), because SEPARATOR points to data correctly.
Change-Id: I15b5758b540816cc727752e7bf68cd45e623f603 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1360 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Matt Dittrich [Tue, 5 Feb 2013 16:53:49 +0000 (10:53 -0600)]
flash/nor: add lpc4300 variant to lpc2000 driver
This patch adds flash programming support for internal flash of the
LPC43x2/3/5/7 part, tested on a LPC4337 (also tested on a LPC1768
and LPC2468). It should also work with LPC1800's with onchip flash.
The "base" parameter of the "flash bank" command is now significant
for the lpc4300 variant and required to determine the bank number
parameter needed by the IAP routines.
NOTE: I could only program flash successfully when the chip is powered
with "P2_7" pulled low to put it in ISP mode. When running from flash
(and not the ISP ROM), the target fails to halt and the sector erase
fails. This is similar to the behavior I remember when trying out the
spifi driver on a LPC4350... lots of power cycles to make progress, one
To burn, one to run. So I am not confident my config is set up correctly.
Reword info about creating SSH key - it's not required to add it to
Github account. Mention adding created SSH key to Gerrit account -
without this step it's not possible to access Gerrit in further
steps.
R. Steve McKown [Fri, 19 Apr 2013 17:29:59 +0000 (11:29 -0600)]
Support newer OSBDM firmware
OSBDM: add new VID:PID implemented in OSJTAG/OSBDM firmware somewhere
between versions 30.13 and 31.21. PFLASH programming works with this
patch, tested on a Freescale Kinetis TWR-K20D72M using its onboard OSBDM
JTAG adapter.
Note: flash program testing required hacking kinetis_write() to force
longword programming, as the FTFL program section commands formulated by
kinetis_write() currently fail on this board's PK20DX256VLL7 processor.
Change-Id: Ib7b92ff2fe9ebf6158fb1489f554a19e96cd9651 Signed-off-by: R. Steve McKown <rsmckown@gmail.com>
Reviewed-on: http://openocd.zylin.com/1348 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Salvador Arroyo [Wed, 3 Apr 2013 15:12:01 +0000 (17:12 +0200)]
mips: m4k alternate pracc code. Patch 4
Now all the functions with only fetch accesses are modified.
The same delay between scans has been added to mips32_pracc_fastdata_xfer(), it should work
at the same scan rates as the other pracc functions, but it needs higher scan_delays
to work.
Salvador Arroyo [Sun, 3 Mar 2013 19:11:38 +0000 (20:11 +0100)]
mips: m4k alternate pracc code. Patch 3
Functions mips32_pracc_read_mem(), mips32_cp0_read() and mips32_pracc_read_regs() are now modified.
mips32_cp0_read() is very similar to mips32_read_u32() with one store access.
mips32_pracc_read_regs() is the only function that can not be executed from only one queue.
Now this function is modified to use reg8, it saves all the registers but does not restore reg8.
To remedy this, mips_ejtag_config_step() is called after mips32_save_context() in
mips_m4k_debug_entry(). Function mips_ejtag_config_step() is modified to use reg8 and
restore it from ejtag info instead of using DeSave for save/restore.
Salvador Arroyo [Sun, 3 Mar 2013 12:08:42 +0000 (13:08 +0100)]
mips: m4k alternate pracc code. Patch 2
Each pracc function defines a variable ctx of type struct pracc_queue_info.
To simplify the code tree auxiliary functions are defined: pracc_queue_init(), pracc_add() and
pracc_queue_free().
The second parameter in pracc_add() is the store address if the instruction is a store at dmseg,
otherwise it should be 0.
The code is executed by mips32_pracc_queue_exec(). If ejtag_info->mode is 0 mips32_pracc_exec()
is called and it should work like with current code.
To generate the delay between scans the number of clock ticks are calculated with the help of
jtag_get_speed_khz(). Due to delays in the execution of each single ftdi instruction the number of ticks
are higher as it should be, specially at higher scan rates.
mips32_pracc_read_u32() should now work with the new code.
Salvador Arroyo [Sun, 3 Mar 2013 09:50:42 +0000 (10:50 +0100)]
mips: m4k alternate pracc code. Patch 1
This patch and the following patches define another way of doing processor access without the need to read back
the pracc address as needed in current pracc code.
Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200
and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start.
Most of the processor accesses are fetch and some are store accesses.
After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses.
The pracc address for a store depends only on the store instruction given before.
m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access
will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline.
For reference: MD00249 mips32 m4k manual.
A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the
lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by
current code or by the new one to generate the sequence of pracc accesses.
For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96().
This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution.
The pracc bit is not checked before execution, is checked after the queue has been executed.
Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx
with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay
between scans is added by calling jtag_add_cloks().
A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it.
A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set,
current code is executed, if lower, new code is executed.
Initial default values are set in function mips32_init_arch_info. A reset does not change this settings.
Ben Nahill [Fri, 19 Apr 2013 15:10:04 +0000 (11:10 -0400)]
stm32w: Added sample target configuration for STM32W108 with STLink-V2
As requested, here is the target configuration that I'm using for an
STLink-V2-attached STM32W108C8. For some reason, it only seems to work
with "reset_config trst_only".
Ben Nahill [Wed, 17 Apr 2013 20:46:07 +0000 (16:46 -0400)]
topic: STM32W support added to em357 driver
The em357 driver only supported one page configuration (192k in 96 2048k)
pages. This is fine for em357 chips since that's the size they have, but
ST's STM32W chips (pretty much the same) have different flash
configurations available (64, 128, 192, 256k). I can't find anywhere
that would indicate the size of the chip anywhere in memory so the
selection must be manual, using the 'size' parameter. For backwards
compatibility, any size not known to be in use defaults to the 192k
configuration. I don't have any em357 devices to test, but I also found
that I had to re-assert the FPEC clock enable before performing an
erase. This is a single line and shouldn't break any configurations.
My testing so far has only been with a 64k device with 8k of RAM.
Change-Id: Ic0ac400a9696efaa09d1407dd4a4d456bc2c318b Signed-off-by: Ben Nahill <bnahill@gmail.com>
Reviewed-on: http://openocd.zylin.com/1336 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se>
Spencer Oliver [Fri, 12 Apr 2013 12:10:35 +0000 (13:10 +0100)]
program: do not poll target after reset run
Disable polling the target before we issue a 'reset run'. This stops errors or
warnings if the target disables the SWD or JTAG interface as part of the
application code.
Change-Id: I5019dffdad41a8e210003ece1caf89069ee0f223 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1331 Tested-by: jenkins
Spencer Oliver [Tue, 26 Mar 2013 15:23:16 +0000 (15:23 +0000)]
parport: fix parport_toggling_time regression
If parport_toggling_time is called before the adapter speed has been
configured then the call fails. Probably not the best fix, but does at least
enable parport_toggling_time to be used again.
Michel JAOUEN [Mon, 18 Mar 2013 15:45:40 +0000 (16:45 +0100)]
arm_adi_v5: fix for csw nonsecure access.
Add command to fix CSW_SPROT in register AP_CSW.
This solves dap apmem access in non secure access.
Change-Id: I7cfcb6434d75f5cfd4a2630a059901cdeea010ce Signed-off-by: Michel JAOUEN <michel.jaouen@stericsson.com>
Reviewed-on: http://openocd.zylin.com/1276 Tested-by: jenkins Reviewed-by: mike brown Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Sun, 24 Feb 2013 16:05:28 +0000 (17:05 +0100)]
mips: change in restoring debug working register
In current devel code there are 3 functions (related to m4k code) that need to restore register 8 from pracc stack:
mips32_pracc_read_u32()
mips32_cp0_read()
mips32_pracc_write_mem_generic()
And mips32_pracc_read_mem() needs to restore regs 8 and 9 from pracc stack.
Values in this registers should be the same as read by mips32_pracc_read_regs() when entering debug
mode and can be modified by mips32_pracc_write_regs() when leaving debug mode.
There is no need to read their values from the processor registers every time.
The fields reg8 and reg9 are added to struct mips_ejtag to store these register values
and the call to mips32_save_context() is shifted in mips_m4k_debug_entry() in order
to store them before any other function needs to restore these registers.
For the same reason in function mips_m4k_step() the call to mips_m4k_set_breakpoint(), if needed,
should be made after calling mips_m4k_debug_entry().
For single word write the number of pracc accesses are now 9 or 8, from 13 or 12 in current code,
single word read takes now 10 instead of 12.
This patch is really the first in a set of patches for an alternate m4k pracc code
much faster that current code. At least for me with pic32mx works fine.
Change-Id: Ibd9df5e8b9f78ce05a180949ba6a561c761b61d6 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1146 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Sat, 23 Feb 2013 21:53:35 +0000 (22:53 +0100)]
mips: mips32_pracc_fastdata_xfer() little modification
In this function after loading the handler code and the jump code there is a call
to wait_for_pracc_rw() to verify that a pracc access is pending.
Next the address is read to verify that the handler is running, the address should be at
fastdata area.
Next, another call is made to wait_for_pracc_rw(). This call is not needed, we now already
that a pracc access is pending.
Better we call this function before loading the end address to be sure it is loaded correctly.
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Change-Id: If311450ea634786fc28cf1a8e18ed24ce5257d20
Reviewed-on: http://openocd.zylin.com/1142 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Salvador Arroyo [Sat, 23 Feb 2013 19:00:21 +0000 (20:00 +0100)]
pic32mx: 0 wait state option
By default pic32mx starts after any reset with 1 wait state for RAM access/exec.
It can be changed to 0 wait states by clearing the BMXWSDRM bit (bit 6) in BMXCON register.
With 0 wait states near doubles the execution speed. CRC check sum can be done much faster
increasing verify_image speed. Fast data transfer also works with a bit higher scan rate, up to 1500 Khz.
This option can be set at any time with
mww 0xbf882004 0x40
or cleared with
mww 0xbf882008 0x40.
Some numbers for FTDI/HS with current devel code and a elf file:
Core clock / wait states verify_image speed
------------------------------------|------------------------------
Salvador Arroyo [Sun, 17 Feb 2013 18:23:16 +0000 (19:23 +0100)]
pic32mx: false pending at low core clock
To show up the fail try to step with the core clock set to 31.25Khz
and with a ftdi/hs adapter or with a wiggler, -not with ft2232-.
The scan frequency should be set to 300Khz or higher, at lower frequency probably will not fail.
The code exits with error because the pracc address is at 0x0.
It also fails when using the "all" register, but in this case the code works without any message because the
pracc address is at 0xff202004 when it fails.
I never saw this fail with the core clock set to 500Khz or higher, but ...
The workaround simply puts a 1 ms delay after the execution of the DERET instruction.
Change-Id: I38e8c01a9c39aedd3282140543b83a0844d8ad29 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1139 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Moved JTAG code out of transport-neutral file (arm_adi_v5.c) into
transport specific file (adi_v5_jtag.c).
Added ap_block_read to dap_ops interface (arm_adi_v5.h) to support
the move.
Change-Id: I796d3984f138aad052b97c77ac9c12ffd1158f74 Signed-off-by: mike brown <mike@theshedworks.org.uk>
Reviewed-on: http://openocd.zylin.com/1277 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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