Sergei Shtylyov [Mon, 28 Jun 2010 18:44:49 +0000 (22:44 +0400)]
EHCI: zero out QH transfer overlay in ehci_submit_async()
ehci_submit_async() doesn't really zero out the QH transfer overlay (as the EHCI
specification suggests) which leads to the controller seeing the "token" field
as the previous call has left it, i.e.:
- if a timeout occured on the previous call (Active bit left as 1), controller
incorrectly tries to complete a previous transaction on a newly programmed
endpoint;
- if a halt occured on the previous call (Halted bit set to 1), controller just
ignores the newly programmed TD(s) and the function then keeps returning error
ad infinitum.
This turned out to be caused by the wrong orger of the arguments to the memset()
call in ehci_alloc(), so the allocated TDs weren't cleared either.
While at it, stop needlessly initializing the alternate next TD pointer in the
QH transfer overlay...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Acked-by: Remy Bohmer <linux@bohmer.net>
Felix Radensky [Sun, 27 Jun 2010 22:57:39 +0000 (01:57 +0300)]
tsec: Fix eTSEC2 link problem on P2020RDB
On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII.
Current TBI PHY settings for SGMII mode cause link problems on
this platform, link never comes up.
Fix this by making TBI PHY settings configurable and add a working
configuration for P2020RDB.
Signed-off-by: Felix Radensky <felix@embedded-sol.com> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Peter Tyser <ptyser@xes-inc.com>
Felix Radensky [Sun, 27 Jun 2010 22:57:39 +0000 (01:57 +0300)]
tsec: Fix eTSEC2 link problem on P2020RDB
On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII.
Current TBI PHY settings for SGMII mode cause link problems on
this platform, link never comes up.
Fix this by making TBI PHY settings configurable and add a working
configuration for P2020RDB.
Signed-off-by: Felix Radensky <felix@embedded-sol.com> Acked-by: Andy Fleming <afleming@freescale.com>
Wolfgang Denk [Mon, 28 Jun 2010 23:33:35 +0000 (01:33 +0200)]
MPC512x: workaround data corruption for unaligned local bus accesses
Commit 460c2ce3 "MPC5200: workaround data corruption for unaligned
local bus accesses" fixed the problem for MPC5200 only, but MPC512x is
affected as well, so apply the same fix here, too.
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
Wolfgang Denk [Mon, 21 Jun 2010 20:29:59 +0000 (22:29 +0200)]
MPC5200: workaround data corruption for unaligned local bus accesses
The MPC5200 has a nasty problem that will cause silent data corruption
when performing unaligned 16 or 32 byte accesses when reading from the
local bus - typically this affects reading from flash. The problem can
be easily shown:
This commit implements a workaround at least for the most blatant
problem: using memcpy() from NOR flash. We rename the assembler
routine into __memcpy() and provide a wrapper, which will use a
byte-wise copy loop for unaligned source or target addresses when
reading from NOR flash, and branch to the optimized __memcpy()
in all other cases, thus minimizing the performance impact.
Tested on lite5200b and TQM5200S.
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
Minkyu Kang [Fri, 18 Jun 2010 10:31:10 +0000 (19:31 +0900)]
ARM: remove unused VIDEOLFB ATAG
ATAG_VIDEOLFB is not used anywhere.
The belowing warning is occurred due to this ATAG.
[ 0.000000] Ignoring unrecognised tag 0x54410008
This patch fixed it.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Martin Krause <Martin.Krause@tqs.de>
Peter Horton [Sat, 12 Jun 2010 01:11:56 +0000 (10:11 +0900)]
UBI: initialise update marker
UBI: initialise update marker
The in kernel copy of a volume's update marker is not initialised from the
volume table. This means that volumes where an update was unfinnished will
not be treated as "forbidden to use". This is basically that the update
functionality was broken.
Signed-off-by: Peter Horton <zero@colonel-panic.org> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Stefan Roese <sr@denx.de>
Ilya Yanok [Mon, 21 Jun 2010 14:13:21 +0000 (18:13 +0400)]
Makefile: always call date with LC_ALL=C set
Ensure that date is called only with LC_ALL=C locale set to make dates
locale neutral thus preventing lurking of non-ASCII characters into
U-Boot binary.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Changed LANG= into LC_ALL= as suggested by Mike Frysinger <vapier@gentoo.org> Signed-off-by: Wolfgang Denk <wd@denx.de>
Vitaly Kuzmichev [Tue, 15 Jun 2010 18:18:11 +0000 (22:18 +0400)]
ARM: Align stack to 8 bytes
The ARM ABI requires that the stack be aligned to 8 bytes as it is noted
in Procedure Call Standard for the ARM Architecture:
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042d/index.html
Unaligned SP also causes the problem with variable-length arrays
allocation when VLA address becomes less than stack pointer during
aligning of this address, so the next 'push' in the stack overwrites
first 4 bytes of VLA.
Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com>
Tested on tx25(mx25), imx27lite(mx27), qong(mx31) and trab(s3c2400) Tested-by: Wolfgang Denk <wd@denx.de>
Fillod Stephane [Fri, 11 Jun 2010 17:26:43 +0000 (19:26 +0200)]
ip/defrag: fix processing of last short fragment
TFTP'ing a file of size 1747851 bytes with CONFIG_IP_DEFRAG and
CONFIG_TFTP_BLOCKSIZE set to 4096 fails with a timeout, because
the last fragment is not taken into account. This patch fixes
IP fragments having less than 8 bytes of payload.
Wolfgang Denk [Sun, 20 Jun 2010 00:16:44 +0000 (02:16 +0200)]
include/compiler.h: remove redundant declaration of errno
Commit 37566090 "compiler.h: unify system ifdef cruft here" added both
a "#include <errno.h>" and a "extern int errno;" to include/compiler.h
which is causing build warnings for some systems, for example for the
"netstar" board:
In file included from /home/wd/git/u-boot/work/lib/crc32.c:15:
include/compiler.h:28: warning: function declaration isn't a prototype
The declaration of "errno" should be redundant, as <errno.h> is
supposed to provide a correct declaration, so drop it.
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Mike Frysinger <vapier@gentoo.org>
Wolfgang Denk [Thu, 17 Jun 2010 19:59:57 +0000 (21:59 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-ti
Conflicts:
CONFLICT (rename/add): Rename
board/davinci/da830evm/Makefile->board/ti/tnetv107xevm/Makefile
in 89b765c7f6ddfde07ba673dd4adbeb5da391a81b.
board/ti/tnetv107xevm/Makefile added in HEAD
But files were identical, so no problem.
Albert Aribaud [Thu, 17 Jun 2010 14:06:07 +0000 (19:36 +0530)]
Initial support for Marvell Orion5x SoC
This patch adds support for the Marvell Orion5x SoC.
It has no use alone, and must be followed by a patch
to add Orion5x support for serial, then support for
the ED Mini V2, an Orion5x-based product from LaCie.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Marek Vasut [Sun, 11 Apr 2010 06:53:55 +0000 (08:53 +0200)]
PXA: Align stack to 8 bytes
Part of this patch is by: Mikhail Kshevetskiy.
Stack must be aligned to 8 bytes on PXA (possibly all armv5te) for LDRD/STRD
instructions. In case LDRD/STRD is issued on an unaligned address, the behaviour
is undefined.
The issue was observed when working with the NAND code, which was rendered
disfunctional. Also, the vsprintf() function had serious problems with printing
64bit wide long longs. After aligning the stack, this wrong behaviour is no
longer present.
DA850/OMAP-L138 is a new SoC from Texas Instruments
(http://focus.ti.com/docs/prod/folders/print/omap-l138.html).
This SoC is similar to DA830/OMAP-L137 in many aspects. Hence
rename the da830 specific files and folders to da8xx to
accommodate DA850/OMAP-L138.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Acked-by: Ben Gardiner <bengardiner@nanometrics.ca> Reviewed-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
TI's DA850/OMAP-L138 platform is similar to DA830/OMAP-L137
in many aspects. So instead of repeating the same code in
multiple files, move the common code to a different file
and call those functions from the respective da830/da850
files.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Acked-by: Nick Thompson <nick.thompson@ge.com> Acked-by: Ben Gardiner <bengardiner@nanometrics.ca> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Pandora has a capacitor connected as backup battery, which allows
retaining RTC for some time while main battery is removed. Enable backup
battery charge function to charge that capacitor.
Delio Brignoli [Mon, 7 Jun 2010 21:16:13 +0000 (17:16 -0400)]
DaVinci: Improve DaVinci SPI speed.
I have updated this patch based on the comments [1] by Wolfgang Denk and
removed unused variables.
[1][http://lists.denx.de/pipermail/u-boot/2010-May/071728.html]
Reduce the number of reads per byte transferred on the BUF register from 2 to 1 and
take advantage of the TX buffer in the SPI module. On LogicPD OMAP-L138 EVM,
SPI read throughput goes up from ~0.8Mbyte/s to ~1.3Mbyte/s. Tested with a 2Mbyte image file.
Remove unused variables in the spi_xfer() function.
Consolidated SDRC related functions into one file - sdrc.c
And also replaced sdrc_init with generic memory init
function (mem_init), this generalization of omap memory setup
is necessary to support the new emif4 interface introduced in AM3517.
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
bunch on on-chip integrated peripherals. This patch adds support for the
TNETV107X EVM board.
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
bunch on on-chip integrated peripherals. This is an initial commit with
basic functionality, more commits with drivers, etc. to follow.
The current ARM1176 CPU specific code is too specific to the SMDK6400
architecture. The following changes were necessary prerequisites for the
addition of other SoCs based on ARM1176.
Existing board's (SMDK6400) configuration has been modified to keep behavior
unchanged despite these changes.
1. Peripheral port remap configurability
The earlier code had hardcoded remap values specific to s3c64xx in start.S.
This change makes the peripheral port remap addresses and sizes configurable.
2. U-Boot code relocation support
Most architectures allow u-boot code to run initially at a different
address (possibly in NOR) and then get relocated to its final resting place
in RAM. Added support for this capability in ARM1176 architecture.
3. Disable TCM if necessary
If a ROM based bootloader happened to have initialized TCM, we disable it here
to keep things sane.
4. Remove unnecessary SoC specific includes
ARM1176 code does not really need this SoC specific include. The presence
of this include prevents builds on other ARM1176 archs.
5. Modified virt-to-phys conversion during MMU disable
The original MMU disable code masks out too many bits from the load address
when it tries to figure out the physical address of the jump target label.
Consequently, it ends up branching to the wrong address after disabling the
MMU.
Delio Brignoli [Mon, 7 Jun 2010 21:16:13 +0000 (17:16 -0400)]
DaVinci: Improve DaVinci SPI speed.
I have updated this patch based on the comments [1] by Wolfgang Denk and
removed unused variables.
[1][http://lists.denx.de/pipermail/u-boot/2010-May/071728.html]
Reduce the number of reads per byte transferred on the BUF register from 2 to 1 and
take advantage of the TX buffer in the SPI module. On LogicPD OMAP-L138 EVM,
SPI read throughput goes up from ~0.8Mbyte/s to ~1.3Mbyte/s. Tested with a 2Mbyte image file.
Remove unused variables in the spi_xfer() function.
Consolidated SDRC related functions into one file - sdrc.c
And also replaced sdrc_init with generic memory init
function (mem_init), this generalization of omap memory setup
is necessary to support the new emif4 interface introduced in AM3517.
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
bunch on on-chip integrated peripherals. This patch adds support for the
TNETV107X EVM board.
TNETV107X is a Texas Instruments SoC based on an ARM1176 core, and with a
bunch on on-chip integrated peripherals. This is an initial commit with
basic functionality, more commits with drivers, etc. to follow.
The current ARM1176 CPU specific code is too specific to the SMDK6400
architecture. The following changes were necessary prerequisites for the
addition of other SoCs based on ARM1176.
Existing board's (SMDK6400) configuration has been modified to keep behavior
unchanged despite these changes.
1. Peripheral port remap configurability
The earlier code had hardcoded remap values specific to s3c64xx in start.S.
This change makes the peripheral port remap addresses and sizes configurable.
2. U-Boot code relocation support
Most architectures allow u-boot code to run initially at a different
address (possibly in NOR) and then get relocated to its final resting place
in RAM. Added support for this capability in ARM1176 architecture.
3. Disable TCM if necessary
If a ROM based bootloader happened to have initialized TCM, we disable it here
to keep things sane.
4. Remove unnecessary SoC specific includes
ARM1176 code does not really need this SoC specific include. The presence
of this include prevents builds on other ARM1176 archs.
5. Modified virt-to-phys conversion during MMU disable
The original MMU disable code masks out too many bits from the load address
when it tries to figure out the physical address of the jump target label.
Consequently, it ends up branching to the wrong address after disabling the
MMU.
Add the new board PM9G45 from Ronetix GmbH.
* AT91SAM9G45 MCU at 400Mhz.
* 128MB DDR2 SDRAM
* 256MB NAND
* 10/100 MBits Ethernet DP83848
* Serial number chip DS2401
The board is made as SODIMM200 module.
For more info www.ronatix.at or info@ronetix.at.
Ron Madrid [Wed, 2 Jun 2010 00:00:49 +0000 (17:00 -0700)]
Update SICRL_USBDR to reflect 4 different settings
This patch changed the SICRL_USBDR define to reflect the 4 different bit
settings for this two-bit field. The four different options are '00', '01',
'10', and '11'. This patch also corrects the config file for SIMPC8313 and
MPC8313ERDB for the appropriate fields. This change only affects the MPC8313
cpu.
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
George G. Davis [Tue, 11 May 2010 14:15:36 +0000 (10:15 -0400)]
ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments
The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
instruction which means "Invalidate Both Caches" when in fact the intent
is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7,
c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate
Both Caches" instruction to insure that memory is consistent with any
dirty cache lines.
Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so
that they correctly describe the actual ARM1136 CP15 C7 Cache Operations
used.
Signed-off-by: George G. Davis <gdavis@mvista.com>
Kim Phillips [Fri, 23 Apr 2010 17:20:11 +0000 (12:20 -0500)]
fdt_support: add entry for sec3.1 and fix sec3.3
Add sec3.1 h/w geometry for fdt node fixups.
Also, technically, whilst SEC v3.3 h/w honours the tls_ssl_stream descriptor
type, it lacks the ARC4 algorithm execution unit required to be able
to execute anything meaningful with it. Change the node to agree with
the documentation that declares that the sec3.3 really doesn't have such
a descriptor type.
Reported-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Thu, 20 May 2010 16:16:16 +0000 (11:16 -0500)]
fsl: rename 'dma' to 'brdcfg1' in the ngPIXIS structure
The ngPIXIS is a board-specific FPGA, but the definition of the registers
is mostly consistent. On boards where it matter, register 9 is called
'brdcfg1' instead of 'dma', so rename the variable in the ngpixis_t
definition.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Thomas Chou [Fri, 14 May 2010 22:00:05 +0000 (06:00 +0800)]
nios2: fix div64 issue for gcc4
This patch fixes the run-time error on div64 when built with
gcc4, which was reported by jhwu0625 on nios forum. It merges
math support from libgcc of gcc4. This patch is copied from
nios2-linux.
It works with both gcc3 and gcc4. The old mult.c, divmod.c and
math.h are removed.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Thomas Chou [Fri, 21 May 2010 03:08:03 +0000 (11:08 +0800)]
nios2: fix r15 issue for gcc4
The "-ffixed-r15" option doesn't work well for gcc4. Since we
don't use gp for small data with option "-G0", we can use gp
as global data pointer. This allows compiler to use r15. It
is necessary for gcc4 to work properly.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Thomas Chou [Fri, 30 Apr 2010 03:34:15 +0000 (11:34 +0800)]
nios2: add gpio support to nios2-generic board
This patch adds gpio support of Altera PIO component to the
nios2-generic board. Though it drives only gpio_led at the
moment, it supports bidirectional port to control bit-banging
I2C, NAND flash busy status or button switches, etc.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Tested-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Thomas Chou [Fri, 30 Apr 2010 03:34:13 +0000 (11:34 +0800)]
nios2: add gpio support
This patch adds driver for a trivial gpio core, which is described
in http://nioswiki.com/GPIO. It is used for gpio led and nand flash
interface in u-boot.
When CONFIG_SYS_GPIO_BASE is not defined, board may provide
its own driver.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Tested-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Wolfgang Wegner [Tue, 30 Mar 2010 18:19:50 +0000 (19:19 +0100)]
add CONFIG_SYS_FEC_NO_SHARED_PHY for MCF5445x
This patch adds the possibility to handle seperate PHYs to MCF5445x.
Naming is chosen to resemble the contrary CONFIG_FEC_SHARED_PHY in the
linux kernel.
Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
Andrew Caldwell [Fri, 7 May 2010 19:10:07 +0000 (15:10 -0400)]
Blackfin: nand: drain the write buffer before returning
The current Blackfin nand write function fills up the write buffer but
returns before it has had a chance to drain. On faster systems, this
isn't a problem as the operation finishes before the ECC registers are
read, but on slower systems the ECC may be incomplete when the core tries
to read it.
So wait for the buffer to drain once we're done writing to it.
Signed-off-by: Andrew Caldwell <Andrew.Caldwell@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
config.mk: use different host compiler for OS X 10.6
Compiling tools subdirectory on Mac OS X 10.6 (Snow Leopard) complains about
wrong syntax in system includes.
In file included from /usr/include/stdio.h:444,
from ../source/u-boot/include/compiler.h:26,
from ../source/u-boot/lib/crc32.c:15:
/usr/include/secure/_stdio.h:46: error: syntax error in macro parameter list
This can be fixed by reverting the workaround for prior OS X releases in
config.mk conditionally for OS X 10.6+.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
Wolfgang Denk [Fri, 21 May 2010 21:14:53 +0000 (23:14 +0200)]
a320evb: fix udelay / __udelay confusion
Fix the following compiler problems:
arch/arm/cpu/arm920t/a320/liba320.a(timer.o): In function `udelay':
/home/wd/git/u-boot/work/arch/arm/cpu/arm920t/a320/timer.c:160: multiple definition of `udelay'
lib/libgeneric.a(time.o):/home/wd/git/u-boot/work/lib/time.c:34: first defined here
lib/libgeneric.a(time.o): In function `udelay':
time.c:(.text+0x1c): undefined reference to `__udelay'
Mahavir Jain [Fri, 21 May 2010 09:07:48 +0000 (14:37 +0530)]
bugfix: Guruplug: Use standard miiphy
call to reset PHY chip.
Current PHY Software Reset operation in guruplug does not
poll reset bit in control register to go to 0(auto clearing)
for making sure reset was successful.This patch uses standard
miiphy call miiphy_reset to make sure proper PHY reset operation.
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