Access to privlist[1] (hardcoded referece to the 2nd tsec's
priv area) is neither correct nor does it make sense in the
current context. Each tsec dev has access to its own priv
instance only, and hence to its own set of group address
registers (GADDR) to filter multicast addresses.
This fix leads to removal of the unused (faulty) privlist[]
and related global static vars. Note that mcast() can be
called only after eth_device allocation and init, and hence
after priv area allocation, so dev->priv is correctly
initialized upon mcast() call.
There are several implementation issues for tsec_mcast_addr()
addressed by this patch:
* unmanaged, not portable r/w access to registers; fixed with
setbits_be32()/ clrbits_be32()
* use of volatile pointers
* unnecessary forced cast to u8 for the ether_crc() result
* removed redundant parens
* corrected some comment slips
This fixes the following compiler warnings when activating
CONFIG_MCAST_TFTP:
tsec.c: In function 'tsec_mcast_addr':
tsec.c:130:2: warning: passing argument 2 of 'ether_crc' makes pointer
from integer without a cast [enabled by default]
In file included from /work/u-boot-net/include/common.h:874:0,
from tsec.c:15:
/work/u-boot-net/include/net.h:189:5: note: expected 'const unsigned
char *' but argument is of type 'u8'
tsec.c: In function 'tsec_initialize':
tsec.c:646:13: warning: assignment from incompatible pointer type
[enabled by default]
eth.c: In function 'eth_mcast_join':
eth.c:358:2: warning: passing argument 2 of 'eth_current->mcast' makes
integer from pointer without a cast [enabled by default]
eth.c:358:2: note: expected 'u32' but argument is of type 'u8 *'
In the eth_mcast_join() implementation, eth_current->mcast()
takes a u8 pointer to the multicast mac address and not a ip
address value as implied by its prototype.
Fix parameter type mismatch for tsec_macst_addr() (tsec.c):
ether_crc() takes a u8 pointer not a u8 value.
mcast() is given a u8 pointer to the multicats mac address.
Update parameter type for the rest of mcast() instances.
net: designware: Fix alignment of buffer descriptors
It's important that buffer descriptors are aligned in accordance to GMAC
data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes)
for every bus width type.
If buffer descriptor is improperly aligned GMAC discards lower bits of
provided address and as a result reads from improper location that
doesn't match expected fields.
Commit ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple
updates/enhancements to designware.c" introduced another structure
member "link_printed" right before buffer descriptors while "padding"
member was left untouched. This together with alignment of structure
itself to 16-byte boundary forces buffer descriptoprs always to be
4-byte aligned that causes driver complete disfunction if GMAC bus width
is 64 or 128-bit.
Proposed change makes sure all buffer descriptors are 16-byte (128-bit)
aligned.
net: designware: Respect "bus mode" register contents on SW reset
"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.
net: add support for extended registers to mdio command
Some phys (Micrel) have additional registers that can
be accessed using a special sequence. This patch allows
to use standard "mdio" command to accesss these registers.
Some phys (Micrel) has extended registers that must be
accessed in a special way. Add pointers to the phy driver
structure to allow to use these functions with mdio command.
This means that a drv->mask of 0xfffff0 will return incorrect phy driver
for the logic above, even if the drv->uid is anything other than
something ending with a 0x0.
For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff
and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then
the phy driver selected will always be RTL8211B even though the
underlying phy connected on the board is a 8211E module.
The cache API of SH was changed from dcache_wback_range to flush_dcache_range.
sh-eth uses dcache_wback_range. This patch changes to flush_dcache_range.
Shengzhou Liu [Thu, 8 Aug 2013 08:33:35 +0000 (16:33 +0800)]
phylib: update atheros ar803x phy
As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the
common driver. Currently AR8031_driver didn't work for AR8033,
hence updated it to have it work on AR8031/AR8033.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
rockly [Sat, 3 Aug 2013 10:09:05 +0000 (18:09 +0800)]
net: tftp: Make sure timeout will not effect wrap offset
When the block 0 store to the memory of client and timeout at this
moment. Because of no ACK packet, the server will send block 0 again,
if this client reconnect to the server at this time,
TftpBlockWrapOffset will become larger than it should be.
Tom Rini [Fri, 15 Nov 2013 17:20:33 +0000 (12:20 -0500)]
TI:omap: Update u-boot-spl.lds for i2c multibus/multiadapter update
In 6789e84 we update u-boot-spl.lds for OMAP to ensure we include
adapter information, as we use i2c during SPL. However, the regex used
also means we included commands that may have been built. On omap5_uevm
this leads to a failure as we include the command from the do_tca642x
command, and fail to link. The fix is to restrict our regex to only the
i2c list parts.
Gabor Juhos [Tue, 12 Nov 2013 15:47:32 +0000 (16:47 +0100)]
malta: use unmapped flash base address
The physical base address of the NOR flash is 0x1e000000
on the Malta boards. The hardware also maps the first 4MiB
of the flash into the 0x1fc00000-0x1fffffff range.
Currently, U-Boot uses the mapped address to access the
flash, which does not work in recent qemu versions.
Since commit a427338b222b43197c2776cbc996936df0302f51
(mips_malta: correct reading MIPS revision at 0x1fc00010)
writing to the mapped address space causes a CPU exception.
Due to the exception, U-Boot hangs during boot when it tries
to detect the CFI flash chip.
Use the correct physical address for the MALTA_FLASH_BASE
constant to fix the problem. In order to avoid relocation
problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE
constants.
The change makes it possible to start U-Boot on a Malta
board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also
works on older versions (tested with 1.1.1, 1.2.2, 1.4.2,
1.5.3).
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
Laurentiu TUDOR [Wed, 23 Oct 2013 12:20:45 +0000 (15:20 +0300)]
powerpc/85xx: fix broken cpu "clock-frequency" property
When indexing freqProcessor[] we use the first
value in the cpu's "reg" property, which on
new e6500 cores IDs the threads.
But freqProcessor[] should be indexed with a
core index so, when fixing "the clock-frequency"
cpu node property, access the freqProcessor[]
with the core index derived from the "reg' property.
If we don't do this, last half of the "cpu" nodes
will have broken "clock-frequency" values.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: York Sun <yorksun@freescale.com>
Laurentiu TUDOR [Wed, 23 Oct 2013 12:20:27 +0000 (15:20 +0300)]
powerpc/t4240: fix per pci endpoint liodn offsets
Update the code that builds the pci endpoint liodn
offset list so that it doesn't overlap with other
liodns and doesn't generate negative offsets like:
The update consists in adding a parameter to the
function that builds the list to specify the base
liodn.
On PCI v2.4 use the old base = 256 and, on PCI 3.0
where some of the PCIE liodns are larger than 256,
use a base = 1024. The version check is based on
the PCI controller's version register.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com>
Laurentiu TUDOR [Wed, 23 Oct 2013 12:20:16 +0000 (15:20 +0300)]
powerpc/t4240: set pcie liodn in the correct register
The liodn for the T4240's PCIE controller is no longer set
through a register in the guts register block but with one
in the PCIE register block itself.
Use the already existing SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com>
Priyanka Jain [Fri, 18 Oct 2013 11:49:23 +0000 (17:19 +0530)]
powerpc/t104xrdb: Add T1042RDB_PI board support
T1042RDB_PI is Freescale Reference Design Board supporting the T1042
QorIQ Power Architecture™ processor. T1042 is a reduced personality
of T1040 SoC without Integrated 8-port Gigabit. The board is designed
with low power features targeted for Printing Image Market.
T1042RDB_PI is similar to T1040RDB board with few differences like
it has video interface, supports T1042 personality
T1042RDB_PI board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Two on-board RGMII 10/100/1G ethernet ports.
- SERDES Connections, 8 lanes supporting:
— PCI
— SATA 2.0
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 1GB 8-bit NAND flash
- NOR: 128MB 16-bit NOR Flash
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- CPLD
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Video
- DIU supports video at up to 1280x1024x32bpp
- HDMI connector
- Power Supplies
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- SDHC/SDXC connector
- SPI
- On-board 64MB SPI flash
- I2C
- Device connected: EEPROM, thermal monitor, VID controller, RTC
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Priyanka Jain [Fri, 18 Oct 2013 07:00:21 +0000 (12:30 +0530)]
powerpc/t1040: Update defines to support T1040SoC personalities
T1040 Soc has four personalities:
-T1040 (4 cores with L2 switch)
-T1042:Reduced personality of T1040 without L2 switch
-T1020:Reduced personality of T1040 with less cores(2 cores)
-T1022:Reduced personality of T1040 with 2 cores and without L2 switch
Update defines in arch/powerpc header files, Makefiles and in
driver/net/fm/Makefile to support all T1040 personalities
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com>
Alexey Brodkin [Thu, 7 Nov 2013 13:51:43 +0000 (17:51 +0400)]
cmd_eeprom: fix i2c_{read|write} usage if env is in I2C EEPROM
Data "offset" is not used directly in case of I2C EEPROM. Istead it is
split into "block number" and "offset within mentioned block". Which are
"addr[0]" and "addr[1]" respectively.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
cc: Peter Tyser <ptyser@xes-inc.com> Cc: Heiko Schocher <hs@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com>
Marek Vasut [Mon, 4 Nov 2013 13:29:12 +0000 (14:29 +0100)]
i2c: mxs_i2c: Squash endless loop
The endless waiting for a bit to be set can cause a hang, add a timeout
so we prevent such situation. A testcase for such a hang is below. The
testcase assumes a device to be present at address 0x50 and a device to
NOT be present at address 0x42 . Also note that the "sleep 1" induced
delays are imperative for this bug to manifest .
Nikita Kiryanov [Wed, 16 Oct 2013 14:23:26 +0000 (17:23 +0300)]
spi: define SPI_XFER_ONCE
The flag combination "SPI_XFER_BEGIN | SPI_XFER_END" is a common use
case of spi_xfer, and it can easily cause an already long line (spi_xfer
takes 5 parameters) to go over the 80 character limit.
define SPI_XFER_ONCE to be a shorter version of the above flag combination.
Cc: Tom Rini <trini@ti.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Nikita Kiryanov [Wed, 16 Oct 2013 14:23:25 +0000 (17:23 +0300)]
spi: omap3: add support for more word lengths
Current implementation only supports 8 bit word lengths, even though
omap3 can handle anything between 4 and 32.
Update the spi interface to support changing the SPI word length,
and implement it in omap3_spi driver to support the full range of
possible word lengths.
This implementation is backwards compatible by defaulting to the old
behavior of 8 bit word lengths.
Also, it required a change to the omap3_spi non static I/O functions,
but since they are not used anywhere else, no collateral changes are required.
Cc: Tom Rini <trini@ti.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Andre Heider [Sat, 9 Nov 2013 10:07:53 +0000 (11:07 +0100)]
video: bcm2835: respect the pitch value
Depending on the firmware's video options [1] the active SDTV or
HDTV mode can yield a framebuffer with noncontiguous horizontal lines,
giving a messed up display, for both, u-boot and the loaded kernel.
Fix this by setting lcd_line_length to the pitch value of the configured
framebuffer.
Remove the redundant lcd_line_length initialisation which
sneaked in when an earlier version of the patch of commit 6d330719 has been rebased.
Some lcd drivers need to setup lcd_line_length not from the
panel_info parameters but by different means. Make the
lcd_get_size() weak to allow setting lcd_line_length in
a driver specific way.
Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org>
Wolfgang Denk [Mon, 11 Nov 2013 19:12:19 +0000 (20:12 +0100)]
MPC824x: remove obsolete "PN62" board
The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade. It is now
causing build issues. Instead of wasting time on things nobody is
interested in any more, we rather drop this board.
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Wolfgang Grandegger <wg@grandegger.com>
cc: Tom Rini <trini@ti.com>
time.c: In function 'tick_to_time':
time.c:59:2: warning: comparison of distinct pointer types lacks a cast [enabled by default]
time.c:59:2: warning: passing argument 1 of '__div64_32' from incompatible pointer type [enabled by default]
In file included from time.c:10:0:
./u-boot-mips/include/div64.h:22:17: note: expected 'uint64_t *' but argument is of type 'long long unsigned int *'
time.c: In function 'usec_to_tick':
time.c:76:2: warning: comparison of distinct pointer types lacks a cast [enabled by default]
time.c:76:2: warning: passing argument 1 of '__div64_32' from incompatible pointer type [enabled by default]
In file included from time.c:10:0:
./u-boot-mips/include/div64.h:22:17: note: expected 'uint64_t *' but argument is of type 'long long unsigned int *'
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Paul Burton [Mon, 11 Nov 2013 11:03:26 +0000 (11:03 +0000)]
malta: arch/mips/include/asm/malta.h SPDX license tag
This patch replaces the GPL-2.0 text with a GPL-2.0
SPDX-License-Identifier tag, and adds Imagination Technologies copyright
following my recent changes.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Makefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:
include/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.
include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.
Note: 'git show' will also list two files just because
they are new:
Gabor Juhos [Thu, 24 Oct 2013 12:32:00 +0000 (14:32 +0200)]
malta: define CONFIG_MEMSIZE_IN_BYTES
The memsize environment variable must contain the
memory size in bytes on the Malta board. Otherwise
Linux will use wrong memory size which causes a kernel
panic.
Define CONFIG_MEMSIZE_IN_BYTES in malta.h to avoid
that.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 8 Nov 2013 11:18:58 +0000 (11:18 +0000)]
malta: add script & instructions to flash U-boot
This patch adds a script which may be used with MIPS Navigator Console
and a MIPS Nagivator Probe in order to flash U-boot to a MIPS Malta
development board.
Please see the newly added doc/README.malta for usage instructions.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 8 Nov 2013 11:18:57 +0000 (11:18 +0000)]
malta: setup PIIX4 interrupt route
Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will
be left disabled. Linux does not set up this routing but relies upon it
having been set up by the bootloader, reading back the IRQ lines which
the PIRQ[A:D] signals have been routed to.
This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11.
This matches the setup used by YAMON.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 8 Nov 2013 11:18:56 +0000 (11:18 +0000)]
malta: store environment in flash
Allow the environment to be stored in the monitor flash of a Malta
board. The environment is stored in the final 128KB of the flash, which
both leaves the majority of the flash available for U-boot code and also
matches the location which YAMON uses.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 8 Nov 2013 11:18:55 +0000 (11:18 +0000)]
malta: enable RTC support
This is actually required in order for a Linux kernel to boot
successfully on a physical Malta board. Without enabling the RTC, a
Malta Linux kernel will get stuck in its estimate_frequencies function
on boot.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 8 Nov 2013 11:18:54 +0000 (11:18 +0000)]
malta: disable L2 caches
Malta boards may be used with cores which support L2 caches, however
U-boot does not yet support L2 cache for MIPS. Thus for the moment we'll
disable L2 caches by setting the L2B bit in Config2. This is specific to
MTI/Imagination MIPS cores which is why this is done for the Malta board
rather than generically.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 8 Nov 2013 11:18:53 +0000 (11:18 +0000)]
malta: remove cache size definitions
These will now be detected at runtime, allowing a single U-boot
configuration to function correctly with different bitstreams. Without
this you may need to re-configure, re-build and re-flash U-boot to your
Malta if you flash a new bitstream with a different cache configuration
to your old bitstream.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 8 Nov 2013 11:18:50 +0000 (11:18 +0000)]
malta: support for coreFPGA6 boards
This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.
Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.
Tested on:
- A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
with and without an L2 cache.
- QEMU.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 8 Nov 2013 11:18:49 +0000 (11:18 +0000)]
malta: setup super I/O UARTs
On a real Malta the Super I/O needs to be configured before we are able
to access the UARTs. This patch performs that configuration, setting up
the UARTs in the same way that YAMON would.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Sat, 9 Nov 2013 10:22:08 +0000 (10:22 +0000)]
qemu-malta: rename to just "malta"
This is in preparation for adapting this board to function correctly on
a physical MIPS Malta board. The board is moved into an "imgtec" vendor
directory at the same time in order to ready us for any other boards
supported by Imagination in the future.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
projects / u-boot / log