]> git.sur5r.net Git - u-boot/commitdiff
i2c, omap24xx: convert driver to new mutlibus/mutliadapter framework
authorHeiko Schocher <hs@denx.de>
Tue, 22 Oct 2013 09:03:18 +0000 (11:03 +0200)
committerHeiko Schocher <hs@denx.de>
Wed, 13 Nov 2013 05:18:17 +0000 (06:18 +0100)
- add omap24xx driver to new multibus/multiadpater support
- adapted all config files, which uses this driver

Tested on the am335x based siemens boards rut, dxr2 and pxm2
posted here:
http://patchwork.ozlabs.org/patch/263211/

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Tom Rini <trini@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Tom Rix <Tom.Rix@windriver.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Cc: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Nishanth Menon <nm@ti.com>
Cc: Pali Rohár <pali.rohar@gmail.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Michael Jones <michael.jones@matrix-vision.de>
Cc: Raphael Assenat <raph@8d.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Stefano Babic <sbabic@denx.de>
41 files changed:
README
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
arch/arm/cpu/armv7/omap3/board.c
arch/arm/cpu/armv7/omap3/clock.c
arch/arm/include/asm/arch-am33xx/i2c.h
board/compulab/cm_t35/cm_t35.c
board/compulab/common/Makefile
board/compulab/common/eeprom.h
board/logicpd/am3517evm/am3517evm.c
board/overo/overo.c
board/phytec/pcm051/board.c
board/siemens/common/board.c
board/ti/am335x/board.c
board/ti/am3517crane/am3517crane.c
board/ti/evm/evm.c
drivers/i2c/Makefile
drivers/i2c/omap24xx_i2c.c
include/configs/am335x_evm.h
include/configs/am3517_crane.h
include/configs/am3517_evm.h
include/configs/cm_t35.h
include/configs/devkit8000.h
include/configs/dig297.h
include/configs/mcx.h
include/configs/nokia_rx51.h
include/configs/omap3_beagle.h
include/configs/omap3_evm_common.h
include/configs/omap3_igep00x0.h
include/configs/omap3_logic.h
include/configs/omap3_mvblx.h
include/configs/omap3_overo.h
include/configs/omap3_pandora.h
include/configs/omap3_sdp3430.h
include/configs/omap3_zoom1.h
include/configs/omap3_zoom2.h
include/configs/pcm051.h
include/configs/siemens-am33x-common.h
include/configs/tam3517-common.h
include/configs/ti_armv7_common.h
include/configs/tricorder.h

diff --git a/README b/README
index 9c6d058ef0e5646c5db6cbf8a216794396afec07..53e56bb1874ac45924dd85b13fa72756964217f4 100644 (file)
--- a/README
+++ b/README
@@ -2058,6 +2058,19 @@ CBFS (Coreboot Filesystem) support
                  - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
                  - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
 
+               - drivers/i2c/omap24xx_i2c.c
+                 - activate this driver with CONFIG_SYS_I2C_OMAP24XX
+                 - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
+                 - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
+                 - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
+                 - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
+                 - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
+
                additional defines:
 
                CONFIG_SYS_NUM_I2C_BUSES
index bb77b5ca3e9af876f8e6f70e412a3b831dadc3c7..dfa3760dfc59b3da88f26868d7e81418a887e5fc 100644 (file)
@@ -779,7 +779,8 @@ void gpi2c_init(void)
        static int gpi2c = 1;
 
        if (gpi2c) {
-               i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+               i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+                        CONFIG_SYS_OMAP24_I2C_SLAVE);
                gpi2c = 0;
        }
 }
index 5e93b343e63cbf11497affbd2d0dd13c7b805f3c..989083c8084a05ba1f5091ed976ec10516cb3964 100644 (file)
@@ -32,6 +32,10 @@ SECTIONS
        . = ALIGN(4);
        .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
+       . = ALIGN(4);
+       .u_boot_list : {
+               KEEP(*(SORT(.u_boot_list*)));
+       } >.sram
        . = ALIGN(4);
        __image_copy_end = .;
        _end = .;
index 7d1f8d9d2c33758d6bdb3b9232dad562ff605248..29228160c32a6c6a79ec6b464e44e3f1424ff705 100644 (file)
@@ -98,7 +98,7 @@ void spl_board_init(void)
        gpmc_init();
 #endif
 #ifdef CONFIG_SPL_I2C_SUPPORT
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 }
 #endif /* CONFIG_SPL_BUILD */
index 9f989ff860e7f6e63acf9236fce81a7174c7bfcc..14fc7e8e810157810b37d2c65820c5cb5464ccd1 100644 (file)
@@ -708,7 +708,7 @@ void per_clocks_enable(void)
        sr32(&prcm_base->iclken_per, 17, 1, 1);
 #endif
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
        /* Turn on all 3 I2C clocks */
        sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
        sr32(&prcm_base->iclken1_core, 15, 3, 0x7);     /* I2C1,2,3 = on */
index 8bfa53f41b80ec68a3a0700fc6f585e295acf3ff..8642c8f8722acfc22eee7f6d88e2313810c404ce 100644 (file)
@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
-#ifndef _I2C_H_
-#define _I2C_H_
+#ifndef _I2C_AM33XX_H_
+#define _I2C_AM33XX_H_
 
 #define  I2C_BASE1             0x44E0B000
 #define  I2C_BASE2             0x4802A000
@@ -62,4 +62,4 @@ struct i2c {
 #define I2C_IP_CLK                     48000000
 #define I2C_INTERNAL_SAMPLING_CLK      12000000
 
-#endif /* _I2C_H_ */
+#endif /* _I2C_AM33XX_H_ */
index 9f2937a9783cea35f5e91d442de9028f573156c6..bc8e0cad9496131739f7f747ce5ec34e369ad152 100644 (file)
@@ -482,7 +482,7 @@ static void setup_net_chip_gmpc(void)
                &ctrl_base->gpmc_nadv_ale);
 }
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
 /*
  * Routine: reset_net_chip
  * Description: reset the Ethernet controller via TPS65930 GPIO
index 831be2e0e74b631cf9ce70aecb0f203eb07fcb29..6d7d06815cdb8c8b770113c0e511f2597139b636 100644 (file)
@@ -6,5 +6,5 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
+obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o
 obj-$(CONFIG_LCD) += omap3_display.o
index cf8c302b2e6563dd757f82fc2633ff4ded14eedc..e87162930d8549a20c5c35ee87396f89dbd9eae0 100644 (file)
@@ -10,7 +10,7 @@
 #ifndef _EEPROM_
 #define _EEPROM_
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
 int cl_eeprom_read_mac_addr(uchar *buf);
 u32 cl_eeprom_get_board_rev(void);
 #else
index b6c68da7a89e5d31b012a6cfc12e408ee677f978..15699054603a1d18c9bd549a350bb27cc623a66b 100644 (file)
@@ -98,8 +98,8 @@ static void am3517_evm_musb_init(void)
  */
 int misc_init_r(void)
 {
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 
        dieid_num_r();
index aace42a8be504446b5cd44d93397f5413c5231dc..9ac35d2f4e331056bff1b1359b270688444e97c2 100644 (file)
@@ -92,7 +92,7 @@ int get_board_revision(void)
 {
        int revision;
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
        unsigned char data;
 
        /* board revisions <= R2410 connect 4030 irq_1 to gpio112             */
index dafb1eb8e633fdbf3443a2038ca18160f65407a3..034886ad5d9da980ffbd6c7cfe5a0c64491b0d8d 100644 (file)
@@ -91,7 +91,7 @@ void set_mux_conf_regs(void)
 {
        /* Initalize the board header */
        enable_i2c0_pin_mux();
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 
        enable_board_pin_mux();
 }
@@ -108,7 +108,7 @@ void sdram_init(void)
  */
 int board_init(void)
 {
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
index 6279c3281ce665a13febef5023d4cf2aa955b61e..32d2ee4de9490d5b0e4ea308f87d222d33f815fd 100644 (file)
@@ -42,7 +42,7 @@ void set_mux_conf_regs(void)
 {
        /* Initalize the board header */
        enable_i2c0_pin_mux();
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_set_bus_num(0);
        if (read_eeprom() < 0)
                puts("Could not get board ID.\n");
 
@@ -67,7 +67,7 @@ int board_init(void)
 #if defined(CONFIG_HW_WATCHDOG)
        hw_watchdog_init();
 #endif /* defined(CONFIG_HW_WATCHDOG) */
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_set_bus_num(0);
        if (read_eeprom() < 0)
                puts("Could not get board ID.\n");
 
index 57fedab340af29e767245aec6768d316104867a3..8edd21b119dcb16b490b6036b430504951bc7df3 100644 (file)
@@ -397,7 +397,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
        struct am335x_baseboard_id header;
 
        enable_i2c0_pin_mux();
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
        if (read_eeprom(&header) < 0)
                puts("Could not get board ID.\n");
 
index 5eb97ff3780ccfc44c6ed4a948cda3af9c05e130..a649697257a8e6c61e479f68b8823e7e0cc104ad 100644 (file)
@@ -43,8 +43,8 @@ int board_init(void)
  */
 int misc_init_r(void)
 {
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 
        dieid_num_r();
index c71c21852998d01be335746f70b1e6ac60eeee5b..81dd081d76a98b6f864037367abf05cc12e934d4 100644 (file)
@@ -146,8 +146,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 int misc_init_r(void)
 {
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 
 #if defined(CONFIG_CMD_NET)
index 0899b6e5acd554035020d7513d29c0dd97cffee6..298b17b3650b5ceda05a896cc8b2520e44a837d1 100644 (file)
@@ -12,8 +12,6 @@ obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
 obj-$(CONFIG_I2C_MV) += mv_i2c.o
 obj-$(CONFIG_I2C_MXS) += mxs_i2c.o
 obj-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o
-obj-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
-obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
 obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
 obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
@@ -23,6 +21,8 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
 obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
+obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
 obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
index ef38d7172522e517e8ccc5c99bb642eec56160e7..3d38c035b67e5953507d509e928fc83acbe823f7 100644 (file)
@@ -35,6 +35,7 @@
  */
 
 #include <common.h>
+#include <i2c.h>
 
 #include <asm/arch/i2c.h>
 #include <asm/io.h>
@@ -48,22 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Absolutely safe for status update at 100 kHz I2C: */
 #define I2C_WAIT       200
 
-static int wait_for_bb(void);
-static u16 wait_for_event(void);
-static void flush_fifo(void);
+static int wait_for_bb(struct i2c_adapter *adap);
+static struct i2c *omap24_get_base(struct i2c_adapter *adap);
+static u16 wait_for_event(struct i2c_adapter *adap);
+static void flush_fifo(struct i2c_adapter *adap);
 
-/*
- * For SPL boot some boards need i2c before SDRAM is initialised so force
- * variables to live in SRAM
- */
-static struct i2c __attribute__((section (".data"))) *i2c_base =
-                                       (struct i2c *)I2C_DEFAULT_BASE;
-static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
-                                       { [0 ... (I2C_BUS_MAX-1)] = 0 };
-static unsigned int __attribute__((section (".data"))) current_bus = 0;
-
-void i2c_init(int speed, int slaveadd)
+static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
+       struct i2c *i2c_base = omap24_get_base(adap);
        int psc, fsscll, fssclh;
        int hsscll = 0, hssclh = 0;
        u32 scll, sclh;
@@ -163,16 +156,15 @@ void i2c_init(int speed, int slaveadd)
               I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
 #endif
        udelay(1000);
-       flush_fifo();
+       flush_fifo(adap);
        writew(0xFFFF, &i2c_base->stat);
        writew(0, &i2c_base->cnt);
-
-       if (gd->flags & GD_FLG_RELOC)
-               bus_initialized[current_bus] = 1;
 }
 
-static void flush_fifo(void)
-{      u16 stat;
+static void flush_fifo(struct i2c_adapter *adap)
+{
+       struct i2c *i2c_base = omap24_get_base(adap);
+       u16 stat;
 
        /* note: if you try and read data when its not there or ready
         * you get a bus error
@@ -192,8 +184,9 @@ static void flush_fifo(void)
  * i2c_probe: Use write access. Allows to identify addresses that are
  *            write-only (like the config register of dual-port EEPROMs)
  */
-int i2c_probe(uchar chip)
+static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
 {
+       struct i2c *i2c_base = omap24_get_base(adap);
        u16 status;
        int res = 1; /* default = fail */
 
@@ -201,7 +194,7 @@ int i2c_probe(uchar chip)
                return res;
 
        /* Wait until bus is free */
-       if (wait_for_bb())
+       if (wait_for_bb(adap))
                return res;
 
        /* No data transfer, slave addr only */
@@ -212,7 +205,7 @@ int i2c_probe(uchar chip)
        writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
               I2C_CON_STP, &i2c_base->con);
 
-       status = wait_for_event();
+       status = wait_for_event(adap);
 
        if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
                /*
@@ -223,7 +216,7 @@ int i2c_probe(uchar chip)
                 */
                if (status == I2C_STAT_XRDY)
                        printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
-                              current_bus, status);
+                              adap->hwadapnr, status);
 
                goto pr_exit;
        }
@@ -239,7 +232,7 @@ int i2c_probe(uchar chip)
                       I2C_CON_STP, &i2c_base->con);            /* STP */
        }
 pr_exit:
-       flush_fifo();
+       flush_fifo(adap);
        writew(0xFFFF, &i2c_base->stat);
        writew(0, &i2c_base->cnt);
        return res;
@@ -258,8 +251,10 @@ pr_exit:
  *           or that do not need a register address at all (such as some clock
  *           distributors).
  */
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
+                          int alen, uchar *buffer, int len)
 {
+       struct i2c *i2c_base = omap24_get_base(adap);
        int i2c_error = 0;
        u16 status;
 
@@ -287,7 +282,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
        }
 
        /* Wait until bus not busy */
-       if (wait_for_bb())
+       if (wait_for_bb(adap))
                return 1;
 
        /* Zero, one or two bytes reg address (offset) */
@@ -308,12 +303,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 #endif
                /* Send register offset */
                while (1) {
-                       status = wait_for_event();
+                       status = wait_for_event(adap);
                        /* Try to identify bus that is not padconf'd for I2C */
                        if (status == I2C_STAT_XRDY) {
                                i2c_error = 2;
                                printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
-                                      current_bus, status);
+                                      adap->hwadapnr, status);
                                goto rd_exit;
                        }
                        if (status == 0 || status & I2C_STAT_NACK) {
@@ -348,7 +343,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 
        /* Receive data */
        while (1) {
-               status = wait_for_event();
+               status = wait_for_event(adap);
                /*
                 * Try to identify bus that is not padconf'd for I2C. This
                 * state could be left over from previous transactions if
@@ -357,7 +352,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
                if (status == I2C_STAT_XRDY) {
                        i2c_error = 2;
                        printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
-                              current_bus, status);
+                              adap->hwadapnr, status);
                        goto rd_exit;
                }
                if (status == 0 || status & I2C_STAT_NACK) {
@@ -375,15 +370,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
        }
 
 rd_exit:
-       flush_fifo();
+       flush_fifo(adap);
        writew(0xFFFF, &i2c_base->stat);
        writew(0, &i2c_base->cnt);
        return i2c_error;
 }
 
 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
+                           int alen, uchar *buffer, int len)
 {
+       struct i2c *i2c_base = omap24_get_base(adap);
        int i;
        u16 status;
        int i2c_error = 0;
@@ -415,7 +412,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
        }
 
        /* Wait until bus not busy */
-       if (wait_for_bb())
+       if (wait_for_bb(adap))
                return 1;
 
        /* Start address phase - will write regoffset + len bytes data */
@@ -428,12 +425,12 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 
        while (alen) {
                /* Must write reg offset (one or two bytes) */
-               status = wait_for_event();
+               status = wait_for_event(adap);
                /* Try to identify bus that is not padconf'd for I2C */
                if (status == I2C_STAT_XRDY) {
                        i2c_error = 2;
                        printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
-                              current_bus, status);
+                              adap->hwadapnr, status);
                        goto wr_exit;
                }
                if (status == 0 || status & I2C_STAT_NACK) {
@@ -455,7 +452,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
        }
        /* Address phase is over, now write data */
        for (i = 0; i < len; i++) {
-               status = wait_for_event();
+               status = wait_for_event(adap);
                if (status == 0 || status & I2C_STAT_NACK) {
                        i2c_error = 1;
                        printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
@@ -474,7 +471,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
        }
 
 wr_exit:
-       flush_fifo();
+       flush_fifo(adap);
        writew(0xFFFF, &i2c_base->stat);
        writew(0, &i2c_base->cnt);
        return i2c_error;
@@ -484,8 +481,9 @@ wr_exit:
  * Wait for the bus to be free by checking the Bus Busy (BB)
  * bit to become clear
  */
-static int wait_for_bb(void)
+static int wait_for_bb(struct i2c_adapter *adap)
 {
+       struct i2c *i2c_base = omap24_get_base(adap);
        int timeout = I2C_TIMEOUT;
        u16 stat;
 
@@ -514,8 +512,9 @@ static int wait_for_bb(void)
  * Wait for the I2C controller to complete current action
  * and update status
  */
-static u16 wait_for_event(void)
+static u16 wait_for_event(struct i2c_adapter *adap)
 {
+       struct i2c *i2c_base = omap24_get_base(adap);
        u16 status;
        int timeout = I2C_TIMEOUT;
 
@@ -540,7 +539,7 @@ static u16 wait_for_event(void)
                 * not been configured for I2C, and/or pull-ups are missing.
                 */
                printf("Check if pads/pull-ups of bus %d are properly configured\n",
-                      current_bus);
+                      adap->hwadapnr);
                writew(0xFFFF, &i2c_base->stat);
                status = 0;
        }
@@ -548,48 +547,93 @@ static u16 wait_for_event(void)
        return status;
 }
 
-int i2c_set_bus_num(unsigned int bus)
+static struct i2c *omap24_get_base(struct i2c_adapter *adap)
 {
-       if (bus >= I2C_BUS_MAX) {
-               printf("Bad bus: %x\n", bus);
-               return -1;
-       }
-
-       switch (bus) {
-       default:
-               bus = 0;        /* Fall through */
+       switch (adap->hwadapnr) {
        case 0:
-               i2c_base = (struct i2c *)I2C_BASE1;
+               return (struct i2c *)I2C_BASE1;
                break;
        case 1:
-               i2c_base = (struct i2c *)I2C_BASE2;
+               return (struct i2c *)I2C_BASE2;
                break;
 #if (I2C_BUS_MAX > 2)
        case 2:
-               i2c_base = (struct i2c *)I2C_BASE3;
+               return (struct i2c *)I2C_BASE3;
                break;
 #if (I2C_BUS_MAX > 3)
        case 3:
-               i2c_base = (struct i2c *)I2C_BASE4;
+               return (struct i2c *)I2C_BASE4;
                break;
 #if (I2C_BUS_MAX > 4)
        case 4:
-               i2c_base = (struct i2c *)I2C_BASE5;
+               return (struct i2c *)I2C_BASE5;
                break;
 #endif
 #endif
 #endif
+       default:
+               printf("wrong hwadapnr: %d\n", adap->hwadapnr);
+               break;
        }
+       return NULL;
+}
 
-       current_bus = bus;
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
+#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
 
-       if (!bus_initialized[current_bus])
-               i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
+                        omap24_i2c_read, omap24_i2c_write, NULL,
+                        CONFIG_SYS_OMAP24_I2C_SPEED,
+                        CONFIG_SYS_OMAP24_I2C_SLAVE,
+                        0)
+U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
+                        omap24_i2c_read, omap24_i2c_write, NULL,
+                        CONFIG_SYS_OMAP24_I2C_SPEED1,
+                        CONFIG_SYS_OMAP24_I2C_SLAVE1,
+                        1)
+#if (I2C_BUS_MAX > 2)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
+#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
 
-       return 0;
-}
+U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
+                        omap24_i2c_read, omap24_i2c_write, NULL,
+                        CONFIG_SYS_OMAP24_I2C_SPEED2,
+                        CONFIG_SYS_OMAP24_I2C_SLAVE2,
+                        2)
+#if (I2C_BUS_MAX > 3)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
+#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
 
-int i2c_get_bus_num(void)
-{
-       return (int) current_bus;
-}
+U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
+                        omap24_i2c_read, omap24_i2c_write, NULL,
+                        CONFIG_SYS_OMAP24_I2C_SPEED3,
+                        CONFIG_SYS_OMAP24_I2C_SLAVE3,
+                        3)
+#if (I2C_BUS_MAX > 4)
+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
+#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
+#endif
+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
+#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
+#endif
+
+U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
+                        omap24_i2c_read, omap24_i2c_write, NULL,
+                        CONFIG_SYS_OMAP24_I2C_SPEED4,
+                        CONFIG_SYS_OMAP24_I2C_SLAVE4,
+                        4)
+#endif
+#endif
+#endif
index c2ba7e35d891bcf145885c9f278ba10e45d73c11..f35ed6fba0c102bafeb2d7b2937dd8cfeb7f4bc4 100644 (file)
 #define CONFIG_SYS_NS16550_COM6                0x481aa000      /* UART5 */
 #define CONFIG_BAUDRATE                        115200
 
-/* I2C Configuration */
 #define CONFIG_CMD_EEPROM
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* Main EEPROM */
index c5e67bf87d43688dac719a7918ec112162dccd16..6fd3fb9045cc3d0c0b985ebcf2c9d60c8b023679 100644 (file)
 #undef CONFIG_CMD_IMLS         /* List all found images        */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
index 5ff65c6d58c1519d52d83eaf19bd2037b1e459e5..7e9c55edf1d4a655ea05c91edc19e60714583c6b 100644 (file)
 #undef CONFIG_CMD_IMLS         /* List all found images        */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
index a6c63cb4933cb3fa9320947ad9e19568fa7418c4..f4ecd0ddbe61aa766de1aceadf2d65f39a6601d2 100644 (file)
 #undef CONFIG_CMD_IMLS         /* List all found images        */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_I2C_MULTI_BUS
index 8343891cb8d8d47d31fb1579a3e1b37b8233bc38..474a5687a95df1b8b3b5c73dc1d6177fda0913d4 100644 (file)
 #define CONFIG_DOS_PARTITION           1
 
 /* I2C */
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /* TWL4030 */
 #define CONFIG_TWL4030_POWER           1
index c19c4c7549d52062aca68c4746b5b679c6f8420c..5049afca7a7025a00939217285c165424ecaa7a4 100644 (file)
 #undef CONFIG_CMD_NFS          /* NFS support                  */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
index 4619dfb3e4759f613b48b06ef67a8e25717e74b3..a2f7cf711d0b223b7d4eeee6d62734216e3e11c4 100644 (file)
 #undef CONFIG_CMD_IMLS         /* List all found images        */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /* RTC */
 #define CONFIG_RTC_DS1337
index 4332779d255109c213f32d967e88312e48e6cd40..e0c0fac8e1935926158e5019a6500d0f57975c81 100644 (file)
 #undef CONFIG_CMD_SETGETDCR            /* DCR support on 4xx */
 
 #define CONFIG_OMAP3_SPI
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
index 47d99020887b975c3a6f797d923bf347212356fa..bba39d428654fc94d71d7f6bb7559b742792f77a 100644 (file)
 #undef CONFIG_CMD_IMLS         /* List all found images        */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_I2C_MULTI_BUS           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_VIDEO_OMAP3     /* DSS Support                  */
 
 /*
index 3eae28884c228a851f4b27309673db08ecc23d40..43616e2b029b791e809063e21bc5b203dc2b7254 100644 (file)
 /*
  * I2C
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_OMAP34XX_I2C
-
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * PISMO support
index ac36ac69504b27fa5cedf04c96b2a84ebf4b88b2..75d7d70d291981f66edd60bb87bf504826e680e5 100644 (file)
 #undef CONFIG_CMD_IMLS         /* List all found images        */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
 
 /*
  * TWL4030
index 0c096f429f1a16d6703386069107900860195018..bedd6f9cb39b61794fefd71c270879f6ae3c8117 100644 (file)
 /*
  * I2C
  */
-#define CONFIG_HARD_I2C
-#define CONFIG_DRIVER_OMAP34XX_I2C
-
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
index 45da2e00b29279e5a9b63a7e687ccf4aa8e90eb8..8d11010f84596e66e05e4b36ee29442747b7ac37 100644 (file)
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_FPGA
 
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           0
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
-#define CONFIG_I2C_MULTI_BUS           1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
index 46416946c7965a418283bee7a71cf52cf2f6206b..84b4aeee2abb32e6eaa301eec1f4e63d8780df58 100644 (file)
 #define CONFIG_CMD_NET         /* bootp, tftpboot, rarpboot    */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
index 3cce0de48d5b1756dc48ee70ce2e974c00ed97b0..eacdfaaa53b04a8df199ed973690cafd44bafa3e 100644 (file)
 #undef CONFIG_CMD_NFS          /* NFS support                  */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
index 697a3f386c059f653b47330d8c8561cfe682aa37..6f1304dc9432e374b9f8203d3e3f77d72fb79d64 100644 (file)
 /*
  * I2C for power management setup
  */
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /* OMITTED:  single 1 Gbit MT29F1G NAND flash */
 
index 8591f98a8a7d79d9e83fa144a0477868b818094f..1dd53fa13308a8ca244c3d83d1c050dc9a909239 100644 (file)
 #undef CONFIG_CMD_NFS          /* NFS support                  */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
index cb8c7ec6f0667a3e7e307901826199538fa4d314..f7497408158f74ba5f187c249f13ac93f43978ec 100644 (file)
 #undef CONFIG_CMD_NFS                  /* NFS support                  */
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C                        1
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /*
  * TWL4030
index 4970b13e9679f6a18948e6ae79b3af89d1680c46..6f41ee771832de055a034028e4c0f8897ac6e943 100644 (file)
 /* I2C Configuration */
 #define CONFIG_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP24XX_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP24XX
 #define CONFIG_CMD_EEPROM
 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* Main EEPROM */
index 9eb0a04da6622dccafeb0211f64b4d3d69097cd0..745e3bea58e403c52add644506d75c61f57f5948 100644 (file)
 /* I2C Configuration */
 #define CONFIG_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP24XX_I2C
-
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    OMAP_I2C_STANDARD
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP24XX
 
 /* Defines for SPL */
 #define CONFIG_SPL
index 683bc54a2c1c2eb929ea623a8739e2a922b390cb..6112c1b7a698bdf25d8649919e9aa81c2ec130a1 100644 (file)
 #undef CONFIG_CMD_IMLS
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED           400000
-#define CONFIG_SYS_I2C_SLAVE           1
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    400000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x50            /* base address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1               /* bytes of address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW    0x07
-#define CONFIG_DRIVER_OMAP34XX_I2C
-
 
 /*
  * Board NAND Info.
@@ -369,7 +368,7 @@ struct tam3517_module_info {
 
 #define TAM3517_READ_EEPROM(info, ret) \
 do {                                                           \
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);   \
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
        if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,          \
                (void *)info, sizeof(*info)))                   \
                ret = 1;                                        \
index 84269ad262c09d32bbc6e8f7e8a5a7017d8628d7..99b60fcf6155c5ee5b335ab3090780d100ec1d8d 100644 (file)
 
 /* I2C IP block */
 #define CONFIG_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_DRIVER_OMAP24XX_I2C
 #define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP24XX
 
 /* MMC/SD IP block */
 #define CONFIG_MMC
index d57394e55016e7b5f3ec80628e049dc73bc0b49c..afd870762b713db75f89bb8849b6f73c7a89598d 100644 (file)
 #define CONFIG_DOS_PARTITION
 
 /* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED           100000
-#define CONFIG_SYS_I2C_SLAVE           1
-#define CONFIG_DRIVER_OMAP34XX_I2C     1
-#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED    100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE    1
+#define CONFIG_SYS_I2C_OMAP34XX
 
 /* EEPROM */
 #define CONFIG_SYS_I2C_MULTI_EEPROMS