]> git.sur5r.net Git - u-boot/log
u-boot
7 years agoenv: common: Make env_get_addr/get_char_memory() static
Simon Glass [Thu, 3 Aug 2017 18:21:51 +0000 (12:21 -0600)]
env: common: Make env_get_addr/get_char_memory() static

These functions are not used outside this file. Make them static and order
them to avoid forward declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoenv: Use tabs in ENV_IS_IN_FAT
Simon Glass [Thu, 3 Aug 2017 18:21:50 +0000 (12:21 -0600)]
env: Use tabs in ENV_IS_IN_FAT

Tidy up the formatting of this option.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoMove environment files from common/ to env/
Simon Glass [Thu, 3 Aug 2017 18:21:49 +0000 (12:21 -0600)]
Move environment files from common/ to env/

About a quarter of the files in common/ relate to the environment. It
seems better to put these into their own subdirectory and remove the
prefix.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoMakefile: Rename 'env' target to 'environ'
Simon Glass [Thu, 3 Aug 2017 18:21:48 +0000 (12:21 -0600)]
Makefile: Rename 'env' target to 'environ'

This target stops us using 'env' as a subdirectory. It is not mentioned in
the help so seems to be an internal target. Rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoPrepare v2017.09-rc2 v2017.09-rc2
Tom Rini [Tue, 15 Aug 2017 00:02:11 +0000 (20:02 -0400)]
Prepare v2017.09-rc2

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoconfigs: Resync with savedefconfig
Tom Rini [Mon, 14 Aug 2017 23:58:53 +0000 (19:58 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoMerge git://git.denx.de/u-boot-net
Tom Rini [Mon, 14 Aug 2017 21:06:58 +0000 (17:06 -0400)]
Merge git://git.denx.de/u-boot-net

7 years agocommon: Move CONFIG_BOOTARGS to Kconfig
Sam Protsenko [Mon, 14 Aug 2017 17:22:17 +0000 (20:22 +0300)]
common: Move CONFIG_BOOTARGS to Kconfig

Also introduce CONFIG_USE_BOOTARGS option so we can control if
CONFIG_BOOTARGS defined at all.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
[trini: Resync r8a779[56]_ulcb, various ls10xx targets]
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agodriver: net: ldpaa: Update priv->phydev after free()
Prabhakar Kushwaha [Wed, 15 Feb 2017 15:26:03 +0000 (20:56 +0530)]
driver: net: ldpaa: Update priv->phydev after free()

Even after memory free of phydev, priv is still pointing to the
obsolete address.
So update priv->phydev as NULL after memory free.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agousb: net: Add support for Microchip LAN75xx and LAN78xx
Yuiko Oshino [Fri, 11 Aug 2017 16:44:58 +0000 (12:44 -0400)]
usb: net: Add support for Microchip LAN75xx and LAN78xx

Add support for Microchip LAN7500, LAN7800 and LAN7850,
USB to 10/100/1000 Ethernet Controllers.

Signed-off-by: Yuiko Oshino <yuiko.oshino@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: Add mii_resolve_flowctrl_fdx()
Yuiko Oshino [Fri, 11 Aug 2017 16:44:57 +0000 (12:44 -0400)]
net: Add mii_resolve_flowctrl_fdx()

Add an mii helper function to resolve flow control status per
IEEE 802.3-2005 table 28B-3.
This function was taken from the Linux source tree.

Signed-off-by: Yuiko Oshino <yuiko.oshino@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: fman: add support RGMII_TXID to memac
Madalin Bucur [Fri, 4 Aug 2017 06:14:53 +0000 (09:14 +0300)]
net: fman: add support RGMII_TXID to memac

Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agoARM: rockchip: rock: Correct test to use CONFIG_IS_ENABLED not defined
Tom Rini [Mon, 14 Aug 2017 17:21:44 +0000 (13:21 -0400)]
ARM: rockchip: rock: Correct test to use CONFIG_IS_ENABLED not defined

While it is likely that this entire case is superfluous and can be
removed, correct the test now to match what is in rockchip-common.h and
makes sense based on context of the code.  Otherwise we get a large
number of warnings.

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-rockchip
Tom Rini [Mon, 14 Aug 2017 14:40:01 +0000 (10:40 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-rockchip

7 years agostm32f1: remove stm32f1 support
Patrice Chotard [Wed, 9 Aug 2017 13:13:02 +0000 (15:13 +0200)]
stm32f1: remove stm32f1 support

A few years ago STM32F1 SoCs support has been added :
0144caf22ce6acd5c  gpio: stm32: add stm32f1 support
2d18ef2364fd3561a  ARMv7M: add STM32F1 support

But neither STM32F1 dedicated defconfig nor board was
associated to these commits.

Got confirmation from Tom Rini and Matt Porter to remove
all this code [1]

[1] http://u-boot.10912.n7.nabble.com/Remove-STM32F1-support-td301603.html

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agocmd/bdinfo: correct comment in board_detail
Chris Packham [Mon, 7 Aug 2017 04:04:14 +0000 (16:04 +1200)]
cmd/bdinfo: correct comment in board_detail

This appears to be a simple typo that dates back to the original
implementation of board_detail in commit e79394643b26 ("common: Update
cmd_bdinfo for PPC").

Signed-off-by: Chris Packham <judge.packham@gmail.com>
7 years agotest: Move the FIT test into the correct place
Simon Glass [Sat, 5 Aug 2017 16:28:41 +0000 (10:28 -0600)]
test: Move the FIT test into the correct place

Move this test so that it will run when 'make tests' is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agotest: Convert the FIT test to test/py
Simon Glass [Sat, 5 Aug 2017 16:28:40 +0000 (10:28 -0600)]
test: Convert the FIT test to test/py

Convert this test to use the pytest framework.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agotest: Indent test-fit.py to match the next patch
Simon Glass [Sat, 5 Aug 2017 16:28:39 +0000 (10:28 -0600)]
test: Indent test-fit.py to match the next patch

We plan to rewrite this script to use the pytest framework. To make it
easier to review the changes, indent the code to match the next patch.
This gets all of the whitespace changes out of the way.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agoARM: OMAP5: Enable support for AVS0 for OMAP5 production devices
Nishanth Menon [Sat, 5 Aug 2017 02:42:09 +0000 (21:42 -0500)]
ARM: OMAP5: Enable support for AVS0 for OMAP5 production devices

OMAP5432 did go into production with AVS class0 registers which were
mutually exclusive from AVS Class 1.5 registers.

Most OMAP5-uEVM boards use the pre-production Class1.5 which has
production efuse registers set to 0. However on production devices,
these are set to valid data.

scale_vcore logic is already smart enough to detect this and use the
"Nominal voltage" on devices that do not have efuse registers populated.

On a test production device populated as follows:
MPU OPP_NOM:
=> md.l 0x04A0021C4 1
4a0021c403a003e9                               ....
(0x3e9 = 1.01v) vs nom voltage of 1.06v
MPU OPP_HIGH:
=> md.l 0x04A0021C8 1
4a0021c803400485                               ..@.

MM OPP_NOM:
=> md.l 0x04A0021A4 1
4a0021a4038003d4                               ....
(0x3d4 = 980mV) vs nom voltage of 1.025v
MM OPP_OD:
=> md.l 0x04A0021A8 1
4a0021a803600403                               ..`.

CORE OPP_NOM:
=> md.l 0x04A0021D8 1
4a0021d8000003cf                               ....
(0x3cf = 975mV) vs nom voltage of 1.040v

Since the efuse values are'nt currently used, we do not regress on
existing pre-production samples (they continue to use nominal voltage).

But on boards that do have production samples populated, we can leverage
the optimal voltages necessary for proper operation.

Tested on:
a) 720-2644-001 OMAP5UEVM with production sample.
b) 750-2628-222(A) UEVM5432G-02 with pre-production sample.

Data based on OMAP5432 Technical reference Manual SWPU282AF (May
2012-Revised Aug 2016)

NOTE: All collaterals on OMAP5432 silicon itself seems to have been
removed from ti.com, though EVM details are still available:
http://www.ti.com/tool/OMAP5432-EVM

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP5: Remove OPP_LOW Definitions for ES2.0
Nishanth Menon [Sat, 5 Aug 2017 02:42:08 +0000 (21:42 -0500)]
ARM: OMAP5: Remove OPP_LOW Definitions for ES2.0

ES2.0 descopes OPP_LOW definition. So remove it from macros defined.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agotest: Fix FIT test to pass again
Simon Glass [Fri, 4 Aug 2017 22:20:16 +0000 (16:20 -0600)]
test: Fix FIT test to pass again

A recent change adjusted a test string so that the test no-longer passes.
Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Heiko Schocher <hs@denx.de>
Fixes: b28c5fcc (test-fit.py: Minor grammar/spelling/clarification tweaks)
7 years agowdt: Update uclass to make clear that the timeout is in ms
Andy Shevchenko [Fri, 4 Aug 2017 21:48:28 +0000 (15:48 -0600)]
wdt: Update uclass to make clear that the timeout is in ms

Convert name to show explicitly that we are using milliseconds. For a
watchdog timer this is precise enough.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7 years agoboot_fit: Change return value from FDT_ERROR to -EINVAL in fdt_offset()
Nobuhiro Iwamatsu [Fri, 4 Aug 2017 20:47:02 +0000 (05:47 +0900)]
boot_fit: Change return value from FDT_ERROR to -EINVAL in fdt_offset()

FDT_ERROR is defined as unsigned long. However, since the return value of
fdt_offset() is int, a warning will occur when compiling. Also, it is better
to use -EINVAL than FDT_ERROR.
This fixes this problem by change return value from FDT_ERROR to -EINVAL.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Franklin S Cooper Jr <fcooper@ti.com>
7 years agox86: qemu: Enable NVMe driver
Bin Meng [Thu, 3 Aug 2017 09:31:03 +0000 (02:31 -0700)]
x86: qemu: Enable NVMe driver

QEMU supports NVMe emulation. Enable the NVMe driver on QEMU x86.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agonvme: Handle zero Maximum Data Transfer Size (MDTS)
Bin Meng [Thu, 3 Aug 2017 09:31:02 +0000 (02:31 -0700)]
nvme: Handle zero Maximum Data Transfer Size (MDTS)

Maximum Data Transfer Size (MDTS) field indicates the maximum
data transfer size between the host and the controller. The
host should not submit a command that exceeds this transfer
size. The value is in units of the minimum memory page size
and is reported as a power of two (2^n).

The spec also says: a value of 0h indicates no restrictions
on transfer size. On the real NVMe card this is normally not
0 due to hardware restrictions, but with QEMU emulated NVMe
device it reports as 0. In nvme_blk_read/write() below we
have the following algorithm for maximum number of logic
blocks per transfer:

u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);

dev->max_transfer_shift being 0 will for sure cause lbas to
overflow. Let's use 20. With this fix, the NVMe driver works
on QEMU emulated NVMe device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agonvme: Fix number of blocks detection
Jon Nettleton [Thu, 3 Aug 2017 09:31:01 +0000 (02:31 -0700)]
nvme: Fix number of blocks detection

NVMe should use the nsze value from the queried device. This will
reflect the total number of blocks of the device and fix detecting
my Samsung 960 EVO 256GB.

Original:
Capacity: 40386.6 MB = 39.4 GB (82711872 x 512)

Fixed:
Capacity: 238475.1 MB = 232.8 GB (488397168 x 512)

Signed-off-by: Jon Nettleton <jon@solid-run.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agonvme: Detect devices that are class Storage Express
Jon Nettleton [Thu, 3 Aug 2017 09:31:00 +0000 (02:31 -0700)]
nvme: Detect devices that are class Storage Express

This adds support to detect the catchall PCI class for NVMe devices.
It allows the drivers to work with most NVMe devices that don't need
specific detection due to quirks etc.

Tested against a Samsung 960 EVO drive.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agonvme: Add nvme commands
Zhikang Zhang [Thu, 3 Aug 2017 09:30:59 +0000 (02:30 -0700)]
nvme: Add nvme commands

Add nvme commands in U-Boot command line.

1. "nvme scan" - scan NVMe blk devices
2. "nvme list" - show all available NVMe blk devices
3. "nvme info" - show current or a specific NVMe blk device
4. "nvme device" - show or set current device
5. "nvme part" - print partition table
6. "nvme read" - read data from NVMe blk device
7. "nvme write" - write data to NVMe blk device

Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agonvme: Add show routine to print detailed information
Zhikang Zhang [Thu, 3 Aug 2017 09:30:58 +0000 (02:30 -0700)]
nvme: Add show routine to print detailed information

This adds nvme_print_info() to show detailed NVMe controller and
namespace information.

Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agonvme: Add NVM Express driver support
Zhikang Zhang [Thu, 3 Aug 2017 09:30:57 +0000 (02:30 -0700)]
nvme: Add NVM Express driver support

NVM Express (NVMe) is a register level interface that allows host
software to communicate with a non-volatile memory subsystem. This
interface is optimized for enterprise and client solid state drives,
typically attached to the PCI express interface.

This adds a U-Boot driver support of devices that follow the NVMe
standard [1] and supports basic read/write operations.

Tested with a 400GB Intel SSD 750 series NVMe card with controller
id 8086:0953.

[1] http://www.nvmexpress.org/resources/specifications/

Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agodm: blk: part: Add UCLASS_NVME and IF_TYPE_NVME
Zhikang Zhang [Thu, 3 Aug 2017 09:30:56 +0000 (02:30 -0700)]
dm: blk: part: Add UCLASS_NVME and IF_TYPE_NVME

This adds a new uclass id and block interface type for NVMe.

Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoarm: mvebu: ddr3_debug: remove self assignments
xypron.glpk@gmx.de [Sun, 30 Jul 2017 19:54:56 +0000 (21:54 +0200)]
arm: mvebu: ddr3_debug: remove self assignments

Remove superfluous self assignements.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoarm: mvebu: remove self assignment
xypron.glpk@gmx.de [Sun, 30 Jul 2017 19:51:05 +0000 (21:51 +0200)]
arm: mvebu: remove self assignment

Assigning dev_num to itself is superfluous.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agotpm: add missing va_end
xypron.glpk@gmx.de [Sun, 30 Jul 2017 19:40:37 +0000 (21:40 +0200)]
tpm: add missing va_end

va_start must always be matched by va_end.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoARM: hisilicon: hikey: do not rely on random stack value
xypron.glpk@gmx.de [Sun, 30 Jul 2017 19:30:55 +0000 (21:30 +0200)]
ARM: hisilicon: hikey: do not rely on random stack value

If CONFIG_MMC_DW is not defined the return value of
init_dwmmc should not rely on a random stack value.

Instead indicate that no error occured.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agostm32: remove redundant 'else if'
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:46:05 +0000 (20:46 +0200)]
stm32: remove redundant 'else if'

The if in the else branch is superfluous.
We can use a simple if.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agoarm: mvebu: avoid possible NULL dereference
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:40:43 +0000 (20:40 +0200)]
arm: mvebu: avoid possible NULL dereference

It does not make sense to check if info is NULL after
dereferencing it.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
7 years agoarmv7m: mpu_config add missing break
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:34:20 +0000 (20:34 +0200)]
armv7m: mpu_config add missing break

For DEVICE_NON_SHARED the newly assigned value of attr
is overwritten due to a missing break.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agobcm281xx: clock: avoid possible NULL dereference
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:27:16 +0000 (20:27 +0200)]
bcm281xx: clock: avoid possible NULL dereference

It does not make sense first to dereference c and then
to check if it is NULL.

The problem was indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agoarm: bcm235xx: clk_set_rate avoid possible NULL deref
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:22:47 +0000 (20:22 +0200)]
arm: bcm235xx: clk_set_rate avoid possible NULL deref

It does not make sense first to dereference c and then
to check if it is NULL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agoarm: bcm235xx: avoid possible NULL dereference
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:15:51 +0000 (20:15 +0200)]
arm: bcm235xx: avoid possible NULL dereference

It does not make sense to first dereference c and then
check if it is NULL.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agoarm: spear: do not return random value from stack
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:09:38 +0000 (20:09 +0200)]
arm: spear: do not return random value from stack

If the NOR device is not available do not return
a random value from the stack.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
7 years agoapi: remove superfluous assignment
xypron.glpk@gmx.de [Sun, 30 Jul 2017 17:54:37 +0000 (19:54 +0200)]
api: remove superfluous assignment

No need to assign a value to sig if the next statement using sig
is itself an assignment of a value to sig.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoConvert CONFIG_OMAP3_SPI to Kconfig
Adam Ford [Thu, 27 Jul 2017 03:25:30 +0000 (22:25 -0500)]
Convert CONFIG_OMAP3_SPI to Kconfig

This converts the following to Kconfig:
   CONFIG_OMAP3_SPI

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Minor comment tweaks]
Signed-off-by: Tom Rini <trini@konsulko.com>
7 years agorockchip: clk: remove RATE_TO_DIV
Kever Yang [Thu, 27 Jul 2017 04:54:02 +0000 (12:54 +0800)]
rockchip: clk: remove RATE_TO_DIV

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: clk: update dwmmc clock div
Kever Yang [Thu, 27 Jul 2017 04:54:01 +0000 (12:54 +0800)]
rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: rk322x: update max-frequency for mmc node
Kever Yang [Thu, 27 Jul 2017 04:54:00 +0000 (12:54 +0800)]
rockchip: rk322x: update max-frequency for mmc node

mmc using 150000000 as max-frequency like what rk3288 sets.
This can speed up the mmc read/write, the actual mmc clock is:
Before this patch: 37.125M
After this patch: 49.5M

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: dts: rk322x: add sdmmc device node
Kever Yang [Fri, 21 Jul 2017 10:21:09 +0000 (18:21 +0800)]
rockchip: dts: rk322x: add sdmmc device node

add node for sdmmc in dts and rk3229-evb.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agoscripts: setlocalversion: safely extract variables from auto.conf using awk
Philipp Tomsich [Tue, 8 Aug 2017 13:26:12 +0000 (15:26 +0200)]
scripts: setlocalversion: safely extract variables from auto.conf using awk

Moving SPL_LDSCRIPT to Kconfig triggered an unfortunate attempt of
command substitution, as the sourced auto.conf may include $(ARCH)
which tries to execute a command 'ARCH'.
This showed up as a warning similar to the following:
  include/config/auto.conf: line 209: ARCH: command not found

This change does no longer attempt to source auto.conf, but rather
passes it through awk to retrieve the values for CONFIG_LOCALVERSION
and CONFIG_LOCALVERSION_AUTO.  This will also mitigate the risk of
unintended command substitution.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
7 years agorockchip: rk322x: set the DDR region as non-secure in SPL
Kever Yang [Thu, 27 Jul 2017 04:53:59 +0000 (12:53 +0800)]
rockchip: rk322x: set the DDR region as non-secure in SPL

Disable the ddr secure region setting in SPL and the ddr memory
becomes non-secure, every one can access it. the trust firmware
like OPTEE should have the correct setting for it after SPL if
there is one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: rk3288: fix EMMC_DIV_MASK definition in header
Kever Yang [Mon, 31 Jul 2017 01:28:14 +0000 (09:28 +0800)]
rockchip: rk3288: fix EMMC_DIV_MASK definition in header

It should be '<<' instead of '<' for _MASK definition, fix it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: spl: move SPL_LDSCRIPT to Kconfig
Philipp Tomsich [Fri, 4 Aug 2017 12:12:26 +0000 (14:12 +0200)]
rockchip: rk3368: spl: move SPL_LDSCRIPT to Kconfig

With the new way of doing things (i.e. the hierarchical selection of
SPL_LDSCRIPT via Kconfig) in place, this moves the SPL_LDSCRIPT setting
for the RK3368 from defconfig back into Kconfig.

With this done, there should be no lingering cases of SPL_LDSCRIPT
outside of Kconfig files.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agospl: moveconfig: remove SPL_LDSCRIPT definitions for header-files
Philipp Tomsich [Fri, 4 Aug 2017 12:01:32 +0000 (14:01 +0200)]
spl: moveconfig: remove SPL_LDSCRIPT definitions for header-files

With the hierarchical defaults set up, we remove these from the header
files.  To do so, I've run moveconfig on SPL_LDSCRIPT and this commits
the changes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agospl: add hierarchical defaults for SPL_LDSCRIPT
Philipp Tomsich [Thu, 3 Aug 2017 21:23:55 +0000 (23:23 +0200)]
spl: add hierarchical defaults for SPL_LDSCRIPT

With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config
node), all the lingering definitions in header files will cause
warnings/errors due to the redefinition of the configuration item.

As we don't want to pollute the defconfig files (and values should
usually be identical for entire architectures), the defaults are moved
into Kconfig.  Kconfig will always pick the first default that
matches, so please keep these values at the end of each file (to allow
any board-specific Kconfig, which will be included earlier) to
override with an unconditional default setting.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3188: rock: adjust for SPL/TPL split
Philipp Tomsich [Thu, 3 Aug 2017 20:52:04 +0000 (22:52 +0200)]
rockchip: rk3188: rock: adjust for SPL/TPL split

With the changes to split SPL/TPL for the RK3368, I apparently missed
some needed adjustments to the RK3188 Kconfig and rock_defconfig.

This fixes build-issues for the rock board after applying the RK3368
enablement (and SPL/TPL) set that resulted from TPL_SERIAL_SUPPORT,
TPL_ROCKCHIP_BACK_TO_BROM and TPL_TINY_MEMSET being separate symbols
now.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: remove the hard coded uart iomux setting for px5 evb
Andy Yan [Wed, 2 Aug 2017 13:10:56 +0000 (21:10 +0800)]
rockchip: remove the hard coded uart iomux setting for px5 evb

As the debug uart is marked as dm-pre-reloc, the pinctrl driver
will handle the correct iomux setting.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: set Pre-reloc malloc pool size to 4kb for rk3368 based boards
Andy Yan [Wed, 2 Aug 2017 13:10:13 +0000 (21:10 +0800)]
rockchip: set Pre-reloc malloc pool size to 4kb for rk3368 based boards

The default 1kb pre-reloc malloc pool is not enough for dm
core to enable the dm-pre-reloc device drivers.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agorockchip: add u-boot specific dts for rk3368 based boards
Andy Yan [Wed, 2 Aug 2017 13:08:59 +0000 (21:08 +0800)]
rockchip: add u-boot specific dts for rk3368 based boards

Device drivers like debug serial, dmc should be enabled before
relocation, so add u-boot.dtsi files to contain devices that
should be marked as dm-pre-reloc.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: remove setup of secure timer from TPL/SPL
Philipp Tomsich [Fri, 28 Jul 2017 16:01:49 +0000 (18:01 +0200)]
rockchip: rk3368: remove setup of secure timer from TPL/SPL

When using DM timers w/ the timer0 block within the RK3368, we no
longer depend on the ARMv8 generic timer counting.  This allows us to
drop the secure timer initialisation from the TPL and SPL stages.

The secure timer will later be set up by ATF, which starts the ARMv8
generic timer.  Thus, there will be a dependency from Linux to the ATF
through the ARMv8 generic timer... this seems reasonable, as Linux
will require the ATF (and PSCI) to start up the secondary cores anyway
(in other words: we don't add any new dependencies).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: lion-rk3368: defconfig: enable DM timer for all stages
Philipp Tomsich [Fri, 28 Jul 2017 16:00:27 +0000 (18:00 +0200)]
rockchip: lion-rk3368: defconfig: enable DM timer for all stages

There is no reasonably robust way (this will be needed so early that
diagnostics will be limited) to specify the base-address of the secure
timer through the DTS for TPL and SPL.  In order to allow us a cleaner
way to structure our SPL and TPL stage, we now move to a DM timer
driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodts: rk3368: make timer0 accessible for SPL and TPL
Philipp Tomsich [Fri, 28 Jul 2017 15:46:39 +0000 (17:46 +0200)]
dts: rk3368: make timer0 accessible for SPL and TPL

To use it with the DM timer driver in SPL and TPL, timer0 needs to be
marked as pre-reloc.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: timer: add device-model timer driver for RK3368 (and similar)
Philipp Tomsich [Fri, 28 Jul 2017 15:43:19 +0000 (17:43 +0200)]
rockchip: timer: add device-model timer driver for RK3368 (and similar)

This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such as the RK3288) for
the down-counting (i.e. non-secure) timers.

This allows us to configure U-Boot for the RK3368 in such a way that
we can run with the secure timer inaccessible or uninitialised (note
that the ARMv8 generic timer does not count, if the secure timer is
not enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: timer: normalise SPL and TPL support
Philipp Tomsich [Fri, 28 Jul 2017 15:38:42 +0000 (17:38 +0200)]
dm: timer: normalise SPL and TPL support

To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
  decision for each stage and under control of $(SPL_TPL_)TIMER
  instead of having the two-level configuration with TIMER and
  $(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
  not be compiled in

This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agotimer: add OF_PLATDATA support for timer-uclass
Philipp Tomsich [Fri, 28 Jul 2017 15:19:58 +0000 (17:19 +0200)]
timer: add OF_PLATDATA support for timer-uclass

The timer-uclass depends on full OF_CONTROL through its interrogation
of /chosen and the code to determine the clock-frequency.

For the OF_PLATDATA case, these code-paths are disabled and it becomes
the timer driver's responsibility to correctly set the clock-frequency
in the uclass priv-data.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoconfigs: mpc85xx: fix fallout from SPL/TPL changes
Philipp Tomsich [Fri, 11 Aug 2017 18:35:30 +0000 (20:35 +0200)]
configs: mpc85xx: fix fallout from SPL/TPL changes

Splitting the feature selection for SPL and TPL, caused a few build
failures to mpx85xx boards.  This fixes the fallout by adding the
needed new option names to the respective defconfig files.

Signed-off-byL Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

7 years agorockchip: board: puma_rk3399: rename ATF firmware
Klaus Goger [Tue, 18 Jul 2017 19:41:28 +0000 (21:41 +0200)]
rockchip: board: puma_rk3399: rename ATF firmware

prefix the bl31 firmware needed to build uboot.itb so it can coexist in
the build area with ATFs from other boards (i.e. lion_rk3368)

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its
Philipp Tomsich [Fri, 5 May 2017 10:33:24 +0000 (12:33 +0200)]
rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its

The ITS file generated warnings due to @<num> designations in the naming
which cause DTC to complain as follows:
  Warning (unit_address_vs_reg): Node /images/uboot@1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /images/atf@1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /images/pmu@1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /configurations/conf@1 has a unit name, but no reg property

This removes the @<num> part from the names, as we only have a single
image for each payload aspect (and only a single configuration) anyway.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agomoveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
Philipp Tomsich [Fri, 28 Jul 2017 18:20:41 +0000 (20:20 +0200)]
moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE

We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the
whitelist (this time it's really happening!) and migrate the setting
(only used on the RK3368-uQ7 so far) into Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL
Philipp Tomsich [Fri, 28 Jul 2017 18:03:07 +0000 (20:03 +0200)]
rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL

The RK3368 needs to have a different base-address and stack-pointer
for its TPL stage.  Now that we want to do this via Kconfig, we need
to tick the appropriate 'TPL_NEEDS_...' boxes.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoarmv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK
Philipp Tomsich [Fri, 28 Jul 2017 18:04:09 +0000 (20:04 +0200)]
armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK

Now that TPL_STACK has been moved off the whitelist (ok, I'm lying:
the 'moving off the whitelist' part comes in once moveconfig
runs... which will be a few commits down the line) and added to
Kconfig, we need to test CONFIG_TPL_NEEDS_SEPARATE_STACK to see
whether the value from TPL_STACK should be used or whether we try to
inherit whatever SPL uses.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agospl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig
Philipp Tomsich [Fri, 28 Jul 2017 18:02:34 +0000 (20:02 +0200)]
spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig

Let's clean up behind ourselves and move the (newly defined)
TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE into Kconfig.  Given that
0x0 might be considered to be valid values for TPL_TEXT_BASE and
TPL_STACK, we need to introduce helper config options
("TPL_NEEDS_SEPARATE_...") to indicate that these symbols are used
(and not inherited from their SPL variants) for any given
target-platform.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: Kconfig: preset TPL_LDSCRIPT via Kconfig for the RK3368
Philipp Tomsich [Wed, 2 Aug 2017 19:26:18 +0000 (21:26 +0200)]
rockchip: Kconfig: preset TPL_LDSCRIPT via Kconfig for the RK3368

Set TPL_LDSCRIPT in Kconfig, so we don't have to pollute our
header file.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
7 years agospl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig
Philipp Tomsich [Fri, 28 Jul 2017 17:20:49 +0000 (19:20 +0200)]
spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig

Now that we have split up SPL_LDSCRIPT into a SPL and TPL variant and
have started to use the TPL-variant for the RK3368, it's time to clean
up behind ourselves: move both variants into Kconfig and remove them
from the whitelist.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: board: lion-rk3368: add support for the RK3368-uQ7
Philipp Tomsich [Wed, 12 Jul 2017 23:36:39 +0000 (01:36 +0200)]
rockchip: board: lion-rk3368: add support for the RK3368-uQ7

The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
MXM-230 edge connector compatible with the Qseven specification)
form-factor system-on-module based on the octo-core Rockchip RK3368.
It is designed, supported and manufactured by Theobroma Systems.

It provides the following features:
 - 8x Cortex-A53 (in 2 clusters of 4 cores each)
 - (on-module) up to 4GB of DDR3 memory
 - (on-module) SPI-NOR flash
 - (on-module) eMMC
 - Gigabit Ethernet (with an on-module KSZ9031 PHY)
 - USB
 - HDMI
 - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
 - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spi: enable support for the rk_spi driver for the RK3368
Philipp Tomsich [Tue, 25 Jul 2017 14:25:30 +0000 (16:25 +0200)]
rockchip: spi: enable support for the rk_spi driver for the RK3368

For the RK3368, we can reuse the SPI driver (although we'll have to
eventually investigate whether it can be merged with the
designware_spi.c driver) also used for the RK3288 and RK3399.
This adds the necessary compatible string to support the RK3368.

Note that the assumption that GPLL will be clocked at 594MHz is not
true for the RK3368, but this will not lead to incorrect functioning
(just to a lower-than-expected SPI operating frequency): this has been
documented in the driver, so it doesn't cause any headaches when
someone next needs to touch the clock code of this driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
Philipp Tomsich [Sun, 11 Jun 2017 21:46:25 +0000 (23:46 +0200)]
rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368

With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
supported from Kconfig for the RK3368.  As this is primarily tested on
the RK3368-uQ7, we'll leave it to board's individual defconfig to
enable.

Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
during the early boot-up, as we turn on TPL and SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: spl: add SPL support
Philipp Tomsich [Mon, 12 Jun 2017 08:33:20 +0000 (10:33 +0200)]
rockchip: rk3368: spl: add SPL support

Adds SPL support for the RK3368 (assuming that our TPL stage has
initialised DRAM and set up the memory firewall).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: spl: make spl-boot-order code reusable (split from rk3399)
Philipp Tomsich [Wed, 19 Jul 2017 20:04:32 +0000 (22:04 +0200)]
rockchip: spl: make spl-boot-order code reusable (split from rk3399)

In order to reuse the support for the u-boot,spl-boot-order property
from the rk3399, we split it into a reusable module that can be
included by the SPL code for any of our boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: spl: add TPL support
Philipp Tomsich [Tue, 4 Jul 2017 12:40:01 +0000 (14:40 +0200)]
rockchip: rk3368: spl: add TPL support

This adds the TPL support for the RK3368, including the u-boot-tpl.lds.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h
Philipp Tomsich [Fri, 14 Jul 2017 15:51:44 +0000 (17:51 +0200)]
rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h

To build TPL and SPL stages for the RK3368, we will also need to
enable the SPL_FRAMEWORK.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: dts: add DMC node in rk3368.dtsi
Philipp Tomsich [Thu, 22 Jun 2017 22:27:31 +0000 (00:27 +0200)]
rockchip: rk3368: dts: add DMC node in rk3368.dtsi

For full SPL support, including DRAM initialisation, we need a few
nodes from the DTS: this commit adds the DMC (DRAM controller) node,
the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
as 'u-boot,dm-pre-reloc'.  In addition to this, we also include the
dt-binding for the DMC to allow DTS files including this DTSI to refer
to the symbolic constants for the DDR3 bin and for the
memory-schedule.

Note that the DMC contains both the memory regions for the
(Designware) protocol controller as well as the DDR PHY.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: add DRAM controller driver with DRAM initialisation
Philipp Tomsich [Thu, 22 Jun 2017 22:12:05 +0000 (00:12 +0200)]
rockchip: rk3368: add DRAM controller driver with DRAM initialisation

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
 - DDR3
 - 32-bit configuration (i.e. fully populated)
 - dual-rank (i.e. no auto-detection of ranks)
 - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: Makefile: streamline SPL/TPL configuration
Philipp Tomsich [Tue, 4 Jul 2017 12:38:28 +0000 (14:38 +0200)]
rockchip: Makefile: streamline SPL/TPL configuration

Handling TPL and SPL in the Makefile for mach-rockchip was based on
nested if checks and/or if-else-if paths.  This can be simplified and
made more readable by using $(SPL_TPL_) and by introducing
intermediate variables for the aggregation of SPL and TPL features.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agonet: gmac_rockchip: Add support for the RK3368 GMAC
Philipp Tomsich [Tue, 25 Jul 2017 15:02:51 +0000 (17:02 +0200)]
net: gmac_rockchip: Add support for the RK3368 GMAC

The GMAC in the RK3368 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3368-specific logic necessary to reuse this driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
7 years agorockchip: clk: rk3368: add support for configuring the SPI clocks
Philipp Tomsich [Tue, 25 Jul 2017 14:48:16 +0000 (16:48 +0200)]
rockchip: clk: rk3368: add support for configuring the SPI clocks

As SPI support may be useful in the boot-flow, this adds support for
configuring the SPI controller's clocks in the RK3368 clock driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()
Philipp Tomsich [Wed, 5 Jul 2017 10:11:58 +0000 (12:11 +0200)]
rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()

With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e.g. in the
SPL build when only MMC is enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock
Philipp Tomsich [Fri, 14 Jul 2017 17:57:39 +0000 (19:57 +0200)]
rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock

To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.

This adds an implementation that implements the use of the <&ext_gmac>
clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
This is the clock setup used by the boards currently supported by
U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).

This includes the change from commit
 - rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)
Philipp Tomsich [Wed, 5 Jul 2017 09:55:23 +0000 (11:55 +0200)]
rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)

As part of the DRAM initialisation process (running as part of the TPL
stage) on the RK3368, we need to set up the DRAM PLL.

This implements support for configuring the PLL to for 1200, 1332 or
1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: implement MMC/SD clock reparenting
Philipp Tomsich [Tue, 4 Jul 2017 12:49:38 +0000 (14:49 +0200)]
rockchip: clk: rk3368: implement MMC/SD clock reparenting

The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving the requested clock-rate: this can lead to higher-than-expected
(or rather: higher than supported) clock rates for the MMC/SD
communiction.

This change rewrites the MMC/SD clock generation to:
 * always generate a clock less-than-or-equal to the requested clock
 * support reparenting among the CPLL, GPLL and OSC24M parents to
   generate the highest clock that does not exceed the requested rate

In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
always works), we adjust the driver appropriately.

This includes the changes from:
 - rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ
Philipp Tomsich [Tue, 4 Jul 2017 12:50:11 +0000 (14:50 +0200)]
rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ

On he RK3368, we need to temporarily disable security on the DMA
engines during TPL and SPL to allow the MMC host to DMA into DRAM.  To
do so, we need to reset the two DMA engines, which in turn requires
the DMA1_SRST_REQ and DMA2_SRST_REQ constants to refer to the
appropriate bits in the CRU.

As the ATF correctly initialises security (and only leaves EL3 after
doing so), this can not pose a security issue.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: implement DPLL (DRAM PLL) support
Philipp Tomsich [Thu, 22 Jun 2017 22:01:10 +0000 (00:01 +0200)]
rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM
Philipp Tomsich [Thu, 22 Jun 2017 21:53:44 +0000 (23:53 +0200)]
rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM

The RK3368 has a somewhat temperamental BootROM (which I learned the
hard way) when it comes to reconfiguring the CPLL and GPLL (in fact,
experiments show that changing the GPLL broke things for me, while
changing the CPLL seems to be more benign).  These should not be
modified by the SPL stage, if we intend to return to the BootROM for
chain booting the next stage.

This commit changes the clock initialisation to not change CPLL/GPLL
before returning to the BootROM (i.e. in TPL).  As it's safe to change
these settings if we no longer intend to return to U-Boot, we'll run
the full PLL setup a little later (i.e. in SPL).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver
Philipp Tomsich [Thu, 22 Jun 2017 21:51:37 +0000 (23:51 +0200)]
rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver

With the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for
the SPL stage.  This implements support for OF_PLATDATA in the clock
driver for the RK3368.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: clk: rk3368: implement bandwidth adjust for PLLs
Philipp Tomsich [Thu, 22 Jun 2017 21:47:11 +0000 (23:47 +0200)]
rockchip: clk: rk3368: implement bandwidth adjust for PLLs

The RK3368 TRM recommends to configure the bandwith adjustment (CON2)
for PLLs to NF/2.  This implements this for all reconfigurations of
PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the
bandwidth-adjustment feature according to its manual).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3368: add SPI support
Philipp Tomsich [Tue, 25 Jul 2017 14:25:10 +0000 (16:25 +0200)]
rockchip: pinctrl: rk3368: add SPI support

To implement pinctrl support for the RK3368, we need to add the
bit-definitions to configure the IOMUX and tie these into the
pinctrl framework. This also adds the mapping from the IRQ# back
onto the periheral id for the SPI devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver
Philipp Tomsich [Tue, 25 Jul 2017 15:09:23 +0000 (17:09 +0200)]
rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver

There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).

This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3368: add support for configuring the MMC pins
Philipp Tomsich [Fri, 14 Jul 2017 18:07:11 +0000 (20:07 +0200)]
rockchip: pinctrl: rk3368: add support for configuring the MMC pins

The RK3368 has two SD/MMC controllers that can be used from U-Boot
both during SPL and for booting an OS from the full bootloader stage.
While both are configured to (mostly) sensible settings from the BROM,
additional configuration for the MMC controller is needed to configure
it to 8bit mode.

This adds pinctrl support for the MMC controller.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: pinctrl: rk3368: add GMAC (RGMII only) support
Philipp Tomsich [Fri, 14 Jul 2017 18:00:58 +0000 (20:00 +0200)]
rockchip: pinctrl: rk3368: add GMAC (RGMII only) support

To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration.  This commit
adds the pinctrl support for GMAC in RGMII mode:
 * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
 * configures the RGMII pins

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agorockchip: rk3368: dts: add sgrf node
Philipp Tomsich [Fri, 28 Jul 2017 09:37:33 +0000 (11:37 +0200)]
rockchip: rk3368: dts: add sgrf node

We will to drop device security temporarily (until the ATF initialises
it fully) from the TPL/SPL stage: this requires access to some
registers in the SGRF.

This adds the sgrf node to the rk3368.dtsi, so we can then bind a
syscon device onto it and access its memory ranges.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>