Edward Fewell [Thu, 28 Dec 2017 23:38:21 +0000 (17:38 -0600)]
flash/nor: Add support for TI CC3220SF internal flash
Added cc3220sf flash driver to support the TI CC3220SF
microcontrollers. Implemented flash driver to support the
internal flash of the CC3220SF. The implementation does not
support the serial flash of the CC32xx family that requires
connection over UART, and not via JTAG/SWD debug. Added config
files for both CC32xx devices (no flash) and CC3220SF (with
flash).
Updated to implement comments from code review.
Additional updates to handle remaining comments from review.
Additional updates per review.
Added code to only request aligned writes and full 32-bit
words down to flash helper algorithm. Updated for recent
changes in OpenOCD flash code.
Removed cc32xx.cfg file made obsolete by this patch.
Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47 Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4319 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Omair Javaid [Thu, 31 May 2018 00:36:53 +0000 (05:36 +0500)]
Fix Semihosting FileIO for targets using vcont packet
This patch fixes a bug where target fails to resume after completing GDB FileIO.
We need to update target last run control information to decide resumption. This
was not being done for vcont packets.
Christopher Head [Fri, 27 Apr 2018 01:09:36 +0000 (18:09 -0700)]
target/cortex_m: constify some variables
Change-Id: I1f3fddd89597333fc1bb9535c0cd76ca3e008324 Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4503 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
flash/nor/core: fix double-free crash with 'virtual' flash banks
flash_bank structure of 'virtual' flash driver is a full copy of
the master flash_bank structure including bank->sectors and
bank->prot_blocks pointers. These pointers point to memory
locations allocated by the master driver and thus master driver
is responsible for deallocating them.
Do not free bank->sectors and bank->prot_blocks of 'virtual'
driver since they were already released by master flash driver.
Antonio Borneo [Sun, 27 May 2018 15:37:38 +0000 (17:37 +0200)]
target: fix syntax in help message
The name of the command is already printed before the string
in ->usage, thus it appears twice.
E.g.
> help examine
stm32f4x.cpu arp_examine arp_examine ['allow-defer']
used internally for reset processing
stm32f4x.cpu examine_deferred examine_deferred
used internally for reset processing
stm32f4x.cpu was_examined was_examined
used internally for reset processing
Remove the command name from the string in ->usage.
Liviu Ionescu [Sun, 13 May 2018 15:39:06 +0000 (18:39 +0300)]
Rework/update ARM semihosting
In 2016, ARM released the second edition of the semihosting specs
("Semihosting for AArch32 and AArch64"), adding support for 64-bits.
To ease the reuse of the semihosting logic for other platforms
(like RISC-V), the semihosting code was isolated from the ARM
target and updated to the latest specs.
The new code is already in use since January (in GNU MCU Eclipse
OpenOCD) and no problems were reported, neither for ARM nor for
RISC-V targets, after more than 7K downloads.
Edward Fewell [Tue, 2 Jan 2018 21:27:51 +0000 (15:27 -0600)]
jtag/drivers: Add support for TI XDS110 debug probe
Add support for the XDS110 debug probe using the APIs in the
probe's firmware. Includes support for older versions of the
firmware (with reduced performance) and support for a newer
version that includes OpenOCD specific APIs. Tested on various
TI LauchPads including MSP432P4, MSP432E4, CC2650, CC2652, and
CC3220SF.
Updated to add better support for swd switch. Removed issues found with
clang static analysis.
Updated to add rules entry for the XDS110 probe and Tiva DFU mode (which
affects both XDS110 and ICDI probes).
Philipp Tomsich [Fri, 27 Apr 2018 17:59:56 +0000 (19:59 +0200)]
arm_dpm: flush both scratch registers (R0 and R1)
Neither the initial loop to clear dirty registers (which visits all
registers starting at R2 and counting upwards) nor the final explicit
flushes ensure a write-back in arm_dpm_write_dirty_registers.
This change makes sure that both our scratch registers (i.e. R0 and
R1) are written back to the target.
Faisal Shah [Tue, 10 Apr 2018 03:46:45 +0000 (22:46 -0500)]
ChibiOS thread states: Update thread state to label mapping
Fixed style issue.
Removed #define with list of strings, and just put the
strings in the array initialization directly.
Removed empty space at the start of line.
Change-Id: I76580be203d7d69b8c5b5440f820156543e0d5cc Signed-off-by: Faisal Shah <faisal.shah@gmail.com>
Reviewed-on: http://openocd.zylin.com/4488 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Bohdan Tymkiv [Wed, 21 Mar 2018 14:13:28 +0000 (16:13 +0200)]
psoc6: Run flash algorithm asynchronously to improve performance
Existing psoc6 driver starts flash algorithm for each Flash row. This is
suboptimal from performance point of view, starting/stopping flash
algorithm for each row adds significant overhead. This change starts
flash algorithm and leaves it running asynchronously while driver
performs flash operations.
Performance gain is 170...250% depending on probe:
board: add configuration for stm32f103c8 "Blue Pill"
The "Blue Pill" is a popular development board with an STM32F103C8
micro controller. According to sources, it has a 128kB Flash on board
even though the option bytes only report 64kB. This patch therefore also
modifies target/stm32f1x.cfg to take an optional FLASH_SIZE variable into
account which the board file sets to 0x20000.
Marek Vasut [Wed, 11 Apr 2018 15:15:01 +0000 (17:15 +0200)]
tcl/target: Add Renesas R-Car R8A7790 H2 target
Add configuration for the Renesas R-Car R8A7790 H2 target.
This is an SoC with four Cortex A15 and four Cortex A7
ARMv7a cores, only the four A15 cores are supported.
Tomas Vanek [Thu, 22 Feb 2018 23:12:50 +0000 (00:12 +0100)]
target/cortex_m: allow setting the type of a breakpoint
Cortex-M target used 'auto_bp_type' mode. The requested type
of breakpoint was ignored and hard (FPB) breakpoints were set in
'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above
0x20000000.
The code memory area of Cortex-M does not mean the memory is flash and
vice versa. External flash (parallel or QSPI) is usually mapped above
code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis
has a RAM block under 0x20000000 boundary.
Remove 'auto_bp_type' mode, set breakpoints to requested type.
Change 'cortex_m maskisr auto' handling to use a hard temporary
breakpoint everywhere: it can also workaround not working soft breakpoints
on Cortex-M7 with ICache enabled.
tcl/board: add board configuration for NXP IMX7SABRE
configuration also contains a reset-init procedure that disables the
watchdog and initilizes the boards DDR memory so that you can upload
baremetal (e.g. boot loader) code into DDR and start it from there.
Tomas Vanek [Thu, 15 Feb 2018 09:18:37 +0000 (10:18 +0100)]
flash/nor/at91sam: implement flash bank deallocation for SAM series
Microchip (former Atmel) SAM drivers allocate a struct per chip.
at91sam3, at91sam34:
Deallocate all chip structs from the list at once, on the first bank
deallocation.
at91samd and at91sam4l drivers do not handle more than one bank.
Convert them to simple driver_priv allocation and use
default_flash_free_driver_priv().
Change-Id: I49d7200f38a4568c7e12f306c27d1b1b72646736 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4416 Tested-by: jenkins
Tomas Vanek [Sat, 10 Feb 2018 12:07:56 +0000 (13:07 +0100)]
flash/nor: handle flash write alignment/padding in the infrastructure
Most of flash drivers have to ensure proper flash write block alignment
and padding. As there was no support for it in the flash infrastructure,
each driver does it its own way. Sometimes this part of code is not properly
tested and contains bugs.
flash_write(_unlock) joins all image sections targeted to one flash bank
using padded areas as a glue. This solves alignment problems on section
boundaries but imposes other problems.
Introduce new flash bank parameters write_start_alignment,
write_end_alignment and minimal_write_gap.
New flash drivers can just properly set these values instead of handling
alignment by its own.
Adapt infrastructure (namely flash_write_unlock(), handle_flash_fill_command()
and handle_flash_write_bank_command()) to prepare write data padded
to an alignment required by the flash bank.
Rework flash_write_unlock() to discontinue write block when the gap
between sections is bigger than minimum specified in minimal_write_gap.
minimal_write_gap is set to one sector by default.
Change-Id: I4368dd402dfaf51c193bcbf1332cffff092b239b Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4399 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Tomas Vanek [Thu, 23 Nov 2017 08:18:24 +0000 (09:18 +0100)]
target, flash: prepare infrastructure for multi-block blank check
'flash erase_check' command runs a check algorithm on a target
if possible. The algorithm is run repeatedly for each flash sector.
Unfortunately every start and stop of the algorithm impose not negligible
overhead.
In practice it means checking is faster than plain read only for
sectors of size approx 4 kByte or bigger. And checking sectors
as short as 512 bytes runs approx 4 times slower than plain read.
The patch changes API call target_blank_check_memory() and related
to take an array of sectors (or arbitrary memory blocks).
Changes in target-specific checking routines are kept minimal.
They use only the first block from the array and process it by
the unchanged algorithm.
default_flash_blank_check() routine repeats target_blank_check_memory()
until all blocks are checked, so it works with both multi-block
and single-block based checkers.
Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Structures rtos_standard_Cortex_M4F_stacking and
rtos_standard_Cortex_M4F_FPU_stacking in rtos_standard_stackings.c
where using rtos_standard_Cortex_M3_stack_align for the stack-align
function. This function calls rtos_Cortex_M_stack_align with
XPSR_OFFSET = 0x3c. This offset is correct for cortex-M3 but not for
cortex-M4F and cortex-M4F with fpu. This patch adds stack_align
functions for M4F an M4F_FPU
Change-Id: If6a90b1898fccbb85619a10f3aef5277dd88ce47 Signed-off-by: Armin van der Togt <armin@otheruse.nl>
Reviewed-on: http://openocd.zylin.com/4037 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
On SMP targets, the "target smp" command creates a list of targets
that belong to the SMP cluster. Free this list when a target gets
destroyed on shutdown. For simplicity, the complete list is free'd as
soon as the first target of the SMP cluster is destroyed instead of
individually removing targets from the list.
Tim Newsome [Tue, 6 Mar 2018 22:10:04 +0000 (14:10 -0800)]
Add gdb_report_register_access_error command
With this option enabled (it's disabled by default) errors accessing
registers are returned to gdb. Otherwise they are ignored and success is
reported to gdb. (This is the current behavior.)
We want this for RISC-V, but there's still some cleanup that needs to be
done before that can be upstreamed.
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I7e56109ea52d18b780c14a07fb35f9e6e8979da4
Reviewed-on: http://openocd.zylin.com/4452 Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
arm_adi_v5: Add ability to ignore the CSYSPWRUPACK bit
The CTRL/STAT register in the ARM DAP DP has a debug power up
ack bit and a system power up ack bit. Some devices do not set
the system power up ack bit until sometime later. To avoid having
the initial target examination fail due to this or to have a
sticky bit error report claim power failure due to this a user
can now specify that this bit should be ignored.
Stefan Arnold [Tue, 17 Oct 2017 08:50:13 +0000 (10:50 +0200)]
flash/nor/at91samd: Add "nvmuserrow" command.
Add option "nvmuserrow" to "at91samd" for changing and reading the register at 0x804000 which represents various fuses.
Change-Id: I6382cc4ac15e6b9681e2f30b0ae60397a6289c3b Signed-off-by: Stefan Arnold <sarnold@sh-sw.de>
Reviewed-on: http://openocd.zylin.com/4260 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tomas Vanek [Wed, 21 Feb 2018 21:19:58 +0000 (22:19 +0100)]
drivers/kitprog: workaround KitProg firmware bug of missing ZLP
KitProg firmware does not send a zero length packet at the end of the bulk-in
transmission of a length divisible by a bulk packet size. This is inconsistent
with the USB specification and results in jtag_libusb_bulk_read()
waits forever when a transmission of specific size is received.
Limit bulk read size to expected number of bytes for problematic tranfer sizes.
Use 1 second timeout as the last resort.
Cody P Schafer [Wed, 7 Mar 2018 16:31:35 +0000 (11:31 -0500)]
target/cortex_m: avoid dwt comparator overflow
Avoid ever overflowing the DWT_COMPARATOR array by allocating space for
16 comparators (the field is masked by 0xf).
On a stm32f767zi chip (on a nucleo-767zi board) I've been seeing crashes
with address sanitizer enabled due to its (apparent) 10 present
comparators. This appears to be due to
https://sourceforge.net/p/openocd/tickets/178/.
In non-address sanitizer builds, this would likely cause some random
memory to be written to in some cases. (see above bug for observations).
Change-Id: I2b7d599eb326236dbc93f74b350c442c9a502c4b Signed-off-by: Cody P Schafer <openocd@codyps.com>
Reviewed-on: http://openocd.zylin.com/4458 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Robert Jordens [Mon, 5 Feb 2018 11:54:29 +0000 (11:54 +0000)]
xilinx-dna.cfg: generic tools for reading Xilinx Device DNA
Most Xilinx FPGA devices contain an embedded, unique device identifier.
The identifier is nonvolatile, permanently programmed into the FPGA, and is
unchangeable providing a great serial / tracking number.
This commit adds generic support for reading the Xilinx Spartan 6 and 7
Series (Kintex, Artix, Ultrascale) Device DNA. The code is similar to
the function in fpga/xilinx-xc6s.cfg for Spartan 6 but the register
addresses are different and the logic has been simplified.
The code was not placed in xilinx-xc7.cfg. The approach of defining taps
in the same file as library code to use them is fundamentally broken on
boards that have more than one FPGA or other chips. This commit (like
the addition of support for Xilinx XADC) starts to remedy that by
splitting library code from board-specific fixed definitions.
The support code is sourced in the Kasli and KC705 board support files
as it was tested on these boards.
Robert Jordens [Mon, 29 Jan 2018 20:12:37 +0000 (21:12 +0100)]
tcl/fpga/xilinx-xadc.cfg: add support for XADC
The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
temperature, internal power supply rail voltages as well as external
voltages. The XADC is available both from fabric as well as through the
JTAG TAP.
This code implements access throught the JTAG TAP.
Robert Jordens [Mon, 15 Jan 2018 10:53:48 +0000 (10:53 +0000)]
tcl/board: add support for Kasli
Kasli is an open hardware FPGA board. It is part of the Sinara family of
devices designed to control quantum physics experiments (see Sayma_AMC
for other boards already suppported by openocd).
Kasli was developed as part of the opticlock project. It features a
Xilinx Artix 7 100T FPGA, DDR3 RAM, a clock reconstruction and
distribution network, four 6 Gb/s transceiver links (three SFP and
one SATA) as well as interfaces to up to 12 Eurocard Extension Modules
(EEMs).
Robert Jordens [Thu, 3 Aug 2017 10:25:07 +0000 (12:25 +0200)]
xilinx-xcu: add Xilinx Ultrascale tap data
The Ultrascale series is a bit more complicated to handle since with the
stacked and interconnected dies the IR gets longer. This adds support
for all currently known chips from the Ultrascale family.
- add 'dap create' command to create dap instances
- move all dap subcmmand into the dap instance commands
- keep 'dap info' for convenience
- change all armv7 and armv8 targets to take a dap
instance instead of a jtag chain position
- restructure tap/dap/target relations, jtag tap no
longer references the dap, daps are now independently
created and initialized.
- clean up swd connect
- re-initialize DAP also on JTAG errors (e.g. after reset,
power cycle)
- update documentation
- update target files
Extend the CTI abstraction to be accessible from TCL and
change the 'target' command to accept a cti 'object' instead of a
base address. This also allows accessing CTI instances that are not
related to a configured target.
If we enter debug state from EL0, some registers are not accessible.
Temporarily move to EL1H and back to gain access. Also, fix
armv8_dpm_modeswitch() to not immediately restore the previous state
on elevating the privilege level.
gdb_server: fake step if thread is not current rtos thread
gdb assumes that a rtos can make any thread active at will in response
to a 'Hg' packet. It further assumes that it needs to step-over after
setting a breakpoint on frame #0 of any non-current thread. Both
assumptions are not valid for an actual rtos. We fake the step-over to
not trigger an internal error in gdb. See
https://sourceware.org/bugzilla/show_bug.cgi?id=22925 for details.
gdb_server: fix ignored interrupt request from gdb during stepping
Normally, when a ctrl-c is received from gdb, a SIGINT is reported back
unconditionally to tell gdb that the target has stopped in response.
However when a rtos support was configured, the rtos awareness overwrote
the signal with an actual thread state, which gdb then ignored and got
stuck without the user able to interrupt.
Tomas Vanek [Fri, 16 Feb 2018 08:13:36 +0000 (09:13 +0100)]
drivers/ftdi: free allocated memory
Also uses calloc() for mpsse_ctx->write_buffer to prevent a false
positive valgrind report
"Syscall param ioctl(USBDEVFS_SUBMITURB).buffer points to uninitialised bytes(s)"
Change-Id: I91963371d15c21ea0fee4c40c1da86174db44520 Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4418 Tested-by: jenkins
Tomas Vanek [Wed, 14 Feb 2018 21:53:14 +0000 (22:53 +0100)]
openocd.c: call server_quit() for cmd line with -c shutdown
If OpenOCD command line contains -c shutdown, server_quit() is not called.
Though if -c init is also on command line, gdb_server is already initialized.
Call server_quit() on both successful and failure exit from command line.
Change-Id: I6df41c5df045b61d84a5515d1abaa5dc96bc30ac Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4409 Tested-by: jenkins
Paul Fertser [Sat, 13 Jan 2018 14:15:29 +0000 (17:15 +0300)]
target: hla: check return value of hl_dcc_read
This should fix "Assigned value is garbage or undefined" warning
reported by clang:
http://build.openocd.org/job/openocd-clang/doclinks/1/report-391318.html
Change-Id: Ib9488fadca871814328501e415f88822291e0c96 Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4332 Tested-by: jenkins
This is a second try for this patch. I removed the queues from the
previous version. I made it compatible with SRST reset and added
support for those features that could be supported in raw binary
mode.
Change-Id: I96fc06abbea9873e98b414f34afd9043fd9c2a41 Signed-off-by: Mateusz Manowiecki <segmentation@fault.pl>
Reviewed-on: http://openocd.zylin.com/3960 Tested-by: jenkins Reviewed-by: Eric Work <work.eric@gmail.com> Reviewed-by: Thomas Jarosch <thomas.jarosch@intra2net.com> Reviewed-by: Jacob Alexander <haata@kiibohd.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tomas Vanek [Sun, 4 Mar 2018 11:05:15 +0000 (12:05 +0100)]
doc: update openocd.texi after change of gdb-attach default value
While on it
- change some occurrences of gdb to GDB if it refers GDB software
(as oposed to a gdb command)
- add some xrefs
- give more meaningful example of target event definition
- remove obsoleted example of GDB hook-step
Cody P Schafer [Wed, 7 Mar 2018 16:27:02 +0000 (11:27 -0500)]
helper/types: cast to uint32_t,uint16_t to avoid UB by shifting int too far
Without this, we have some types promoted to `int` when they need to be
`unsigned int`.
Here's some ubsan output hitting this:
Unfortunately, what happens is that things get promoted to `int`, but
need to be `unsigned int`. Here's the ubsan output:
src/helper/types.h:126:65: runtime error: left shift of 255 by 24 places cannot be represented in type 'int'
#0 0x55978a612060 in le_to_h_u32 src/helper/types.h:126
#1 0x55978a61ff9e in stlink_usb_read_reg src/jtag/drivers/stlink_usb.c:1539
#2 0x55978a8cfd45 in adapter_load_core_reg_u32 src/target/hla_target.c:67
#3 0x55978a9f48e3 in armv7m_read_core_reg src/target/armv7m.c:236
#4 0x55978a8d24fc in adapter_load_context src/target/hla_target.c:372
#5 0x55978a8d261b in adapter_debug_entry src/target/hla_target.c:396
#6 0x55978a8d3123 in adapter_poll src/target/hla_target.c:457
#7 0x55978a528357 in target_poll src/target/target.c:535
#8 0x55978a539fd4 in target_wait_state src/target/target.c:2914
#9 0x55978a556e20 in jim_target_wait_state src/target/target.c:5256
#10 0x55978a5cca62 in command_unknown src/helper/command.c:1030
#11 0x55978aaed894 in JimInvokeCommand /home/cody/d/openocd-code/jimtcl/jim.c:10364
Change-Id: I24f6abfd26b6980100657397d69c84f2b80a005a Signed-off-by: Cody P Schafer <openocd@codyps.com>
Reviewed-on: http://openocd.zylin.com/4455 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com>
armv7a: cache ttbcr and ttb0/1 on debug state entry
Instead of re-reading ttbcr and ttb0/1 whenever a virt2phys translation
is done, cache the values once when entering debug state. Use the cached
values in armv7a_mmu_translate_va().
Omair Javaid [Thu, 15 Feb 2018 22:08:51 +0000 (03:08 +0500)]
Support for Arm VFP v3 registers read/write
This patch adds support in openOCD to read/write Arm vector/floating
point registers. This is compatible with Arm vfp v3 target xml in GDB.
Please refer to binutils-gdb/gdb/features/arm/arm-vfpv3.xml
Omair Javaid [Mon, 5 Mar 2018 11:25:21 +0000 (16:25 +0500)]
Support for AArch32 SIMD/Floating-point registers
This patch adds support for read/write of SIMD and floating-point register in AArch32 mode.
This patch is tested using Raspberry Pi3 halted in AArch32 mode with FP/SIMD enabled.
Software need to make sure floating-point and SIMD unit is enabled.
Omair Javaid [Sun, 21 Jan 2018 22:26:01 +0000 (03:26 +0500)]
Support AArch64 SIMD/FP registers read/write
This patch adds support in openOCD to read/write AArch64 SIMD/FP registers.
This patch depends on a previous patch which adds support to generation
of target xml by openOCD with nested architecture defined types. AArch64
SIMD/FP registers assumes various types and to support all types we
implement them as architecture defined type aarch64v which in turn
consists of various architecture defined types. This is compatible with
AArch64-FPU target xml in GDB. Please refer to
binutils-gdb/gdb/features/aarch64-fpu.xml
Omair Javaid [Sun, 21 Jan 2018 21:57:19 +0000 (02:57 +0500)]
Allow generation of nested target defined types in gdb target xml
This patch adds support to generate multiple nested architecture defined
data types in gdb target xml generated by openOCD. Architecture defined
structs, unions, vectors nested in one or more architecture defined
types can be generated now.
projects / openocd / log