roy zang [Fri, 1 Dec 2006 03:47:36 +0000 (11:47 +0800)]
Clean up the code according to codestyle:
(1) remove some C++ comments.
(2) remove trailing white space.
(3) remove trailing empty line.
(4) Indentation by table.
(5) remove {} in one line condition.
(6) add space before '(' in function call.
Remove some weird printf () output.
Add necessary comments.
Modified Makefile to support building in a separate directory.
Stefan Roese [Wed, 29 Nov 2006 14:42:37 +0000 (15:42 +0100)]
[PATCH] Add support for Prodrive P3M750 & P3M7448 (P3Mx) boards
This patch adds support for the Prodrive P3M750 (PPC750 & MV64460)
and the P3M7448 (MPC7448 & MV64460) PMC modules. Both modules are
quite similar and share the same board directory "prodrive/p3mx"
and the same config file "p3mx.h".
Stefan Roese [Wed, 29 Nov 2006 11:53:15 +0000 (12:53 +0100)]
[PATCH] common/cmd_elf.c: Enable loadaddr as parameter in bootvx command
In the bootvx command the load address was only read from the env
variable "loadaddr" and not optionally passed as paramter as described
in the help. This is fixed with this patch. The behaviour is now the
same as in the bootelf command.
Stefan Roese [Mon, 27 Nov 2006 16:34:10 +0000 (17:34 +0100)]
[PATCH] Select NAND embedded environment from board configuration
The current NAND Bootloader setup forces the environment
variables to be in line with the bootloader. This change
enables the configuration to be made in the board include
file instead so that it can be individually enabled.
Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Mon, 27 Nov 2006 16:04:06 +0000 (17:04 +0100)]
[PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel
This patch allows an arch/ppc kernel to be booted by just passing 1 or 2
arguments to bootm. It removes the getenv("disable_of") test that used
to be used for this purpose.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Jon Loeliger <jdl@freescale.com>
Stefan Roese [Mon, 13 Nov 2006 12:55:24 +0000 (13:55 +0100)]
[PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc. [Updated]
* Adds support for AMD command set Top Boot flash geometry reversal
* Adds support for reading JEDEC Manufacturer ID and Device ID
* Adds support for displaying command set, manufacturer id and
device ids (flinfo)
* Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined
* Removes outdated change history (refer to git log instead)
Signed-off-by: Tolunay Orkun <listmember@orkun.us> Signed-off-by: Stefan Roese <sr@denx.de>
Bartlomiej Sieka [Sat, 11 Nov 2006 21:43:00 +0000 (22:43 +0100)]
Change the GPIO pin multiplexing configuration for V38B. The USB GPIO pin
group is enabled for USB earlier (in cpu_init_f() instead of
usb_lowlevel_init()).
Timur Tabi [Sat, 4 Nov 2006 01:15:00 +0000 (19:15 -0600)]
mpc83xx: Update 83xx to use fsl_i2c.c
Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
Added multiple I2C bus support to fsl_i2c.c.
Dave Liu [Fri, 3 Nov 2006 00:05:50 +0000 (18:05 -0600)]
mpc83xx: Fix the incorrect dcbz operation
The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
* For the 8349E-mITX, fix some size values in pci_init_board(), enable
the clock for the 2nd USB board (Linux kernel will hang otherwise),
and fix the CONFIG_BOOTARGS macro.
Timur Tabi [Wed, 1 Nov 2006 00:44:42 +0000 (18:44 -0600)]
mpc83xx: Add support for the MPC8349E-mITX
PREREQUISITE PATCHES:
* This patch can only be applied after the following patches have been applied:
1) DNX#2006090742000024 "Add support for multiple I2C buses"
2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
CHANGELOG:
* Add support for the Freescale MPC8349E-mITX reference design platform.
The second TSEC (Vitesse 7385 switch) is not supported at this time.
Ben Warren [Thu, 7 Sep 2006 20:51:04 +0000 (16:51 -0400)]
Multi-bus I2C implementation of MPC834x
Hello,
Attached is a patch implementing multiple I2C buses on the MPC834x CPU
family and the MPC8349EMDS board in particular.
This patch requires Patch 1 (Add support for multiple I2C buses).
Testing was performed on a 533MHz board.
Signed-off-by: Ben Warren <bwarren@qstreams.com>
CHANGELOG:
Implemented driver-level code to support two I2C buses on the
MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds
are 50kHz, 100kHz and 400kHz on each bus.
Ben Warren [Thu, 7 Sep 2006 20:50:54 +0000 (16:50 -0400)]
Add support for multiple I2C buses
Hello,
Attached is a patch providing support for multiple I2C buses at the
command level. The second part of the patch includes an implementation
for the MPC834x CPU and MPC8349EMDS board.
Signed-off-by: Ben Warren <bwarren@qstreams.com>
Overview:
1. Include new 'i2c' command (based on USB implementation) using
CONFIG_I2C_CMD_TREE.
2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that
the commands to change bus number and speed are only available under the
new 'i2c' command mentioned in the first bullet.
3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus
systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form
of an array of bus-device pairs. Otherwise, it is an array of uchar.
CHANGELOG:
Added new 'i2c' master command for all I2C interaction. This is
conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for
setting I2C bus speed as well as changing the active bus if the board
has more than one (conditionally compiled with
CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses.
Updated README.
Timur Tabi [Wed, 1 Nov 2006 00:13:36 +0000 (18:13 -0600)]
mpc83xx: Add support for Errata DDR6 on MPC 834x systems
CHANGELOG:
* Errata DDR6, which affects all current MPC 834x processors, lists changes
required to maintain compatibility with various types of DDR memory. This
patch implements those changes.
Nick Spence [Sat, 30 Sep 2006 07:32:59 +0000 (00:32 -0700)]
NAND Flash verify across block boundaries
This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is
defined
and the write crosses a block boundary. The pointer to the verification
buffer (bufstart) is not being updated to reflect the starting of the
new
block so the verification of the second block fails.
CHANGELOG:
* Fix NAND FLASH page verification across block boundaries
roy zang [Thu, 2 Nov 2006 11:12:31 +0000 (19:12 +0800)]
Tsi108 on chip i2c support.
The i2c Interface provides a master-only, serial interface that can be
used for initializing Tsi108/Tsi109 registers from an EEPROM after a
device reset.
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
roy zang [Thu, 2 Nov 2006 11:11:06 +0000 (19:11 +0800)]
Tsi108 on chip pci controller support.
If there is no pci card, the tsi108/109 pci configure read will
cause a machine check exception to the processor. PCI error should
also be cleared after the read.
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
roy zang [Thu, 2 Nov 2006 11:08:55 +0000 (19:08 +0800)]
Tundra tsi108 on chip Ethernet controller support.
The following is a brief description of the Ethernet controller:
The Tsi108/9 Ethernet Controller connects Switch Fabric to two independent
Gigabit Ethernet ports,E0 and E1. It uses a single Management interface
to manage the two physical connection devices (PHYs). Each Ethernet port
has its own statistics monitor that tracks and reports key interface
statistics. Each port supports a 256-entry hash table for address
filtering. In addition, each port is bridged to the Switch Fabric
through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO.
Each Ethernet port also has a pair of internal Ethernet DMA channels to
support the transmit and receive data flows. The Ethernet DMA channels
use descriptors set up in memory, the memory map of the device, and
access via the Switch Fabric. The Ethernet Controller?s DMA arbiter
handles arbitration for the Switch Fabric. The Controller also
has a register businterface for register accesses and status monitor
control.
The PMD (Physical Media Device) interface operates in MII, GMII, or TBI
modes. The MII mode is used for connecting with 10 or 100 Mbit/s PMDs.
The GMII and TBI modes are used to connect with Gigabit PMDs. Internal
data flows to and from the Ethernet Controller through the Switch Fabric.
Each Ethernet port uses its transmit and receive DMA channels to manage
data flows through buffer descriptors that are predefined by the
system (the descriptors can exist anywhere in the system memory map).
These descriptors are data structures that point to buffers filled
with data ready to transmit over Ethernet, or they point to empty
buffers ready to receive data from Ethernet.
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
roy zang [Thu, 2 Nov 2006 11:01:33 +0000 (19:01 +0800)]
Tundra tsi108 header file.
The Tundra Semiconductor Corporation (Tundra) Tsi108 is a host bridge for
PowerPC processors that offers numerous system interconnect options for
embedded application designers. The Tsi108 can interconnect 60x or
MPX processors to PCI/X peripherals, DDR2-400 memory, Gigabit Ethernet,
and Flash. Provided the macro define for tsi108 chip.
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
roy zang [Thu, 2 Nov 2006 10:49:51 +0000 (18:49 +0800)]
General code modification for mpc7448hpc2 board support.
1. Add 7447A and 7448 processor support.
2. Add the following flags.
CFG_CONFIG_BUS_CLK : If the 74xx bus frequency can be configured dynamically
(such as by switch on board), this flag should be set.
CFG_EXCEPTION_AFTER_RELOCATE: If an exception occurs after the u-boot
relocates to RAM, this flag should be set.
CFG_SERIAL_HANG_IN_EXCEPTION: If the print out function will cause the
system hang in exception, this flag should be set.
There is a design issue for tsi108/109 pci configure read. When pci scan
the slots, if there is no pci card, the tsi108/9 will cause a machine
check exception for mpc7448 processor.
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
- Fix issues related to the use of ELDK 4 when compiling for MarelV38B:
* remove warnings when compiling ethaddr.c
* adjust linker script (fixes a crash resulting from incorrect
definition of __u_boot_cmd_start)
- Some MarelV38B code cleanup.
- Add MPC5XXX register definition MPC5XXX_WU_GPIO_DATA_I and change the
MPC5XXX_WU_GPIO_DATA macro to MPC5XXX_WU_GPIO_DATA_O (per MPC5200 User's
Manual). Replace the uses of MPC5XXX_WU_GPIO_DATA with
MPC5XXX_WU_GPIO_DATA_O for affected boards.
projects / u-boot / log