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ddr: altera: Internal mem_calibrate() cleanup part 6
2015-08-08 Dinh Nguyenarm: socfpga: enable the Altera SDRAM controller driver
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-08-08 Dinh Nguyendriver/ddr/altera: Add the sdram calibration portion
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-08-08 Dinh Nguyendriver/ddr/altera: Add DDR driver for Altera's SDRAM...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-05-07 Dinh Nguyengit-mailrc: add Dinh Nguyen as a contact for SoCFPGA
git-mailrc: add Dinh Nguyen as a contact for SoCFPGA
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: update peripheral pll for dev kit
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: add board_init_f to SPL
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Add s_init stub
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: fix uart0 pin mux configuration
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Add SDRAM check
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Use common lowlevel_init
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: printout sdram size
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: add sdram init and calibration
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: allow bootrom to enable IOs after...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Add call to timer_init
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: enable sdram, timer and uart
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: add functions to bring sdram, timer,...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KB
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2014-12-06 Dinh Nguyensocfpga: correctly increment freeze_controller_base...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2014-12-06 Dinh Nguyensocfpga: add missing struct member fifo_triple_byte
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2014-12-06 Dinh Nguyenarm: socfpga: set skew settings for ethernet phy
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2014-07-29 Dinh Nguyenboards.cfg : Add maintainers entries for SOCFPGA
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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2013-07-25 Dinh Nguyensocfpga: Move board/socfpga_cyclone5 to board/socfpga
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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2012-10-04 Dinh NguyenARM: Add Altera SOCFPGA Cyclone5
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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2012-10-03 Dinh NguyenARM: kirkwood/orion5x: Use reset_cpu definition in...
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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2012-07-11 Dinh Nguyennet/designware: Consecutive writes to the same register...
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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Cloned from git://git.denx.de/u-boot.git