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x86: minnowmax: Drop the cache line size hack
2015-07-20 Zhichun Huaarmv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.
Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
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2015-07-20 Zhichun Huaarmv8: Fix TCR macros for shareability attribute
Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
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