git.sur5r.net Git - cc65/blob - asminc/pce.inc

   1 ;
   2 ; PCE definitions. By Groepaz/Hitmem.
   3 ;
   4
   5 ; FIXME: screen dimensions my change according to selected video mode
   6 screenrows      = (224/8)
   7 charsperline    = 61
   8
   9 CH_HLINE        = 1
  10 CH_VLINE        = 2
  11
  12 ; huc6270 - Video Display Controller (VDC)
  13
  14 VDC_MAWR        = 0             ; Memory Address Write Register
  15 VDC_MARR        = 1             ; Memory Address Read Register
  16 VDC_VWR         = 2             ; VRAM Write Register (write only)
  17 VDC_VRR         = 2             ; VRAM Read Register (read only)
  18 VDC_UNK03       = 3             ; (unknown)
  19 VDC_UNK04       = 4             ; (unknown)
  20 VDC_CR          = 5             ; Control Register
  21 VDC_RCR         = 6             ; Raster Counter Register
  22 VDC_BXR         = 7             ; Background X-Scroll Register
  23 VDC_BYR         = 8             ; Background Y-Scroll Register
  24 VDC_MWR         = 9             ; Memory-access Width Register
  25 VDC_HSR         = 10            ; Horizontal Sync Register
  26 VDC_HDR         = 11            ; Horizontal Display Register
  27 VDC_VPR         = 12            ; Vertical synchronous register
  28 VDC_VDW         = 13            ; Vertical display register
  29 VDC_VCR         = 14            ; Vertical display END position register
  30 VDC_DCR         = 15            ; (DMA) Control Register
  31 VDC_SOUR        = 16            ; (DMA) Source Register
  32 VDC_DESR        = 17            ; (DMA) Destination Register
  33 VDC_LENR        = 18            ; (DMA) Length Register
  34 VDC_SATB        = 19            ; Sprite Attribute Table
  35
  36 ; VDC port
  37 ; Note: absolute addressing mode must be used when writing to this port
  38
  39 VDC_CTRL        = $0000
  40 VDC_DATA_LO     = $0002
  41 VDC_DATA_HI     = $0003
  42
  43 ; huc6260 - Video Color Encoder (vce)
  44
  45 ; The DAC has a palette of 512 colours.
  46 ; bitmap of the palette data is this: 0000000gggrrrbbb.
  47 ; You can read and write the DAC-registers.
  48
  49 VCE             = $0400         ; base
  50
  51 VCE_CTRL        = $0400         ; write$00 to reset
  52 VCE_ADDR_LO     = $0402         ; LSB of byte offset into palette
  53 VCE_ADDR_HI     = $0403         ; MSB of byte offset into palette
  54 VCE_DATA_LO     = $0404         ; LSB of 16-bit palette data
  55 VCE_DATA_HI     = $0405         ; MSB of 16-bit palette data
  56
  57 ; programmable sound generator (PSG)
  58
  59 PSG             = $0800         ; base
  60
  61 PSG_CHAN_SELECT = $0800
  62 PSG_GLOBAL_PAN  = $0801
  63 PSG_FREQ_LO     = $0802
  64 PSG_FREQ_HI     = $0803
  65 PSG_CHAN_CTRL   = $0804
  66 PSG_CHAN_PAN    = $0805
  67 PSG_CHAN_DATA   = $0806
  68 PSG_NOISE       = $0807
  69 PSG_LFO_FREQ    = $0808
  70 PSG_LFO_CTRL    = $0809
  71
  72 ; timer
  73
  74 TIMER           = $0c00         ; base
  75
  76 TIMER_COUNT     = $0c00
  77 TIMER_CTRL      = $0c01
  78
  79 JOY_CTRL        = $1000
  80
  81 IRQ_MASK        = $1402
  82 IRQ_STATUS      = $1403
  83
  84 CDR_MEM_DISABLE = $1803
  85 CDR_MEM_ENABLE  = $1807
  86
  87 ; Write VDC register
  88 .macro VREG arg1,arg2
  89         st0     #arg1
  90         st1     #<(arg2)
  91         st2     #>(arg2)
  92 .endmacro