1 /* ----------------------------------------------------------------------------
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2 * SAM Software Package License
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3 * ----------------------------------------------------------------------------
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4 * Copyright (c) 2015, Atmel Corporation
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6 * All rights reserved.
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8 * Redistribution and use in source and binary forms, with or without
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9 * modification, are permitted provided that the following conditions are met:
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11 * - Redistributions of source code must retain the above copyright notice,
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12 * this list of conditions and the disclaimer below.
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14 * Atmel's name may not be used to endorse or promote products derived from
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15 * this software without specific prior written permission.
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17 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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20 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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23 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * ----------------------------------------------------------------------------
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33 * Interface for Level 2 cache (L2CC) controller.
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37 /** \addtogroup l2cc_module L2 Cache Operations
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38 * \ingroup cache_module
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40 * - Enable or disable L2CC with L2CC_Enable() or L2CC_Disable().
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41 * - Check if L2CC is enabled with L2CC_IsEnabled().
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42 * - Enable or disable L2CC interrupt with L2CC_EnableIT() or L2CC_DisableIT().
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43 * - Enable data or instruction prefetch with L2CC_DataPrefetchEnable() or L2CC_InstPrefetchEnable().
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53 /*----------------------------------------------------------------------------
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55 *----------------------------------------------------------------------------*/
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60 /*----------------------------------------------------------------------------
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62 *----------------------------------------------------------------------------*/
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68 #define OFFSET_BIT 5
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72 #define L2CC_RESET_EVCOUNTER0 0
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73 #define L2CC_RESET_EVCOUNTER1 1
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74 #define L2CC_RESET_BOTH_COUNTER 3
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76 #define FWA_DEFAULT 0u
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77 #define FWA_NO_ALLOCATE 1u
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78 #define FWA_FORCE_ALLOCATE 2u
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79 #define FWA_INTERNALLY_MAPPED 3u
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81 /*----------------------------------------------------------------------------
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83 *----------------------------------------------------------------------------*/
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97 struct _ram_latency_control {
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98 struct _latency tag;
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99 struct _latency data;
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102 /** L2CC structure */
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103 struct _l2cc_control {
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104 /** High Priority for SO and Dev Reads Enable */
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105 uint32_t high_prior_so: 1,
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106 /** Store Buffer Device Limitation Enable */
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107 store_buff_dev_limit: 1,
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108 /** Shared Attribute Invalidate Enable */
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109 shared_attr_invalidate: 1,
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110 /** Event Monitor Bus Enable */
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112 /** Parity Enable */
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114 /** Shared Attribute Override Enable */
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115 shared_attr_override: 1,
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116 /** Force Write Allocate */
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117 force_write_alloc: 2,
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118 /** Cache Replacement Policy */
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119 cache_replacement: 1,
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120 /** Non-Secure Lockdown Enable*/
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121 non_sec_lockdown: 1,
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122 /** Non-Secure Interrupt Access Control */
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123 it_acces_non_sec: 1,
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124 /** Data Prefetch Enable*/
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126 /** Instruction Prefetch Enable */
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127 instruct_prefetch: 1,
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128 /** Prefetch Offset */
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130 /** Not Same ID on Exclusive Sequence Enable */
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131 exclusive_seq_same_id: 1,
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132 /** INCR Double Linefill Enable */
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133 incr_double_linefill: 1,
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134 /** Prefetch Drop Enable*/
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136 /** Double Linefill on WRAP Read Disable */
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138 /** Double linefill Enable */
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139 double_linefill: 1,
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140 /** Standby Mode Enable */
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142 /** Dynamic Clock Gating Enable */
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143 dyn_clock_gating: 1,
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144 /** Disable Cache Linefill*/
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145 no_cache_linefill: 1,
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146 /** Disable Write-back, Force Write-through */
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149 /*----------------------------------------------------------------------------
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150 * Exported functions
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151 *----------------------------------------------------------------------------*/
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154 * \brief Check if Level 2 cache is enable.
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156 extern uint32_t l2cc_is_enabled(void);
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159 * \brief Enable Level 2 cache.
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161 extern void l2cc_enable(void);
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164 * \brief Disable Level 2 cache.
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166 extern void l2cc_disable(void);
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169 * \brief Configures Level 2 cache as exclusive cache.
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170 * \param Enable Enable/disable exclusive cache.
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172 extern void l2cc_exclusive_cache(uint8_t enable);
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175 * \brief Configures Level 2 cache RAM Latency (Tag and Data).
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176 * \param latencies Structure containing RAM Tag and Data latencies
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178 extern void l2cc_config_lat_ram(struct _ram_latency_control * latencies);
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181 * \brief Configures Level 2 cache.
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182 * \param cfg Configuration values to put in Auxiliary, prefetch,
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183 * debug and powercontrol registers.
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185 extern void l2cc_set_config(const struct _l2cc_control* cfg);
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188 * \brief Enables Data prefetch on L2
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190 extern void l2cc_data_prefetch_enable(void);
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193 * \brief Enables instruction prefetch on L2
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195 extern void l2cc_inst_prefetch_enable(void);
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198 * \brief Enables instruction prefetch on L2
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199 * \param event_counter Counter of the events.
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201 extern void l2cc_enable_reset_counter(uint8_t event_counter);
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204 * \brief Configures Event of Level 2 cache.
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205 * \param event_counter Eventcounter 1 or 0
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206 * \param source Event Genration source
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207 * \param it Event Counter Interrupt Generation condition
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209 extern void l2cc_event_config(uint8_t event_counter, uint8_t source,
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213 * \brief Reads Event Counter value.
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214 * \param event_counter choose Eventcounter 1 or 0
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216 extern uint32_t l2cc_event_counter_value(uint8_t event_counter);
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219 * \brief Enable interrupts
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220 * \param sources Interrupt source
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222 extern void l2cc_enable_it(uint16_t sources);
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225 * \brief Disable interrupts
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226 * \param sources Interrupt source
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228 extern void l2cc_disable_it(uint16_t sources);
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231 * \brief Enabled interrupt's raw status
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232 * \param sources Interrupt source
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234 extern uint16_t l2cc_it_status_raw(uint16_t sources);
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237 * \brief Status of masked interrupts
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238 * \param sources Interrupt source
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240 extern uint16_t l2cc_it_status_mask(uint16_t sources);
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243 * \brief Clear interrupts
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244 * \param sources Interrupt source
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246 extern void l2cc_it_clear(uint16_t sources);
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249 * \brief Poll SPNIDEN signal
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251 extern uint8_t l2cc_poll_spniden(void);
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254 * \brief Synchronizes the L2 cache
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256 extern void l2cc_cache_sync(void);
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259 * \brief Invalidate cache by way
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260 * \param way way number
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262 extern void l2cc_invalidate_way(uint8_t way);
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265 * \brief Clean cache by way
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266 * \param way way number
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268 extern void l2cc_clean_way(uint8_t way);
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271 * \brief Invalidate cache by Physical addersse
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272 * \param phys_addr Physical addresse
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274 extern void l2cc_invalidate_pal(uint32_t phys_addr);
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277 * \brief Clean cache by Physical addersse
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278 * \param phys_addr Physical addresse
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280 extern void l2cc_clean_pal(uint32_t phys_addr);
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283 * \brief Clean index cache by Physical addersse
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284 * \param phys_addr Physical addresse
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286 extern void l2cc_clean_ix(uint32_t phys_addr);
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289 * \brief Clean cache by Index
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290 * \param phys_addr Physical addresse
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291 * \param way way number
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293 extern void l2cc_clean_index(uint32_t phys_addr, uint8_t way);
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296 * \brief Clean Invalidate cache by index
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297 * \param phys_addr Physical address
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298 * \param way way number
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300 extern void l2cc_clean_invalidate_index(uint32_t phys_addr, uint8_t way);
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303 * \brief cache Data lockdown
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304 * \param way way number
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306 extern void l2cc_data_lockdown(uint8_t way);
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309 * \brief cache instruction lockdown
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310 * \param way way number
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312 extern void l2cc_instruction_lockdown(uint8_t way);
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315 * \brief L2 DCache maintenance (clean/invalidate/flush)
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317 * \param maintenance Maintenance operation to apply: \sa #_maint_op
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319 extern void l2cc_cache_maintenance(enum _maint_op maintenance);
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322 * \brief Invalidate cache lines corresponding to a memory region
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324 * \param start Beginning of the memory region
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325 * \param end End of the memory region
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327 extern void l2cc_invalidate_region(uint32_t start, uint32_t end);
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330 * \brief Clean cache lines corresponding to a memory region
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332 * \param start Beginning of the memory region
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333 * \param end End of the memory region
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335 extern void l2cc_clean_region(uint32_t start, uint32_t end);
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338 * \brief Enable level two cache controller (L2CC)
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340 * \param cfg configuration to apply: \sa #_l2cc_control
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342 extern void l2cc_configure(const struct _l2cc_control* cfg);
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347 #endif /* #ifndef _L2CC_ */
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