1 /* ---------------------------------------------------------------------------- */
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2 /* Atmel Microcontroller Software Support */
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3 /* SAM Software Package License */
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4 /* ---------------------------------------------------------------------------- */
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5 /* Copyright (c) 2015, Atmel Corporation */
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7 /* All rights reserved. */
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9 /* Redistribution and use in source and binary forms, with or without */
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10 /* modification, are permitted provided that the following condition is met: */
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12 /* - Redistributions of source code must retain the above copyright notice, */
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13 /* this list of conditions and the disclaimer below. */
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15 /* Atmel's name may not be used to endorse or promote products derived from */
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16 /* this software without specific prior written permission. */
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18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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28 /* ---------------------------------------------------------------------------- */
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30 #ifndef _SAMA5D2_AES_COMPONENT_
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31 #define _SAMA5D2_AES_COMPONENT_
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33 /* ============================================================================= */
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34 /** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
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35 /* ============================================================================= */
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36 /** \addtogroup SAMA5D2_AES Advanced Encryption Standard */
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39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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40 /** \brief Aes hardware registers */
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42 __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */
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43 __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */
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44 __I uint32_t Reserved1[2];
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45 __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */
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46 __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */
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47 __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */
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48 __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */
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49 __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */
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50 __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */
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51 __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */
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52 __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */
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53 __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */
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54 __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */
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55 __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */
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56 __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */
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57 __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */
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58 __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */
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59 __I uint32_t Reserved2[1];
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60 __IO uint32_t AES_EMR; /**< \brief (Aes Offset: 0xB0) Extended Mode Register */
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61 __IO uint32_t AES_BCNT; /**< \brief (Aes Offset: 0xB4) Byte Counter Register */
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62 __I uint32_t Reserved3[2];
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63 __IO uint32_t AES_TWR[4]; /**< \brief (Aes Offset: 0xC0) Tweak Word Register */
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64 __O uint32_t AES_ALPHAR[4]; /**< \brief (Aes Offset: 0xD0) Alpha Word Register */
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65 __I uint32_t Reserved4[7];
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66 __I uint32_t AES_VERSION; /**< \brief (Aes Offset: 0xFC) Version Register */
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68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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69 /* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */
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70 #define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */
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71 #define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */
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72 #define AES_CR_LOADSEED (0x1u << 16) /**< \brief (AES_CR) Random Number Generator Seed Loading */
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73 /* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */
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74 #define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */
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75 #define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */
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76 #define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */
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77 #define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */
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78 #define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */
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79 #define AES_MR_PROCDLY_Pos 4
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80 #define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */
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81 #define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))
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82 #define AES_MR_SMOD_Pos 8
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83 #define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */
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84 #define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)))
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85 #define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */
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86 #define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */
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87 #define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */
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88 #define AES_MR_KEYSIZE_Pos 10
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89 #define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */
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90 #define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)))
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91 #define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */
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92 #define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */
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93 #define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */
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94 #define AES_MR_OPMOD_Pos 12
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95 #define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */
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96 #define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)))
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97 #define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */
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98 #define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */
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99 #define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */
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100 #define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */
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101 #define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */
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102 #define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */
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103 #define AES_MR_OPMOD_XTS (0x6u << 12) /**< \brief (AES_MR) XTS: XEX-based tweaked-codebook mode */
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104 #define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */
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105 #define AES_MR_CFBS_Pos 16
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106 #define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */
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107 #define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)))
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108 #define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */
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109 #define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */
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110 #define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */
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111 #define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */
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112 #define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */
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113 #define AES_MR_CKEY_Pos 20
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114 #define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Countermeasure Key */
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115 #define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))
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116 #define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */
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117 #define AES_MR_CMTYP1 (0x1u << 24) /**< \brief (AES_MR) Countermeasure Type 1 */
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118 #define AES_MR_CMTYP1_NOPROT_EXTKEY (0x0u << 24) /**< \brief (AES_MR) Countermeasure type 1 is disabled. */
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119 #define AES_MR_CMTYP1_PROT_EXTKEY (0x1u << 24) /**< \brief (AES_MR) Countermeasure type 1 is enabled. */
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120 #define AES_MR_CMTYP2 (0x1u << 25) /**< \brief (AES_MR) Countermeasure Type 2 */
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121 #define AES_MR_CMTYP2_NO_PAUSE (0x0u << 25) /**< \brief (AES_MR) Countermeasure type 2 is disabled. */
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122 #define AES_MR_CMTYP2_PAUSE (0x1u << 25) /**< \brief (AES_MR) Countermeasure type 2 is enabled. */
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123 #define AES_MR_CMTYP3 (0x1u << 26) /**< \brief (AES_MR) Countermeasure Type 3 */
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124 #define AES_MR_CMTYP3_NO_DUMMY (0x0u << 26) /**< \brief (AES_MR) Countermeasure type 3 is disabled. */
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125 #define AES_MR_CMTYP3_DUMMY (0x1u << 26) /**< \brief (AES_MR) Countermeasure type 3 is enabled. */
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126 #define AES_MR_CMTYP4 (0x1u << 27) /**< \brief (AES_MR) Countermeasure Type 4 */
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127 #define AES_MR_CMTYP4_NO_RESTART (0x0u << 27) /**< \brief (AES_MR) Countermeasure type 4 is disabled. */
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128 #define AES_MR_CMTYP4_RESTART (0x1u << 27) /**< \brief (AES_MR) Countermeasure type 4 is enabled. */
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129 #define AES_MR_CMTYP5 (0x1u << 28) /**< \brief (AES_MR) Countermeasure Type 5 */
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130 #define AES_MR_CMTYP5_NO_ADDACCESS (0x0u << 28) /**< \brief (AES_MR) Countermeasure type 5 is disabled. */
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131 #define AES_MR_CMTYP5_ADDACCESS (0x1u << 28) /**< \brief (AES_MR) Countermeasure type 5 is enabled. */
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132 #define AES_MR_CMTYP6 (0x1u << 29) /**< \brief (AES_MR) Countermeasure Type 6 */
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133 #define AES_MR_CMTYP6_NO_IDLECURRENT (0x0u << 29) /**< \brief (AES_MR) Countermeasure type 6 is disabled. */
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134 #define AES_MR_CMTYP6_IDLECURRENT (0x1u << 29) /**< \brief (AES_MR) Countermeasure type 6 is enabled. */
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135 /* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
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136 #define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */
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137 #define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */
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138 #define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */
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139 #define AES_IER_EOPAD (0x1u << 17) /**< \brief (AES_IER) End of Padding Interrupt Enable */
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140 #define AES_IER_PLENERR (0x1u << 18) /**< \brief (AES_IER) Padding Length Error Interrupt Enable */
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141 /* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
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142 #define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */
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143 #define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */
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144 #define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */
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145 #define AES_IDR_EOPAD (0x1u << 17) /**< \brief (AES_IDR) End of Padding Interrupt Disable */
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146 #define AES_IDR_PLENERR (0x1u << 18) /**< \brief (AES_IDR) Padding Length Error Interrupt Disable */
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147 /* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
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148 #define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */
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149 #define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */
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150 #define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */
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151 #define AES_IMR_EOPAD (0x1u << 17) /**< \brief (AES_IMR) End of Padding Interrupt Mask */
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152 #define AES_IMR_PLENERR (0x1u << 18) /**< \brief (AES_IMR) Padding Length Error Interrupt Mask */
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153 /* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */
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154 #define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */
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155 #define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */
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156 #define AES_ISR_URAT_Pos 12
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157 #define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */
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158 #define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */
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159 #define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */
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160 #define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */
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161 #define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */
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162 #define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */
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163 #define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */
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164 #define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */
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165 #define AES_ISR_EOPAD (0x1u << 17) /**< \brief (AES_ISR) End of Padding */
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166 #define AES_ISR_PLENERR (0x1u << 18) /**< \brief (AES_ISR) Padding Length Error */
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167 /* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */
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168 #define AES_KEYWR_KEYW_Pos 0
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169 #define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */
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170 #define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))
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171 /* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */
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172 #define AES_IDATAR_IDATA_Pos 0
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173 #define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */
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174 #define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))
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175 /* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */
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176 #define AES_ODATAR_ODATA_Pos 0
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177 #define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */
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178 /* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */
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179 #define AES_IVR_IV_Pos 0
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180 #define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */
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181 #define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))
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182 /* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */
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183 #define AES_AADLENR_AADLEN_Pos 0
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184 #define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */
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185 #define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))
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186 /* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */
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187 #define AES_CLENR_CLEN_Pos 0
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188 #define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */
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189 #define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))
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190 /* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */
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191 #define AES_GHASHR_GHASH_Pos 0
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192 #define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */
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193 #define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))
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194 /* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */
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195 #define AES_TAGR_TAG_Pos 0
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196 #define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */
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197 /* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */
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198 #define AES_CTRR_CTR_Pos 0
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199 #define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */
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200 /* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */
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201 #define AES_GCMHR_H_Pos 0
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202 #define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */
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203 #define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))
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204 /* -------- AES_EMR : (AES Offset: 0xB0) Extended Mode Register -------- */
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205 #define AES_EMR_APEN (0x1u << 0) /**< \brief (AES_EMR) Auto Padding Enable */
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206 #define AES_EMR_APM (0x1u << 1) /**< \brief (AES_EMR) Auto Padding Mode */
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207 #define AES_EMR_PLIPEN (0x1u << 4) /**< \brief (AES_EMR) Protocol Layer Improved Performance Enable */
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208 #define AES_EMR_PLIPD (0x1u << 5) /**< \brief (AES_EMR) Protocol Layer Improved Performance Decipher */
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209 #define AES_EMR_PADLEN_Pos 8
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210 #define AES_EMR_PADLEN_Msk (0xffu << AES_EMR_PADLEN_Pos) /**< \brief (AES_EMR) Auto Padding Length */
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211 #define AES_EMR_PADLEN(value) ((AES_EMR_PADLEN_Msk & ((value) << AES_EMR_PADLEN_Pos)))
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212 #define AES_EMR_NHEAD_Pos 16
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213 #define AES_EMR_NHEAD_Msk (0xffu << AES_EMR_NHEAD_Pos) /**< \brief (AES_EMR) IPSEC Next Header */
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214 #define AES_EMR_NHEAD(value) ((AES_EMR_NHEAD_Msk & ((value) << AES_EMR_NHEAD_Pos)))
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215 /* -------- AES_BCNT : (AES Offset: 0xB4) Byte Counter Register -------- */
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216 #define AES_BCNT_BCNT_Pos 0
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217 #define AES_BCNT_BCNT_Msk (0xffffffffu << AES_BCNT_BCNT_Pos) /**< \brief (AES_BCNT) Auto Padding Byte Counter */
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218 #define AES_BCNT_BCNT(value) ((AES_BCNT_BCNT_Msk & ((value) << AES_BCNT_BCNT_Pos)))
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219 /* -------- AES_TWR[4] : (AES Offset: 0xC0) Tweak Word Register -------- */
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220 #define AES_TWR_TWEAK_Pos 0
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221 #define AES_TWR_TWEAK_Msk (0xffffffffu << AES_TWR_TWEAK_Pos) /**< \brief (AES_TWR[4]) Tweak Word x */
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222 #define AES_TWR_TWEAK(value) ((AES_TWR_TWEAK_Msk & ((value) << AES_TWR_TWEAK_Pos)))
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223 /* -------- AES_ALPHAR[4] : (AES Offset: 0xD0) Alpha Word Register -------- */
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224 #define AES_ALPHAR_ALPHA_Pos 0
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225 #define AES_ALPHAR_ALPHA_Msk (0xffffffffu << AES_ALPHAR_ALPHA_Pos) /**< \brief (AES_ALPHAR[4]) Alpha Word x */
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226 #define AES_ALPHAR_ALPHA(value) ((AES_ALPHAR_ALPHA_Msk & ((value) << AES_ALPHAR_ALPHA_Pos)))
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227 /* -------- AES_VERSION : (AES Offset: 0xFC) Version Register -------- */
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228 #define AES_VERSION_VERSION_Pos 0
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229 #define AES_VERSION_VERSION_Msk (0xfffu << AES_VERSION_VERSION_Pos) /**< \brief (AES_VERSION) Version of the Hardware Module */
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230 #define AES_VERSION_MFN_Pos 16
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231 #define AES_VERSION_MFN_Msk (0x7u << AES_VERSION_MFN_Pos) /**< \brief (AES_VERSION) Metal Fix Number */
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236 #endif /* _SAMA5D2_AES_COMPONENT_ */
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