1 /* ---------------------------------------------------------------------------- */
\r
2 /* Atmel Microcontroller Software Support */
\r
3 /* SAM Software Package License */
\r
4 /* ---------------------------------------------------------------------------- */
\r
5 /* Copyright (c) 2015, Atmel Corporation */
\r
7 /* All rights reserved. */
\r
9 /* Redistribution and use in source and binary forms, with or without */
\r
10 /* modification, are permitted provided that the following condition is met: */
\r
12 /* - Redistributions of source code must retain the above copyright notice, */
\r
13 /* this list of conditions and the disclaimer below. */
\r
15 /* Atmel's name may not be used to endorse or promote products derived from */
\r
16 /* this software without specific prior written permission. */
\r
18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
\r
19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
\r
20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
\r
21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
\r
22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
\r
23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
\r
24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
\r
25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
\r
26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
\r
27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
\r
28 /* ---------------------------------------------------------------------------- */
\r
30 #ifndef _SAMA5D2_AIC_COMPONENT_
\r
31 #define _SAMA5D2_AIC_COMPONENT_
\r
33 /* ============================================================================= */
\r
34 /** SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
\r
35 /* ============================================================================= */
\r
36 /** \addtogroup SAMA5D2_AIC Advanced Interrupt Controller */
\r
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
\r
40 /** \brief Aic hardware registers */
\r
42 __IO uint32_t AIC_SSR; /**< \brief (Aic Offset: 0x00) Source Select Register */
\r
43 __IO uint32_t AIC_SMR; /**< \brief (Aic Offset: 0x04) Source Mode Register */
\r
44 __IO uint32_t AIC_SVR; /**< \brief (Aic Offset: 0x08) Source Vector Register */
\r
45 __I uint32_t Reserved1[1];
\r
46 __I uint32_t AIC_IVR; /**< \brief (Aic Offset: 0x10) Interrupt Vector Register */
\r
47 __I uint32_t AIC_FVR; /**< \brief (Aic Offset: 0x14) FIQ Vector Register */
\r
48 __I uint32_t AIC_ISR; /**< \brief (Aic Offset: 0x18) Interrupt Status Register */
\r
49 __I uint32_t Reserved2[1];
\r
50 __I uint32_t AIC_IPR0; /**< \brief (Aic Offset: 0x20) Interrupt Pending Register 0 */
\r
51 __I uint32_t AIC_IPR1; /**< \brief (Aic Offset: 0x24) Interrupt Pending Register 1 */
\r
52 __I uint32_t AIC_IPR2; /**< \brief (Aic Offset: 0x28) Interrupt Pending Register 2 */
\r
53 __I uint32_t AIC_IPR3; /**< \brief (Aic Offset: 0x2C) Interrupt Pending Register 3 */
\r
54 __I uint32_t AIC_IMR; /**< \brief (Aic Offset: 0x30) Interrupt Mask Register */
\r
55 __I uint32_t AIC_CISR; /**< \brief (Aic Offset: 0x34) Core Interrupt Status Register */
\r
56 __O uint32_t AIC_EOICR; /**< \brief (Aic Offset: 0x38) End of Interrupt Command Register */
\r
57 __IO uint32_t AIC_SPU; /**< \brief (Aic Offset: 0x3C) Spurious Interrupt Vector Register */
\r
58 __O uint32_t AIC_IECR; /**< \brief (Aic Offset: 0x40) Interrupt Enable Command Register */
\r
59 __O uint32_t AIC_IDCR; /**< \brief (Aic Offset: 0x44) Interrupt Disable Command Register */
\r
60 __O uint32_t AIC_ICCR; /**< \brief (Aic Offset: 0x48) Interrupt Clear Command Register */
\r
61 __O uint32_t AIC_ISCR; /**< \brief (Aic Offset: 0x4C) Interrupt Set Command Register */
\r
62 __I uint32_t Reserved3[7];
\r
63 __IO uint32_t AIC_DCR; /**< \brief (Aic Offset: 0x6C) Debug Control Register */
\r
64 __I uint32_t Reserved4[29];
\r
65 __IO uint32_t AIC_WPMR; /**< \brief (Aic Offset: 0xE4) Write Protection Mode Register */
\r
66 __I uint32_t AIC_WPSR; /**< \brief (Aic Offset: 0xE8) Write Protection Status Register */
\r
67 __I uint32_t Reserved5[4];
\r
68 __I uint32_t AIC_VERSION; /**< \brief (Aic Offset: 0XFC) AIC Version Register */
\r
70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
\r
71 /* -------- AIC_SSR : (AIC Offset: 0x00) Source Select Register -------- */
\r
72 #define AIC_SSR_INTSEL_Pos 0
\r
73 #define AIC_SSR_INTSEL_Msk (0x7fu << AIC_SSR_INTSEL_Pos) /**< \brief (AIC_SSR) Interrupt Line Selection */
\r
74 #define AIC_SSR_INTSEL(value) ((AIC_SSR_INTSEL_Msk & ((value) << AIC_SSR_INTSEL_Pos)))
\r
75 /* -------- AIC_SMR : (AIC Offset: 0x04) Source Mode Register -------- */
\r
76 #define AIC_SMR_PRIOR_Pos 0
\r
77 #define AIC_SMR_PRIOR_Msk (0x7u << AIC_SMR_PRIOR_Pos) /**< \brief (AIC_SMR) Priority Level */
\r
78 #define AIC_SMR_PRIOR(value) ((AIC_SMR_PRIOR_Msk & ((value) << AIC_SMR_PRIOR_Pos)))
\r
79 #define AIC_SMR_SRCTYPE_Pos 5
\r
80 #define AIC_SMR_SRCTYPE_Msk (0x3u << AIC_SMR_SRCTYPE_Pos) /**< \brief (AIC_SMR) Interrupt Source Type */
\r
81 #define AIC_SMR_SRCTYPE(value) ((AIC_SMR_SRCTYPE_Msk & ((value) << AIC_SMR_SRCTYPE_Pos)))
\r
82 #define AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceLow level Sensitive for external source */
\r
83 #define AIC_SMR_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourceNegative edge triggered for external source */
\r
84 #define AIC_SMR_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) /**< \brief (AIC_SMR) High level Sensitive for internal sourceHigh level Sensitive for external source */
\r
85 #define AIC_SMR_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) /**< \brief (AIC_SMR) Positive edge triggered for internal sourcePositive edge triggered for external source */
\r
86 /* -------- AIC_SVR : (AIC Offset: 0x08) Source Vector Register -------- */
\r
87 #define AIC_SVR_VECTOR_Pos 0
\r
88 #define AIC_SVR_VECTOR_Msk (0xffffffffu << AIC_SVR_VECTOR_Pos) /**< \brief (AIC_SVR) Source Vector */
\r
89 #define AIC_SVR_VECTOR(value) ((AIC_SVR_VECTOR_Msk & ((value) << AIC_SVR_VECTOR_Pos)))
\r
90 /* -------- AIC_IVR : (AIC Offset: 0x10) Interrupt Vector Register -------- */
\r
91 #define AIC_IVR_IRQV_Pos 0
\r
92 #define AIC_IVR_IRQV_Msk (0xffffffffu << AIC_IVR_IRQV_Pos) /**< \brief (AIC_IVR) Interrupt Vector Register */
\r
93 /* -------- AIC_FVR : (AIC Offset: 0x14) FIQ Vector Register -------- */
\r
94 #define AIC_FVR_FIQV_Pos 0
\r
95 #define AIC_FVR_FIQV_Msk (0xffffffffu << AIC_FVR_FIQV_Pos) /**< \brief (AIC_FVR) FIQ Vector Register */
\r
96 /* -------- AIC_ISR : (AIC Offset: 0x18) Interrupt Status Register -------- */
\r
97 #define AIC_ISR_IRQID_Pos 0
\r
98 #define AIC_ISR_IRQID_Msk (0x7fu << AIC_ISR_IRQID_Pos) /**< \brief (AIC_ISR) Current Interrupt Identifier */
\r
99 /* -------- AIC_IPR0 : (AIC Offset: 0x20) Interrupt Pending Register 0 -------- */
\r
100 #define AIC_IPR0_FIQ (0x1u << 0) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
101 #define AIC_IPR0_SYS (0x1u << 1) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
102 #define AIC_IPR0_PID2 (0x1u << 2) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
103 #define AIC_IPR0_PID3 (0x1u << 3) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
104 #define AIC_IPR0_PID4 (0x1u << 4) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
105 #define AIC_IPR0_PID5 (0x1u << 5) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
106 #define AIC_IPR0_PID6 (0x1u << 6) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
107 #define AIC_IPR0_PID7 (0x1u << 7) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
108 #define AIC_IPR0_PID8 (0x1u << 8) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
109 #define AIC_IPR0_PID9 (0x1u << 9) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
110 #define AIC_IPR0_PID10 (0x1u << 10) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
111 #define AIC_IPR0_PID11 (0x1u << 11) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
112 #define AIC_IPR0_PID12 (0x1u << 12) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
113 #define AIC_IPR0_PID13 (0x1u << 13) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
114 #define AIC_IPR0_PID14 (0x1u << 14) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
115 #define AIC_IPR0_PID15 (0x1u << 15) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
116 #define AIC_IPR0_PID16 (0x1u << 16) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
117 #define AIC_IPR0_PID17 (0x1u << 17) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
118 #define AIC_IPR0_PID18 (0x1u << 18) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
119 #define AIC_IPR0_PID19 (0x1u << 19) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
120 #define AIC_IPR0_PID20 (0x1u << 20) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
121 #define AIC_IPR0_PID21 (0x1u << 21) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
122 #define AIC_IPR0_PID22 (0x1u << 22) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
123 #define AIC_IPR0_PID23 (0x1u << 23) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
124 #define AIC_IPR0_PID24 (0x1u << 24) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
125 #define AIC_IPR0_PID25 (0x1u << 25) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
126 #define AIC_IPR0_PID26 (0x1u << 26) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
127 #define AIC_IPR0_PID27 (0x1u << 27) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
128 #define AIC_IPR0_PID28 (0x1u << 28) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
129 #define AIC_IPR0_PID29 (0x1u << 29) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
130 #define AIC_IPR0_PID30 (0x1u << 30) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
131 #define AIC_IPR0_PID31 (0x1u << 31) /**< \brief (AIC_IPR0) Interrupt Pending */
\r
132 /* -------- AIC_IPR1 : (AIC Offset: 0x24) Interrupt Pending Register 1 -------- */
\r
133 #define AIC_IPR1_PID32 (0x1u << 0) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
134 #define AIC_IPR1_PID33 (0x1u << 1) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
135 #define AIC_IPR1_PID34 (0x1u << 2) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
136 #define AIC_IPR1_PID35 (0x1u << 3) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
137 #define AIC_IPR1_PID36 (0x1u << 4) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
138 #define AIC_IPR1_PID37 (0x1u << 5) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
139 #define AIC_IPR1_PID38 (0x1u << 6) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
140 #define AIC_IPR1_PID39 (0x1u << 7) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
141 #define AIC_IPR1_PID40 (0x1u << 8) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
142 #define AIC_IPR1_PID41 (0x1u << 9) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
143 #define AIC_IPR1_PID42 (0x1u << 10) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
144 #define AIC_IPR1_PID43 (0x1u << 11) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
145 #define AIC_IPR1_PID44 (0x1u << 12) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
146 #define AIC_IPR1_PID45 (0x1u << 13) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
147 #define AIC_IPR1_PID46 (0x1u << 14) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
148 #define AIC_IPR1_PID47 (0x1u << 15) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
149 #define AIC_IPR1_PID48 (0x1u << 16) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
150 #define AIC_IPR1_PID49 (0x1u << 17) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
151 #define AIC_IPR1_PID50 (0x1u << 18) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
152 #define AIC_IPR1_PID51 (0x1u << 19) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
153 #define AIC_IPR1_PID52 (0x1u << 20) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
154 #define AIC_IPR1_PID53 (0x1u << 21) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
155 #define AIC_IPR1_PID54 (0x1u << 22) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
156 #define AIC_IPR1_PID55 (0x1u << 23) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
157 #define AIC_IPR1_PID56 (0x1u << 24) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
158 #define AIC_IPR1_PID57 (0x1u << 25) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
159 #define AIC_IPR1_PID58 (0x1u << 26) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
160 #define AIC_IPR1_PID59 (0x1u << 27) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
161 #define AIC_IPR1_PID60 (0x1u << 28) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
162 #define AIC_IPR1_PID61 (0x1u << 29) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
163 #define AIC_IPR1_PID62 (0x1u << 30) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
164 #define AIC_IPR1_PID63 (0x1u << 31) /**< \brief (AIC_IPR1) Interrupt Pending */
\r
165 /* -------- AIC_IPR2 : (AIC Offset: 0x28) Interrupt Pending Register 2 -------- */
\r
166 #define AIC_IPR2_PID64 (0x1u << 0) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
167 #define AIC_IPR2_PID65 (0x1u << 1) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
168 #define AIC_IPR2_PID66 (0x1u << 2) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
169 #define AIC_IPR2_PID67 (0x1u << 3) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
170 #define AIC_IPR2_PID68 (0x1u << 4) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
171 #define AIC_IPR2_PID69 (0x1u << 5) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
172 #define AIC_IPR2_PID70 (0x1u << 6) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
173 #define AIC_IPR2_PID71 (0x1u << 7) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
174 #define AIC_IPR2_PID72 (0x1u << 8) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
175 #define AIC_IPR2_PID73 (0x1u << 9) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
176 #define AIC_IPR2_PID74 (0x1u << 10) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
177 #define AIC_IPR2_PID75 (0x1u << 11) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
178 #define AIC_IPR2_PID76 (0x1u << 12) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
179 #define AIC_IPR2_PID77 (0x1u << 13) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
180 #define AIC_IPR2_PID78 (0x1u << 14) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
181 #define AIC_IPR2_PID79 (0x1u << 15) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
182 #define AIC_IPR2_PID80 (0x1u << 16) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
183 #define AIC_IPR2_PID81 (0x1u << 17) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
184 #define AIC_IPR2_PID82 (0x1u << 18) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
185 #define AIC_IPR2_PID83 (0x1u << 19) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
186 #define AIC_IPR2_PID84 (0x1u << 20) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
187 #define AIC_IPR2_PID85 (0x1u << 21) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
188 #define AIC_IPR2_PID86 (0x1u << 22) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
189 #define AIC_IPR2_PID87 (0x1u << 23) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
190 #define AIC_IPR2_PID88 (0x1u << 24) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
191 #define AIC_IPR2_PID89 (0x1u << 25) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
192 #define AIC_IPR2_PID90 (0x1u << 26) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
193 #define AIC_IPR2_PID91 (0x1u << 27) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
194 #define AIC_IPR2_PID92 (0x1u << 28) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
195 #define AIC_IPR2_PID93 (0x1u << 29) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
196 #define AIC_IPR2_PID94 (0x1u << 30) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
197 #define AIC_IPR2_PID95 (0x1u << 31) /**< \brief (AIC_IPR2) Interrupt Pending */
\r
198 /* -------- AIC_IPR3 : (AIC Offset: 0x2C) Interrupt Pending Register 3 -------- */
\r
199 #define AIC_IPR3_PID96 (0x1u << 0) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
200 #define AIC_IPR3_PID97 (0x1u << 1) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
201 #define AIC_IPR3_PID98 (0x1u << 2) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
202 #define AIC_IPR3_PID99 (0x1u << 3) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
203 #define AIC_IPR3_PID100 (0x1u << 4) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
204 #define AIC_IPR3_PID101 (0x1u << 5) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
205 #define AIC_IPR3_PID102 (0x1u << 6) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
206 #define AIC_IPR3_PID103 (0x1u << 7) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
207 #define AIC_IPR3_PID104 (0x1u << 8) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
208 #define AIC_IPR3_PID105 (0x1u << 9) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
209 #define AIC_IPR3_PID106 (0x1u << 10) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
210 #define AIC_IPR3_PID107 (0x1u << 11) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
211 #define AIC_IPR3_PID108 (0x1u << 12) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
212 #define AIC_IPR3_PID109 (0x1u << 13) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
213 #define AIC_IPR3_PID110 (0x1u << 14) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
214 #define AIC_IPR3_PID111 (0x1u << 15) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
215 #define AIC_IPR3_PID112 (0x1u << 16) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
216 #define AIC_IPR3_PID113 (0x1u << 17) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
217 #define AIC_IPR3_PID114 (0x1u << 18) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
218 #define AIC_IPR3_PID115 (0x1u << 19) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
219 #define AIC_IPR3_PID116 (0x1u << 20) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
220 #define AIC_IPR3_PID117 (0x1u << 21) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
221 #define AIC_IPR3_PID118 (0x1u << 22) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
222 #define AIC_IPR3_PID119 (0x1u << 23) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
223 #define AIC_IPR3_PID120 (0x1u << 24) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
224 #define AIC_IPR3_PID121 (0x1u << 25) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
225 #define AIC_IPR3_PID122 (0x1u << 26) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
226 #define AIC_IPR3_PID123 (0x1u << 27) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
227 #define AIC_IPR3_PID124 (0x1u << 28) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
228 #define AIC_IPR3_PID125 (0x1u << 29) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
229 #define AIC_IPR3_PID126 (0x1u << 30) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
230 #define AIC_IPR3_PID127 (0x1u << 31) /**< \brief (AIC_IPR3) Interrupt Pending */
\r
231 /* -------- AIC_IMR : (AIC Offset: 0x30) Interrupt Mask Register -------- */
\r
232 #define AIC_IMR_INTM (0x1u << 0) /**< \brief (AIC_IMR) Interrupt Mask */
\r
233 /* -------- AIC_CISR : (AIC Offset: 0x34) Core Interrupt Status Register -------- */
\r
234 #define AIC_CISR_NFIQ (0x1u << 0) /**< \brief (AIC_CISR) NFIQ Status */
\r
235 #define AIC_CISR_NIRQ (0x1u << 1) /**< \brief (AIC_CISR) NIRQ Status */
\r
236 /* -------- AIC_EOICR : (AIC Offset: 0x38) End of Interrupt Command Register -------- */
\r
237 #define AIC_EOICR_ENDIT (0x1u << 0) /**< \brief (AIC_EOICR) Interrupt Processing Complete Command */
\r
238 /* -------- AIC_SPU : (AIC Offset: 0x3C) Spurious Interrupt Vector Register -------- */
\r
239 #define AIC_SPU_SIVR_Pos 0
\r
240 #define AIC_SPU_SIVR_Msk (0xffffffffu << AIC_SPU_SIVR_Pos) /**< \brief (AIC_SPU) Spurious Interrupt Vector Register */
\r
241 #define AIC_SPU_SIVR(value) ((AIC_SPU_SIVR_Msk & ((value) << AIC_SPU_SIVR_Pos)))
\r
242 /* -------- AIC_IECR : (AIC Offset: 0x40) Interrupt Enable Command Register -------- */
\r
243 #define AIC_IECR_INTEN (0x1u << 0) /**< \brief (AIC_IECR) Interrupt Enable */
\r
244 /* -------- AIC_IDCR : (AIC Offset: 0x44) Interrupt Disable Command Register -------- */
\r
245 #define AIC_IDCR_INTD (0x1u << 0) /**< \brief (AIC_IDCR) Interrupt Disable */
\r
246 /* -------- AIC_ICCR : (AIC Offset: 0x48) Interrupt Clear Command Register -------- */
\r
247 #define AIC_ICCR_INTCLR (0x1u << 0) /**< \brief (AIC_ICCR) Interrupt Clear */
\r
248 /* -------- AIC_ISCR : (AIC Offset: 0x4C) Interrupt Set Command Register -------- */
\r
249 #define AIC_ISCR_INTSET (0x1u << 0) /**< \brief (AIC_ISCR) Interrupt Set */
\r
250 /* -------- AIC_DCR : (AIC Offset: 0x6C) Debug Control Register -------- */
\r
251 #define AIC_DCR_PROT (0x1u << 0) /**< \brief (AIC_DCR) Protection Mode */
\r
252 #define AIC_DCR_GMSK (0x1u << 1) /**< \brief (AIC_DCR) General Interrupt Mask */
\r
253 /* -------- AIC_WPMR : (AIC Offset: 0xE4) Write Protection Mode Register -------- */
\r
254 #define AIC_WPMR_WPEN (0x1u << 0) /**< \brief (AIC_WPMR) Write Protection Enable */
\r
255 #define AIC_WPMR_WPKEY_Pos 8
\r
256 #define AIC_WPMR_WPKEY_Msk (0xffffffu << AIC_WPMR_WPKEY_Pos) /**< \brief (AIC_WPMR) Write Protection Key */
\r
257 #define AIC_WPMR_WPKEY(value) ((AIC_WPMR_WPKEY_Msk & ((value) << AIC_WPMR_WPKEY_Pos)))
\r
258 #define AIC_WPMR_WPKEY_PASSWD (0x414943u << 8) /**< \brief (AIC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
\r
259 /* -------- AIC_WPSR : (AIC Offset: 0xE8) Write Protection Status Register -------- */
\r
260 #define AIC_WPSR_WPVS (0x1u << 0) /**< \brief (AIC_WPSR) Write Protection Violation Status */
\r
261 #define AIC_WPSR_WPVSRC_Pos 8
\r
262 #define AIC_WPSR_WPVSRC_Msk (0xffffu << AIC_WPSR_WPVSRC_Pos) /**< \brief (AIC_WPSR) Write Protection Violation Source */
\r
263 /* -------- AIC_VERSION : (AIC Offset: 0XFC) AIC Version Register -------- */
\r
264 #define AIC_VERSION_VERSION_Pos 0
\r
265 #define AIC_VERSION_VERSION_Msk (0xfffu << AIC_VERSION_VERSION_Pos) /**< \brief (AIC_VERSION) Version of the Hardware Module */
\r
266 #define AIC_VERSION_MFN_Pos 16
\r
267 #define AIC_VERSION_MFN_Msk (0x7u << AIC_VERSION_MFN_Pos) /**< \brief (AIC_VERSION) Metal Fix Number */
\r
272 #endif /* _SAMA5D2_AIC_COMPONENT_ */
\r
projects / freertos / blob