git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_intr.c

   1 /* $Id: xemacps_intr.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
   2 /******************************************************************************
   3 *
   4 * Copyright (C) 2010 - 2014 Xilinx, Inc.  All rights reserved.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * Use of the Software is limited solely to applications:
  17 * (a) running on a Xilinx device, or
  18 * (b) that interact with a Xilinx device through a bus or interconnect.
  19 *
  20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  25 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  26 * SOFTWARE.
  27 *
  28 * Except as contained in this notice, the name of the Xilinx shall not be used
  29 * in advertising or otherwise to promote the sale, use or other dealings in
  30 * this Software without prior written authorization from Xilinx.
  31 *
  32 ******************************************************************************/
  33 /*****************************************************************************/
  34 /**
  35 *
  36 * @file xemacps_intr.c
  37 * @addtogroup emacps_v2_0
  38 * @{
  39 *
  40 * Functions in this file implement general purpose interrupt processing related
  41 * functionality. See xemacps.h for a detailed description of the driver.
  42 *
  43 * <pre>
  44 * MODIFICATION HISTORY:
  45 *
  46 * Ver   Who  Date     Changes
  47 * ----- ---- -------- -------------------------------------------------------
  48 * 1.00a wsy  01/10/10 First release
  49 * 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
  50 *                     Rx errors. Under heavy Rx traffic, there will be a large
  51 *                     number of errors related to receive buffer not available.
  52 *                     Because of a HW bug (SI #692601), under such heavy errors,
  53 *                     the Rx data path can become unresponsive. To reduce the
  54 *                     probabilities for hitting this HW bug, the SW writes to
  55 *                     bit 18 to flush a packet from Rx DPRAM immediately. The
  56 *                     changes for it are done in the function
  57 *                     XEmacPs_IntrHandler.
  58 * </pre>
  59 ******************************************************************************/
  60
  61 /***************************** Include Files *********************************/
  62
  63 #include "xemacps.h"
  64
  65 /************************** Constant Definitions *****************************/
  66
  67
  68 /**************************** Type Definitions *******************************/
  69
  70
  71 /***************** Macros (Inline Functions) Definitions *********************/
  72
  73
  74 /************************** Function Prototypes ******************************/
  75
  76
  77 /************************** Variable Definitions *****************************/
  78
  79
  80 /*****************************************************************************/
  81 /**
  82  * Install an asynchronious handler function for the given HandlerType:
  83  *
  84  * @param InstancePtr is a pointer to the instance to be worked on.
  85  * @param HandlerType indicates what interrupt handler type is.
  86  *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
  87  *        XEMACPS_HANDLER_ERROR.
  88  * @param FuncPtr is the pointer to the callback function
  89  * @param CallBackRef is the upper layer callback reference passed back when
  90  *        when the callback function is invoked.
  91  *
  92  * @return
  93  *
  94  * None.
  95  *
  96  * @note
  97  * There is no assert on the CallBackRef since the driver doesn't know what
  98  * it is.
  99  *
 100  *****************************************************************************/
 101 int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
 102                         void *FuncPtr, void *CallBackRef)
 103 {
 104         Xil_AssertNonvoid(InstancePtr != NULL);
 105         Xil_AssertNonvoid(FuncPtr != NULL);
 106         Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 107
 108         switch (HandlerType) {
 109         case XEMACPS_HANDLER_DMASEND:
 110                 InstancePtr->SendHandler = (XEmacPs_Handler) FuncPtr;
 111                 InstancePtr->SendRef = CallBackRef;
 112                 break;
 113         case XEMACPS_HANDLER_DMARECV:
 114                 InstancePtr->RecvHandler = (XEmacPs_Handler) FuncPtr;
 115                 InstancePtr->RecvRef = CallBackRef;
 116                 break;
 117         case XEMACPS_HANDLER_ERROR:
 118                 InstancePtr->ErrorHandler = (XEmacPs_ErrHandler) FuncPtr;
 119                 InstancePtr->ErrorRef = CallBackRef;
 120                 break;
 121         default:
 122                 return (XST_INVALID_PARAM);
 123         }
 124         return (XST_SUCCESS);
 125 }
 126
 127 /*****************************************************************************/
 128 /**
 129 * Master interrupt handler for EMAC driver. This routine will query the
 130 * status of the device, bump statistics, and invoke user callbacks.
 131 *
 132 * This routine must be connected to an interrupt controller using OS/BSP
 133 * specific methods.
 134 *
 135 * @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
 136 *        interrupt.
 137 *
 138 ******************************************************************************/
 139 void XEmacPs_IntrHandler(void *XEmacPsPtr)
 140 {
 141         u32 RegISR;
 142         u32 RegSR;
 143         u32 RegCtrl;
 144         XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
 145
 146         Xil_AssertVoid(InstancePtr != NULL);
 147         Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 148
 149         /* This ISR will try to handle as many interrupts as it can in a single
 150          * call. However, in most of the places where the user's error handler
 151          * is called, this ISR exits because it is expected that the user will
 152          * reset the device in nearly all instances.
 153          */
 154         RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 155                                    XEMACPS_ISR_OFFSET);
 156
 157         /* Clear the interrupt status register */
 158         XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
 159                            RegISR);
 160
 161         /* Receive complete interrupt */
 162         if (RegISR & (XEMACPS_IXR_FRAMERX_MASK)) {
 163                 /* Clear RX status register RX complete indication but preserve
 164                  * error bits if there is any */
 165                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 166                                    XEMACPS_RXSR_OFFSET,
 167                                    XEMACPS_RXSR_FRAMERX_MASK |
 168                                    XEMACPS_RXSR_BUFFNA_MASK);
 169                 InstancePtr->RecvHandler(InstancePtr->RecvRef);
 170         }
 171
 172         /* Transmit complete interrupt */
 173         if (RegISR & (XEMACPS_IXR_TXCOMPL_MASK)) {
 174                 /* Clear TX status register TX complete indication but preserve
 175                  * error bits if there is any */
 176                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 177                                    XEMACPS_TXSR_OFFSET,
 178                                    XEMACPS_TXSR_TXCOMPL_MASK |
 179                                    XEMACPS_TXSR_USEDREAD_MASK);
 180                 InstancePtr->SendHandler(InstancePtr->SendRef);
 181         }
 182
 183         /* Receive error conditions interrupt */
 184         if (RegISR & (XEMACPS_IXR_RX_ERR_MASK)) {
 185                 /* Clear RX status register */
 186                 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 187                                           XEMACPS_RXSR_OFFSET);
 188                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 189                                    XEMACPS_RXSR_OFFSET, RegSR);
 190
 191                 /* Fix for CR # 692702. Write to bit 18 of net_ctrl
 192                  * register to flush a packet out of Rx SRAM upon
 193                  * an error for receive buffer not available. */
 194                 if (RegISR & XEMACPS_IXR_RXUSED_MASK) {
 195                         RegCtrl =
 196                         XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 197                                                 XEMACPS_NWCTRL_OFFSET);
 198                         RegCtrl |= XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
 199                         XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 200                                         XEMACPS_NWCTRL_OFFSET, RegCtrl);
 201                 }
 202                 InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_RECV,
 203                                           RegSR);
 204         }
 205
 206         /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
 207          * will be asserted the same time.
 208          * Have to distinguish this bit to handle the real error condition.
 209          */
 210         /* Transmit error conditions interrupt */
 211         if (RegISR & (XEMACPS_IXR_TX_ERR_MASK) &&
 212             !(RegISR & (XEMACPS_IXR_TXCOMPL_MASK))) {
 213                 /* Clear TX status register */
 214                 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
 215                                           XEMACPS_TXSR_OFFSET);
 216                 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
 217                                    XEMACPS_TXSR_OFFSET, RegSR);
 218                 InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
 219                                           RegSR);
 220         }
 221
 222 }
 223 /** @} */