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   1 /******************************************************************************
   2 *
   3 * Copyright (C) 2013 - 2014 Xilinx, Inc.  All rights reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a copy
   6 * of this software and associated documentation files (the "Software"), to deal
   7 * in the Software without restriction, including without limitation the rights
   8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9 * copies of the Software, and to permit persons to whom the Software is
  10 * furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * Use of the Software is limited solely to applications:
  16 * (a) running on a Xilinx device, or
  17 * (b) that interact with a Xilinx device through a bus or interconnect.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  23 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  24 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25 * SOFTWARE.
  26 *
  27 * Except as contained in this notice, the name of the Xilinx shall not be used
  28 * in advertising or otherwise to promote the sale, use or other dealings in
  29 * this Software without prior written authorization from Xilinx.
  30 *
  31 ******************************************************************************/
  32 /*****************************************************************************/
  33 /**
  34 *
  35 * @file xqspips_hw.c
  36 * @addtogroup qspips_v3_0
  37 * @{
  38 *
  39 * Contains low level functions, primarily reset related.
  40 *
  41 * <pre>
  42 * MODIFICATION HISTORY:
  43 *
  44 * Ver   Who Date     Changes
  45 * ----- --- -------- -----------------------------------------------
  46 * 2.03a hk  09/17/13 First release
  47 *
  48 * </pre>
  49 *
  50 ******************************************************************************/
  51
  52 /***************************** Include Files *********************************/
  53
  54 #include "xqspips_hw.h"
  55 #include "xqspips.h"
  56
  57 /************************** Constant Definitions *****************************/
  58
  59 /** @name Pre-scaler value for divided by 4
  60  *
  61  * Pre-scaler value for divided by 4
  62  *
  63  * @{
  64  */
  65 #define XQSPIPS_CR_PRESC_DIV_BY_4       0x01
  66 /* @} */
  67
  68 /**************************** Type Definitions *******************************/
  69
  70 /***************** Macros (Inline Functions) Definitions *********************/
  71
  72 /************************** Function Prototypes ******************************/
  73
  74 /************************** Variable Definitions *****************************/
  75
  76
  77 /*****************************************************************************/
  78 /**
  79 *
  80 * Resets QSPI by disabling the device and bringing it to reset state through
  81 * register writes.
  82 *
  83 * @param        None
  84 *
  85 * @return       None.
  86 *
  87 * @note         None.
  88 *
  89 ******************************************************************************/
  90 void XQspiPs_ResetHw(u32 BaseAddress)
  91 {
  92         u32 ConfigReg;
  93
  94         /*
  95          * Disable interrupts
  96          */
  97         XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
  98                                 XQSPIPS_IXR_DISABLE_ALL);
  99
 100         /*
 101          * Disable device
 102          */
 103         XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
 104                                 0);
 105
 106         /*
 107          * De-assert slave select lines.
 108          */
 109         ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
 110         ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
 111         XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
 112
 113         /*
 114          * Write default value to RX and TX threshold registers
 115          * RX threshold should be set to 1 here because the corresponding
 116          * status bit is used next to clear the RXFIFO
 117          */
 118         XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
 119                         (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
 120         XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
 121                         (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
 122
 123         /*
 124          * Clear RXFIFO
 125          */
 126         while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
 127                 XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
 128                 XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
 129         }
 130
 131         /*
 132          * Clear status register by reading register and
 133          * writing 1 to clear the write to clear bits
 134          */
 135         XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
 136         XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
 137                                 XQSPIPS_IXR_WR_TO_CLR_MASK);
 138
 139         /*
 140          * Write default value to configuration register
 141          */
 142         XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
 143                                 XQSPIPS_CR_RESET_STATE);
 144
 145
 146         /*
 147          * De-select linear mode
 148          */
 149         XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
 150                                 0x0);
 151
 152 }
 153
 154 /*****************************************************************************/
 155 /**
 156 *
 157 * Initializes QSPI to Linear mode with default QSPI boot settings.
 158 *
 159 * @param        None
 160 *
 161 * @return       None.
 162 *
 163 * @note         None.
 164 *
 165 ******************************************************************************/
 166 void XQspiPs_LinearInit(u32 BaseAddress)
 167 {
 168         u32 BaudRateDiv;
 169         u32 LinearCfg;
 170
 171         /*
 172          * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
 173          * should be set to 0x001; hence shift the value and use the mask.
 174          */
 175         BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
 176                         XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
 177         /*
 178          * Write configuration register with default values, slave selected &
 179          * pre-scaler value for divide by 4
 180          */
 181         XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
 182                                 ((XQSPIPS_CR_RESET_STATE |
 183                                 XQSPIPS_CR_HOLD_B_MASK | BaudRateDiv) &
 184                                 (~XQSPIPS_CR_SSCTRL_MASK) ));
 185
 186         /*
 187          * Write linear configuration register with default value -
 188          * enable linear mode and use fast read.
 189          */
 190
 191         if(XPAR_PS7_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
 192
 193                 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
 194
 195         }else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
 196                         XQSPIPS_CONNECTION_MODE_STACKED){
 197
 198                 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
 199                                 XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
 200
 201         }else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
 202                         XQSPIPS_CONNECTION_MODE_PARALLEL){
 203
 204                 LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
 205                                 XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
 206                                 XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
 207
 208         }
 209
 210         XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
 211                                 LinearCfg);
 212
 213         /*
 214          * Enable device
 215          */
 216         XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
 217                                 XQSPIPS_ER_ENABLE_MASK);
 218
 219 }
 220
 221
 222 /** @} */