2 ******************************************************************************
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3 * @file stm32h7xx_hal_rcc_ex.c
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4 * @author MCD Application Team
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5 * @brief Extended RCC HAL module driver.
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6 * This file provides firmware functions to manage the following
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7 * functionalities RCC extension peripheral:
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8 * + Extended Peripheral Control functions
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10 ******************************************************************************
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13 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
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14 * All rights reserved.</center></h2>
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16 * This software component is licensed by ST under BSD 3-Clause license,
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17 * the "License"; You may not use this file except in compliance with the
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18 * License. You may obtain a copy of the License at:
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19 * opensource.org/licenses/BSD-3-Clause
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21 ******************************************************************************
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24 /* Includes ------------------------------------------------------------------*/
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25 #include "stm32h7xx_hal.h"
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27 /** @addtogroup STM32H7xx_HAL_Driver
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31 /** @defgroup RCCEx RCCEx
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32 * @brief RCC HAL module driver
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36 #ifdef HAL_RCC_MODULE_ENABLED
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38 /* Private typedef -----------------------------------------------------------*/
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39 /* Private defines -----------------------------------------------------------*/
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40 /** @defgroup RCCEx_Private_defines Private Defines
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43 #define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
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44 #define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
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46 #define DIVIDER_P_UPDATE 0U
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47 #define DIVIDER_Q_UPDATE 1U
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48 #define DIVIDER_R_UPDATE 2U
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53 /* Private macros ------------------------------------------------------------*/
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54 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
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61 /* Private variables ---------------------------------------------------------*/
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62 /* Private function prototypes -----------------------------------------------*/
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63 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
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64 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
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67 /* Exported functions --------------------------------------------------------*/
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69 /** @defgroup RCCEx_Exported_Functions Exported Functions
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73 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
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74 * @brief Extended Peripheral Control functions
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77 ===============================================================================
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78 ##### Extended Peripheral Control functions #####
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79 ===============================================================================
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81 This subsection provides a set of functions allowing to control the RCC Clocks
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84 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
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85 select the RTC clock source; in this case the Backup domain will be reset in
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86 order to modify the RTC Clock source, as consequence RTC registers (including
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87 the backup registers) and RCC_BDCR register are set to their reset values.
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93 * @brief Initializes the RCC extended peripherals clocks according to the specified
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94 * parameters in the RCC_PeriphCLKInitTypeDef.
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95 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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96 * contains the configuration information for the Extended Peripherals
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97 * clocks(SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
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98 * USART234578, USART16, RNG, HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
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99 * SAI4A,SAI4B,SPI6,RTC).
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100 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
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101 * the RTC clock source; in this case the Backup domain will be reset in
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102 * order to modify the RTC Clock source, as consequence RTC registers (including
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103 * the backup registers) are set to their reset values.
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105 * @retval HAL status
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107 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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110 uint32_t tickstart;
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111 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
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112 HAL_StatusTypeDef status = HAL_OK; /* Final status */
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114 /*---------------------------- SPDIFRX configuration -------------------------------*/
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116 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
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119 switch(PeriphClkInit->SpdifrxClockSelection)
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121 case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/
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122 /* Enable SAI Clock output generated form System PLL . */
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123 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
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125 /* SAI1 clock source configuration done later after clock selection check */
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128 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
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130 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
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132 /* SAI1 clock source configuration done later after clock selection check */
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135 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/
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136 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
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138 /* SAI1 clock source configuration done later after clock selection check */
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141 case RCC_SPDIFRXCLKSOURCE_HSI:
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142 /* Internal OSC clock is used as source of SPDIFRX clock*/
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143 /* SPDIFRX clock source configuration done later after clock selection check */
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153 /* Set the source of SPDIFRX clock*/
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154 __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
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158 /* set overall return value */
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163 /*---------------------------- SAI1 configuration -------------------------------*/
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164 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
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166 switch(PeriphClkInit->Sai1ClockSelection)
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168 case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
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169 /* Enable SAI Clock output generated form System PLL . */
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170 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
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172 /* SAI1 clock source configuration done later after clock selection check */
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175 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
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177 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
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179 /* SAI1 clock source configuration done later after clock selection check */
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182 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
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183 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
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185 /* SAI1 clock source configuration done later after clock selection check */
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188 case RCC_SAI1CLKSOURCE_PIN:
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189 /* External clock is used as source of SAI1 clock*/
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190 /* SAI1 clock source configuration done later after clock selection check */
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193 case RCC_SAI1CLKSOURCE_CLKP:
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194 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
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195 /* SAI1 clock source configuration done later after clock selection check */
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205 /* Set the source of SAI1 clock*/
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206 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
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210 /* set overall return value */
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215 /*---------------------------- SAI2/3 configuration -------------------------------*/
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216 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
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218 switch(PeriphClkInit->Sai23ClockSelection)
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220 case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */
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221 /* Enable SAI Clock output generated form System PLL . */
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222 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
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224 /* SAI2/3 clock source configuration done later after clock selection check */
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227 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
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229 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
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231 /* SAI2/3 clock source configuration done later after clock selection check */
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234 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */
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235 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
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237 /* SAI2/3 clock source configuration done later after clock selection check */
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240 case RCC_SAI23CLKSOURCE_PIN:
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241 /* External clock is used as source of SAI2/3 clock*/
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242 /* SAI2/3 clock source configuration done later after clock selection check */
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245 case RCC_SAI23CLKSOURCE_CLKP:
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246 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
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247 /* SAI2/3 clock source configuration done later after clock selection check */
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257 /* Set the source of SAI2/3 clock*/
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258 __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
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262 /* set overall return value */
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267 /*---------------------------- SAI4A configuration -------------------------------*/
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268 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
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270 switch(PeriphClkInit->Sai4AClockSelection)
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272 case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
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273 /* Enable SAI Clock output generated form System PLL . */
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274 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
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276 /* SAI1 clock source configuration done later after clock selection check */
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279 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
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281 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
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283 /* SAI2 clock source configuration done later after clock selection check */
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286 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
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287 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
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289 /* SAI1 clock source configuration done later after clock selection check */
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292 case RCC_SAI4ACLKSOURCE_PIN:
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293 /* External clock is used as source of SAI2 clock*/
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294 /* SAI2 clock source configuration done later after clock selection check */
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297 case RCC_SAI4ACLKSOURCE_CLKP:
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298 /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
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299 /* SAI1 clock source configuration done later after clock selection check */
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309 /* Set the source of SAI2 clock*/
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310 __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
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314 /* set overall return value */
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318 /*---------------------------- SAI4B configuration -------------------------------*/
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319 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
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321 switch(PeriphClkInit->Sai4BClockSelection)
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323 case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
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324 /* Enable SAI Clock output generated form System PLL . */
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325 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
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327 /* SAI1 clock source configuration done later after clock selection check */
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330 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
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332 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
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334 /* SAI2 clock source configuration done later after clock selection check */
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337 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
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338 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
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340 /* SAI1 clock source configuration done later after clock selection check */
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343 case RCC_SAI4BCLKSOURCE_PIN:
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344 /* External clock is used as source of SAI2 clock*/
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345 /* SAI2 clock source configuration done later after clock selection check */
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348 case RCC_SAI4BCLKSOURCE_CLKP:
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349 /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
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350 /* SAI1 clock source configuration done later after clock selection check */
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360 /* Set the source of SAI2 clock*/
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361 __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
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365 /* set overall return value */
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369 /*---------------------------- QSPI configuration -------------------------------*/
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370 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
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372 switch(PeriphClkInit->QspiClockSelection)
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374 case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/
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375 /* Enable QSPI Clock output generated form System PLL . */
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376 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
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378 /* QSPI clock source configuration done later after clock selection check */
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381 case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
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383 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
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385 /* QSPI clock source configuration done later after clock selection check */
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389 case RCC_QSPICLKSOURCE_CLKP:
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390 /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
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391 /* QSPI clock source configuration done later after clock selection check */
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394 case RCC_QSPICLKSOURCE_D1HCLK:
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395 /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */
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405 /* Set the source of QSPI clock*/
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406 __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
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410 /* set overall return value */
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415 /*---------------------------- SPI1/2/3 configuration -------------------------------*/
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416 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
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418 switch(PeriphClkInit->Spi123ClockSelection)
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420 case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */
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421 /* Enable SPI Clock output generated form System PLL . */
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422 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
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424 /* SPI1/2/3 clock source configuration done later after clock selection check */
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427 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
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428 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
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430 /* SPI1/2/3 clock source configuration done later after clock selection check */
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433 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */
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434 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
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436 /* SPI1/2/3 clock source configuration done later after clock selection check */
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439 case RCC_SPI123CLKSOURCE_PIN:
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440 /* External clock is used as source of SPI1/2/3 clock*/
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441 /* SPI1/2/3 clock source configuration done later after clock selection check */
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444 case RCC_SPI123CLKSOURCE_CLKP:
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445 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
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446 /* SPI1/2/3 clock source configuration done later after clock selection check */
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456 /* Set the source of SPI1/2/3 clock*/
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457 __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
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461 /* set overall return value */
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466 /*---------------------------- SPI4/5 configuration -------------------------------*/
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467 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
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469 switch(PeriphClkInit->Spi45ClockSelection)
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471 case RCC_SPI45CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for SPI4/5 */
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472 /* SPI4/5 clock source configuration done later after clock selection check */
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475 case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
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477 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
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479 /* SPI4/5 clock source configuration done later after clock selection check */
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481 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */
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482 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
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483 /* SPI4/5 clock source configuration done later after clock selection check */
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486 case RCC_SPI45CLKSOURCE_HSI:
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487 /* HSI oscillator clock is used as source of SPI4/5 clock*/
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488 /* SPI4/5 clock source configuration done later after clock selection check */
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491 case RCC_SPI45CLKSOURCE_CSI:
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492 /* CSI oscillator clock is used as source of SPI4/5 clock */
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493 /* SPI4/5 clock source configuration done later after clock selection check */
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496 case RCC_SPI45CLKSOURCE_HSE:
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497 /* HSE, oscillator is used as source of SPI4/5 clock */
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498 /* SPI4/5 clock source configuration done later after clock selection check */
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508 /* Set the source of SPI4/5 clock*/
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509 __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
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513 /* set overall return value */
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518 /*---------------------------- SPI6 configuration -------------------------------*/
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519 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
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521 switch(PeriphClkInit->Spi6ClockSelection)
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523 case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for SPI6*/
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524 /* SPI6 clock source configuration done later after clock selection check */
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527 case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
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529 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
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531 /* SPI6 clock source configuration done later after clock selection check */
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533 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/
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534 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
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535 /* SPI6 clock source configuration done later after clock selection check */
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538 case RCC_SPI6CLKSOURCE_HSI:
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539 /* HSI oscillator clock is used as source of SPI6 clock*/
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540 /* SPI6 clock source configuration done later after clock selection check */
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543 case RCC_SPI6CLKSOURCE_CSI:
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544 /* CSI oscillator clock is used as source of SPI6 clock */
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545 /* SPI6 clock source configuration done later after clock selection check */
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548 case RCC_SPI6CLKSOURCE_HSE:
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549 /* HSE, oscillator is used as source of SPI6 clock */
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550 /* SPI6 clock source configuration done later after clock selection check */
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560 /* Set the source of SPI6 clock*/
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561 __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
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565 /* set overall return value */
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571 /*---------------------------- DSI configuration -------------------------------*/
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572 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
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574 switch(PeriphClkInit->DsiClockSelection)
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577 case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
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579 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
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581 /* DSI clock source configuration done later after clock selection check */
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584 case RCC_DSICLKSOURCE_PHY:
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585 /* PHY is used as clock source for DSI*/
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586 /* DSI clock source configuration done later after clock selection check */
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596 /* Set the source of DSI clock*/
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597 __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
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601 /* set overall return value */
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607 #if defined(FDCAN1) || defined(FDCAN2)
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608 /*---------------------------- FDCAN configuration -------------------------------*/
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609 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
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611 switch(PeriphClkInit->FdcanClockSelection)
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613 case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/
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614 /* Enable FDCAN Clock output generated form System PLL . */
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615 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
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617 /* FDCAN clock source configuration done later after clock selection check */
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620 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
\r
622 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
\r
624 /* FDCAN clock source configuration done later after clock selection check */
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627 case RCC_FDCANCLKSOURCE_HSE:
\r
628 /* HSE is used as clock source for FDCAN*/
\r
629 /* FDCAN clock source configuration done later after clock selection check */
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639 /* Set the source of FDCAN clock*/
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640 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
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644 /* set overall return value */
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649 #endif /*FDCAN1 || FDCAN2*/
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650 /*---------------------------- FMC configuration -------------------------------*/
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651 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
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653 switch(PeriphClkInit->FmcClockSelection)
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655 case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/
\r
656 /* Enable FMC Clock output generated form System PLL . */
\r
657 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
\r
659 /* FMC clock source configuration done later after clock selection check */
\r
662 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
\r
664 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
\r
666 /* FMC clock source configuration done later after clock selection check */
\r
670 case RCC_FMCCLKSOURCE_CLKP:
\r
671 /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
\r
672 /* FMC clock source configuration done later after clock selection check */
\r
675 case RCC_FMCCLKSOURCE_D1HCLK:
\r
676 /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */
\r
686 /* Set the source of FMC clock*/
\r
687 __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
\r
691 /* set overall return value */
\r
696 /*---------------------------- RTC configuration -------------------------------*/
\r
697 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
\r
699 /* check for RTC Parameters used to output RTCCLK */
\r
700 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
\r
702 /* Enable write access to Backup domain */
\r
703 SET_BIT(PWR->CR1, PWR_CR1_DBP);
\r
705 /* Wait for Backup domain Write protection disable */
\r
706 tickstart = HAL_GetTick();
\r
708 while((PWR->CR1 & PWR_CR1_DBP) == 0U)
\r
710 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
\r
719 /* Reset the Backup domain only if the RTC Clock source selection is modified */
\r
720 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
\r
722 /* Store the content of BDCR register before the reset of Backup Domain */
\r
723 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
\r
724 /* RTC Clock selection can be changed only if the Backup Domain is reset */
\r
725 __HAL_RCC_BACKUPRESET_FORCE();
\r
726 __HAL_RCC_BACKUPRESET_RELEASE();
\r
727 /* Restore the Content of BDCR register */
\r
728 RCC->BDCR = tmpreg;
\r
731 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
\r
732 if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
\r
734 /* Get Start Tick*/
\r
735 tickstart = HAL_GetTick();
\r
737 /* Wait till LSE is ready */
\r
738 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
\r
740 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
\r
750 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
\r
754 /* set overall return value */
\r
760 /* set overall return value */
\r
766 /*-------------------------- USART1/6 configuration --------------------------*/
\r
767 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
\r
769 switch(PeriphClkInit->Usart16ClockSelection)
\r
771 case RCC_USART16CLKSOURCE_D2PCLK2: /* D2PCLK2 as clock source for USART1/6 */
\r
772 /* USART1/6 clock source configuration done later after clock selection check */
\r
775 case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
\r
776 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
\r
777 /* USART1/6 clock source configuration done later after clock selection check */
\r
780 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
\r
781 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
\r
782 /* USART1/6 clock source configuration done later after clock selection check */
\r
785 case RCC_USART16CLKSOURCE_HSI:
\r
786 /* HSI oscillator clock is used as source of USART1/6 clock */
\r
787 /* USART1/6 clock source configuration done later after clock selection check */
\r
790 case RCC_USART16CLKSOURCE_CSI:
\r
791 /* CSI oscillator clock is used as source of USART1/6 clock */
\r
792 /* USART1/6 clock source configuration done later after clock selection check */
\r
795 case RCC_USART16CLKSOURCE_LSE:
\r
796 /* LSE, oscillator is used as source of USART1/6 clock */
\r
797 /* USART1/6 clock source configuration done later after clock selection check */
\r
807 /* Set the source of USART1/6 clock */
\r
808 __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
\r
812 /* set overall return value */
\r
817 /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
\r
818 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
\r
820 switch(PeriphClkInit->Usart234578ClockSelection)
\r
822 case RCC_USART234578CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for USART2/3/4/5/7/8 */
\r
823 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
\r
826 case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
\r
827 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
\r
828 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
\r
831 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
\r
832 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
\r
833 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
\r
836 case RCC_USART234578CLKSOURCE_HSI:
\r
837 /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
\r
838 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
\r
841 case RCC_USART234578CLKSOURCE_CSI:
\r
842 /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
\r
843 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
\r
846 case RCC_USART234578CLKSOURCE_LSE:
\r
847 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */
\r
848 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
\r
858 /* Set the source of USART2/3/4/5/7/8 clock */
\r
859 __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
\r
863 /* set overall return value */
\r
868 /*-------------------------- LPUART1 Configuration -------------------------*/
\r
869 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
\r
871 switch(PeriphClkInit->Lpuart1ClockSelection)
\r
873 case RCC_LPUART1CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPUART1 */
\r
874 /* LPUART1 clock source configuration done later after clock selection check */
\r
877 case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
\r
878 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
\r
879 /* LPUART1 clock source configuration done later after clock selection check */
\r
882 case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
\r
883 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
\r
884 /* LPUART1 clock source configuration done later after clock selection check */
\r
887 case RCC_LPUART1CLKSOURCE_HSI:
\r
888 /* HSI oscillator clock is used as source of LPUART1 clock */
\r
889 /* LPUART1 clock source configuration done later after clock selection check */
\r
892 case RCC_LPUART1CLKSOURCE_CSI:
\r
893 /* CSI oscillator clock is used as source of LPUART1 clock */
\r
894 /* LPUART1 clock source configuration done later after clock selection check */
\r
897 case RCC_LPUART1CLKSOURCE_LSE:
\r
898 /* LSE, oscillator is used as source of LPUART1 clock */
\r
899 /* LPUART1 clock source configuration done later after clock selection check */
\r
909 /* Set the source of LPUART1 clock */
\r
910 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
\r
914 /* set overall return value */
\r
919 /*---------------------------- LPTIM1 configuration -------------------------------*/
\r
920 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
\r
922 switch(PeriphClkInit->Lptim1ClockSelection)
\r
924 case RCC_LPTIM1CLKSOURCE_D2PCLK1: /* D2PCLK1 as clock source for LPTIM1*/
\r
925 /* LPTIM1 clock source configuration done later after clock selection check */
\r
928 case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
\r
930 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
\r
932 /* LPTIM1 clock source configuration done later after clock selection check */
\r
935 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/
\r
936 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
\r
938 /* LPTIM1 clock source configuration done later after clock selection check */
\r
941 case RCC_LPTIM1CLKSOURCE_LSE:
\r
942 /* External low speed OSC clock is used as source of LPTIM1 clock*/
\r
943 /* LPTIM1 clock source configuration done later after clock selection check */
\r
946 case RCC_LPTIM1CLKSOURCE_LSI:
\r
947 /* Internal low speed OSC clock is used as source of LPTIM1 clock*/
\r
948 /* LPTIM1 clock source configuration done later after clock selection check */
\r
950 case RCC_LPTIM1CLKSOURCE_CLKP:
\r
951 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
\r
952 /* LPTIM1 clock source configuration done later after clock selection check */
\r
962 /* Set the source of LPTIM1 clock*/
\r
963 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
\r
967 /* set overall return value */
\r
972 /*---------------------------- LPTIM2 configuration -------------------------------*/
\r
973 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
\r
975 switch(PeriphClkInit->Lptim2ClockSelection)
\r
977 case RCC_LPTIM2CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPTIM2*/
\r
978 /* LPTIM2 clock source configuration done later after clock selection check */
\r
981 case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
\r
983 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
\r
985 /* LPTIM2 clock source configuration done later after clock selection check */
\r
988 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/
\r
989 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
\r
991 /* LPTIM2 clock source configuration done later after clock selection check */
\r
994 case RCC_LPTIM2CLKSOURCE_LSE:
\r
995 /* External low speed OSC clock is used as source of LPTIM2 clock*/
\r
996 /* LPTIM2 clock source configuration done later after clock selection check */
\r
999 case RCC_LPTIM2CLKSOURCE_LSI:
\r
1000 /* Internal low speed OSC clock is used as source of LPTIM2 clock*/
\r
1001 /* LPTIM2 clock source configuration done later after clock selection check */
\r
1003 case RCC_LPTIM2CLKSOURCE_CLKP:
\r
1004 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
\r
1005 /* LPTIM2 clock source configuration done later after clock selection check */
\r
1015 /* Set the source of LPTIM2 clock*/
\r
1016 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
\r
1020 /* set overall return value */
\r
1025 /*---------------------------- LPTIM345 configuration -------------------------------*/
\r
1026 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
\r
1028 switch(PeriphClkInit->Lptim345ClockSelection)
\r
1031 case RCC_LPTIM345CLKSOURCE_D3PCLK1: /* D3PCLK1 as clock source for LPTIM3/4/5 */
\r
1032 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
\r
1035 case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
\r
1036 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
\r
1038 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
\r
1041 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */
\r
1042 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
\r
1044 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
\r
1047 case RCC_LPTIM345CLKSOURCE_LSE:
\r
1048 /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
\r
1049 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
\r
1052 case RCC_LPTIM345CLKSOURCE_LSI:
\r
1053 /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */
\r
1054 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
\r
1056 case RCC_LPTIM345CLKSOURCE_CLKP:
\r
1057 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
\r
1058 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
\r
1068 /* Set the source of LPTIM3/4/5 clock */
\r
1069 __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
\r
1073 /* set overall return value */
\r
1078 /*------------------------------ I2C1/2/3 Configuration ------------------------*/
\r
1079 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
\r
1081 /* Check the parameters */
\r
1082 assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
\r
1084 if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )
\r
1086 if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
\r
1088 status = HAL_ERROR;
\r
1094 __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
\r
1099 /*------------------------------ I2C4 Configuration ------------------------*/
\r
1100 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
\r
1102 /* Check the parameters */
\r
1103 assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
\r
1105 if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
\r
1107 if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
\r
1109 status = HAL_ERROR;
\r
1115 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
\r
1119 /*---------------------------- ADC configuration -------------------------------*/
\r
1120 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
\r
1122 switch(PeriphClkInit->AdcClockSelection)
\r
1125 case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
\r
1127 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
\r
1129 /* ADC clock source configuration done later after clock selection check */
\r
1132 case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/
\r
1133 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
\r
1135 /* ADC clock source configuration done later after clock selection check */
\r
1138 case RCC_ADCCLKSOURCE_CLKP:
\r
1139 /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
\r
1140 /* ADC clock source configuration done later after clock selection check */
\r
1150 /* Set the source of ADC clock*/
\r
1151 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
\r
1155 /* set overall return value */
\r
1160 /*------------------------------ USB Configuration -------------------------*/
\r
1161 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
\r
1164 switch(PeriphClkInit->UsbClockSelection)
\r
1166 case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/
\r
1167 /* Enable USB Clock output generated form System USB . */
\r
1168 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
\r
1170 /* USB clock source configuration done later after clock selection check */
\r
1173 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
\r
1175 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
\r
1177 /* USB clock source configuration done later after clock selection check */
\r
1180 case RCC_USBCLKSOURCE_HSI48:
\r
1181 /* HSI48 oscillator is used as source of USB clock */
\r
1182 /* USB clock source configuration done later after clock selection check */
\r
1192 /* Set the source of USB clock*/
\r
1193 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
\r
1197 /* set overall return value */
\r
1203 /*------------------------------------- SDMMC Configuration ------------------------------------*/
\r
1204 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
\r
1206 /* Check the parameters */
\r
1207 assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
\r
1209 switch(PeriphClkInit->SdmmcClockSelection)
\r
1211 case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/
\r
1212 /* Enable SDMMC Clock output generated form System PLL . */
\r
1213 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
\r
1215 /* SDMMC clock source configuration done later after clock selection check */
\r
1218 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
\r
1220 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
\r
1222 /* SDMMC clock source configuration done later after clock selection check */
\r
1232 /* Set the source of SDMMC clock*/
\r
1233 __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
\r
1237 /* set overall return value */
\r
1243 /*-------------------------------------- LTDC Configuration -----------------------------------*/
\r
1244 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
\r
1246 if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)
\r
1253 /*------------------------------ RNG Configuration -------------------------*/
\r
1254 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
\r
1257 switch(PeriphClkInit->RngClockSelection)
\r
1259 case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/
\r
1260 /* Enable RNG Clock output generated form System RNG . */
\r
1261 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
\r
1263 /* RNG clock source configuration done later after clock selection check */
\r
1266 case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
\r
1268 /* RNG clock source configuration done later after clock selection check */
\r
1271 case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
\r
1273 /* RNG clock source configuration done later after clock selection check */
\r
1275 case RCC_RNGCLKSOURCE_HSI48:
\r
1276 /* HSI48 oscillator is used as source of RNG clock */
\r
1277 /* RNG clock source configuration done later after clock selection check */
\r
1287 /* Set the source of RNG clock*/
\r
1288 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
\r
1292 /* set overall return value */
\r
1298 /*------------------------------ SWPMI1 Configuration ------------------------*/
\r
1299 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
\r
1301 /* Check the parameters */
\r
1302 assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
\r
1304 /* Configure the SWPMI1 interface clock source */
\r
1305 __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
\r
1308 /*------------------------------ HRTIM1 clock Configuration ----------------*/
\r
1309 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
\r
1311 /* Check the parameters */
\r
1312 assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
\r
1314 /* Configure the HRTIM1 clock source */
\r
1315 __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
\r
1318 /*------------------------------ DFSDM1 Configuration ------------------------*/
\r
1319 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
\r
1321 /* Check the parameters */
\r
1322 assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
\r
1324 /* Configure the DFSDM1 interface clock source */
\r
1325 __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
\r
1328 /*------------------------------------ TIM configuration --------------------------------------*/
\r
1329 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
\r
1331 /* Check the parameters */
\r
1332 assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
\r
1334 /* Configure Timer Prescaler */
\r
1335 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
\r
1338 /*------------------------------------ CKPER configuration --------------------------------------*/
\r
1339 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
\r
1341 /* Check the parameters */
\r
1342 assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
\r
1344 /* Configure the CKPER clock source */
\r
1345 __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
\r
1348 if (status == HAL_OK)
\r
1356 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
\r
1357 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
\r
1358 * returns the configuration information for the Extended Peripherals clocks :
\r
1359 * (SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
\r
1360 * USART234578, USART16, RNG,HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
\r
1361 * SAI4A,SAI4B,SPI6,RTC,TIM).
\r
1364 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
\r
1366 /* Set all possible values for the extended clock type parameter------------*/
\r
1367 PeriphClkInit->PeriphClockSelection =
\r
1368 RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C123 |
\r
1369 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 |
\r
1370 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI23 | RCC_PERIPHCLK_SAI4A | RCC_PERIPHCLK_SAI4B |
\r
1371 RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_FDCAN |
\r
1372 RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC |
\r
1373 RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CEC |
\r
1374 RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_SPDIFRX |
\r
1375 RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_CKPER;
\r
1378 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
\r
1381 /* Get the PLL3 Clock configuration -----------------------------------------------*/
\r
1382 PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);
\r
1383 PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U;
\r
1384 PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U;
\r
1385 PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U;
\r
1386 PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U;
\r
1387 PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
\r
1388 PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
\r
1390 /* Get the PLL2 Clock configuration -----------------------------------------------*/
\r
1391 PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos);
\r
1392 PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U;
\r
1393 PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U;
\r
1394 PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U;
\r
1395 PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U;
\r
1396 PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
\r
1397 PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
\r
1399 /* Get the USART1 configuration --------------------------------------------*/
\r
1400 PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE();
\r
1401 /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
\r
1402 PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE();
\r
1403 /* Get the LPUART1 clock source --------------------------------------------*/
\r
1404 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
\r
1405 /* Get the I2C1/2/3 clock source -------------------------------------------*/
\r
1406 PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
\r
1407 /* Get the LPTIM1 clock source ---------------------------------------------*/
\r
1408 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
\r
1409 /* Get the LPTIM2 clock source ---------------------------------------------*/
\r
1410 PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
\r
1411 /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
\r
1412 PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE();
\r
1413 /* Get the SAI1 clock source -----------------------------------------------*/
\r
1414 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
\r
1415 /* Get the SAI2/3 clock source ---------------------------------------------*/
\r
1416 PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE();
\r
1417 /* Get the SAI4A clock source ----------------------------------------------*/
\r
1418 PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE();
\r
1419 /* Get the SAI4B clock source ----------------------------------------------*/
\r
1420 PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE();
\r
1421 /* Get the RTC clock source ------------------------------------------------*/
\r
1422 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
\r
1423 /* Get the USB clock source ------------------------------------------------*/
\r
1424 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
\r
1425 /* Get the SDMMC clock source ----------------------------------------------*/
\r
1426 PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();
\r
1427 /* Get the RNG clock source ------------------------------------------------*/
\r
1428 PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
\r
1429 /* Get the HRTIM1 clock source ---------------------------------------------*/
\r
1430 PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
\r
1431 /* Get the ADC clock source ------------------------------------------------*/
\r
1432 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
\r
1433 /* Get the SWPMI1 clock source ---------------------------------------------*/
\r
1434 PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();
\r
1435 /* Get the DFSDM1 clock source ---------------------------------------------*/
\r
1436 PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
\r
1437 /* Get the SPDIFRX clock source --------------------------------------------*/
\r
1438 PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
\r
1439 /* Get the SPI1/2/3 clock source -------------------------------------------*/
\r
1440 PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE();
\r
1441 /* Get the SPI4/5 clock source ---------------------------------------------*/
\r
1442 PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE();
\r
1443 /* Get the SPI6 clock source -----------------------------------------------*/
\r
1444 PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
\r
1445 /* Get the FDCAN clock source ----------------------------------------------*/
\r
1446 PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
\r
1447 /* Get the CEC clock source ------------------------------------------------*/
\r
1448 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
\r
1449 /* Get the FMC clock source ------------------------------------------------*/
\r
1450 PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();
\r
1451 /* Get the QSPI clock source -----------------------------------------------*/
\r
1452 PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
\r
1455 /* Get the DSI clock source ------------------------------------------------*/
\r
1456 PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
\r
1459 /* Get the CKPER clock source ----------------------------------------------*/
\r
1460 PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
\r
1462 /* Get the TIM Prescaler configuration -------------------------------------*/
\r
1463 if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
\r
1465 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
\r
1469 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
\r
1474 * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
\r
1475 * @note Return 0 if peripheral clock identifier not managed by this API
\r
1476 * @param PeriphClk: Peripheral clock identifier
\r
1477 * This parameter can be one of the following values:
\r
1478 * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock
\r
1479 * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock
\r
1480 * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock
\r
1481 * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock
\r
1482 * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
\r
1483 * @retval Frequency in KHz
\r
1485 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
\r
1487 PLL1_ClocksTypeDef pll1_clocks;
\r
1488 PLL2_ClocksTypeDef pll2_clocks;
\r
1489 PLL3_ClocksTypeDef pll3_clocks;
\r
1491 /* This variable is used to store the SAI clock frequency (value in Hz) */
\r
1492 uint32_t frequency;
\r
1493 /* This variable is used to store the SAI and CKP clock source */
\r
1494 uint32_t saiclocksource;
\r
1495 uint32_t ckpclocksource;
\r
1498 if (PeriphClk == RCC_PERIPHCLK_SAI1)
\r
1501 saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
\r
1503 switch (saiclocksource)
\r
1505 case 0: /* PLL1 is the clock source for SAI1 */
\r
1507 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
\r
1508 frequency = pll1_clocks.PLL1_Q_Frequency;
\r
1511 case RCC_D2CCIP1R_SAI1SEL_0: /* PLLI2 is the clock source for SAI1 */
\r
1513 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
\r
1514 frequency = pll2_clocks.PLL2_P_Frequency;
\r
1518 case RCC_D2CCIP1R_SAI1SEL_1: /* PLLI3 is the clock source for SAI1 */
\r
1520 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
\r
1521 frequency = pll3_clocks.PLL3_P_Frequency;
\r
1525 case RCC_D2CCIP1R_SAI1SEL_2: /* CKPER is the clock source for SAI1*/
\r
1528 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
\r
1530 if(ckpclocksource== 0U)
\r
1532 /* In Case the CKPER Source is HSI */
\r
1533 frequency = HSI_VALUE;
\r
1536 else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
\r
1538 /* In Case the CKPER Source is CSI */
\r
1539 frequency = CSI_VALUE;
\r
1542 else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
\r
1544 /* In Case the CKPER Source is HSE */
\r
1545 frequency = HSE_VALUE;
\r
1550 /* In Case the CKPER is disabled*/
\r
1557 case (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1 ): /* External clock is the clock source for SAI1 */
\r
1559 frequency = EXTERNAL_CLOCK_VALUE;
\r
1570 else if (PeriphClk == RCC_PERIPHCLK_SAI23)
\r
1573 saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
\r
1575 switch (saiclocksource)
\r
1577 case 0: /* PLL1 is the clock source for SAI2/3 */
\r
1579 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
\r
1580 frequency = pll1_clocks.PLL1_Q_Frequency;
\r
1583 case RCC_D2CCIP1R_SAI23SEL_0: /* PLLI2 is the clock source for SAI2/3 */
\r
1585 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
\r
1586 frequency = pll2_clocks.PLL2_P_Frequency;
\r
1590 case RCC_D2CCIP1R_SAI23SEL_1: /* PLLI3 is the clock source for SAI2/3 */
\r
1592 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
\r
1593 frequency = pll3_clocks.PLL3_P_Frequency;
\r
1597 case RCC_D2CCIP1R_SAI23SEL_2: /* CKPER is the clock source for SAI2/3 */
\r
1600 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
\r
1602 if(ckpclocksource== 0U)
\r
1604 /* In Case the CKPER Source is HSI */
\r
1605 frequency = HSI_VALUE;
\r
1608 else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
\r
1610 /* In Case the CKPER Source is CSI */
\r
1611 frequency = CSI_VALUE;
\r
1614 else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
\r
1616 /* In Case the CKPER Source is HSE */
\r
1617 frequency = HSE_VALUE;
\r
1622 /* In Case the CKPER is disabled*/
\r
1629 case (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1 ): /* External clock is the clock source for SAI2/3 */
\r
1631 frequency = EXTERNAL_CLOCK_VALUE;
\r
1642 else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
\r
1645 saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
\r
1647 switch (saiclocksource)
\r
1649 case 0: /* PLL1 is the clock source for SAI4A */
\r
1651 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
\r
1652 frequency = pll1_clocks.PLL1_Q_Frequency;
\r
1655 case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */
\r
1657 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
\r
1658 frequency = pll2_clocks.PLL2_P_Frequency;
\r
1662 case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */
\r
1664 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
\r
1665 frequency = pll3_clocks.PLL3_P_Frequency;
\r
1669 case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/
\r
1672 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
\r
1674 if(ckpclocksource== 0U)
\r
1676 /* In Case the CKPER Source is HSI */
\r
1677 frequency = HSI_VALUE;
\r
1680 else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
\r
1682 /* In Case the CKPER Source is CSI */
\r
1683 frequency = CSI_VALUE;
\r
1686 else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
\r
1688 /* In Case the CKPER Source is HSE */
\r
1689 frequency = HSE_VALUE;
\r
1694 /* In Case the CKPER is disabled*/
\r
1701 case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */
\r
1703 frequency = EXTERNAL_CLOCK_VALUE;
\r
1715 else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
\r
1718 saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
\r
1720 switch (saiclocksource)
\r
1722 case 0: /* PLL1 is the clock source for SAI4B */
\r
1724 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
\r
1725 frequency = pll1_clocks.PLL1_Q_Frequency;
\r
1728 case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */
\r
1730 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
\r
1731 frequency = pll2_clocks.PLL2_P_Frequency;
\r
1735 case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */
\r
1737 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
\r
1738 frequency = pll3_clocks.PLL3_P_Frequency;
\r
1742 case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/
\r
1745 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
\r
1747 if(ckpclocksource== 0U)
\r
1749 /* In Case the CKPER Source is HSI */
\r
1750 frequency = HSI_VALUE;
\r
1753 else if(ckpclocksource== RCC_D1CCIPR_CKPERSEL_0)
\r
1755 /* In Case the CKPER Source is CSI */
\r
1756 frequency = CSI_VALUE;
\r
1759 else if (ckpclocksource== RCC_D1CCIPR_CKPERSEL_1)
\r
1761 /* In Case the CKPER Source is HSE */
\r
1762 frequency = HSE_VALUE;
\r
1767 /* In Case the CKPER is disabled*/
\r
1774 case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */
\r
1776 frequency = EXTERNAL_CLOCK_VALUE;
\r
1788 else if (PeriphClk == RCC_PERIPHCLK_SPI123)
\r
1790 /* Get SPI1/2/3 clock source */
\r
1791 srcclk= __HAL_RCC_GET_SPI123_SOURCE();
\r
1795 case 0: /* PLL1 is the clock source for I2S */
\r
1797 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
\r
1798 frequency = pll1_clocks.PLL1_Q_Frequency;
\r
1801 case RCC_D2CCIP1R_SPI123SEL_0: /* PLL2 is the clock source for I2S */
\r
1803 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
\r
1804 frequency = pll2_clocks.PLL2_P_Frequency;
\r
1808 case RCC_D2CCIP1R_SPI123SEL_1: /* PLL3 is the clock source for I2S */
\r
1810 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
\r
1811 frequency = pll3_clocks.PLL3_P_Frequency;
\r
1815 case RCC_D2CCIP1R_SPI123SEL_2: /* CKPER is the clock source for I2S */
\r
1818 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
\r
1820 if(ckpclocksource== RCC_CLKPSOURCE_HSI)
\r
1822 /* In Case the CKPER Source is HSI */
\r
1823 frequency = HSI_VALUE;
\r
1826 else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
\r
1828 /* In Case the CKPER Source is CSI */
\r
1829 frequency = CSI_VALUE;
\r
1832 else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
\r
1834 /* In Case the CKPER Source is HSE */
\r
1835 frequency = HSE_VALUE;
\r
1840 /* In Case the CKPER is disabled*/
\r
1847 case (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1): /* External clock is the clock source for I2S */
\r
1849 frequency = EXTERNAL_CLOCK_VALUE;
\r
1859 else if (PeriphClk == RCC_PERIPHCLK_ADC)
\r
1861 /* Get ADC clock source */
\r
1862 srcclk= __HAL_RCC_GET_ADC_SOURCE();
\r
1866 case RCC_ADCCLKSOURCE_PLL2:
\r
1868 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
\r
1869 frequency = pll2_clocks.PLL2_P_Frequency;
\r
1872 case RCC_ADCCLKSOURCE_PLL3:
\r
1874 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
\r
1875 frequency = pll3_clocks.PLL3_R_Frequency;
\r
1879 case RCC_ADCCLKSOURCE_CLKP:
\r
1882 ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
\r
1884 if(ckpclocksource== RCC_CLKPSOURCE_HSI)
\r
1886 /* In Case the CKPER Source is HSI */
\r
1887 frequency = HSI_VALUE;
\r
1890 else if(ckpclocksource== RCC_CLKPSOURCE_CSI)
\r
1892 /* In Case the CKPER Source is CSI */
\r
1893 frequency = CSI_VALUE;
\r
1896 else if (ckpclocksource== RCC_CLKPSOURCE_HSE)
\r
1898 /* In Case the CKPER Source is HSE */
\r
1899 frequency = HSE_VALUE;
\r
1904 /* In Case the CKPER is disabled*/
\r
1928 * @brief Returns the D1PCLK1 frequency
\r
1929 * @note Each time D1PCLK1 changes, this function must be called to update the
\r
1930 * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
\r
1931 * @retval D1PCLK1 frequency
\r
1933 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
\r
1935 /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
\r
1936 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
\r
1940 * @brief Returns the D3PCLK1 frequency
\r
1941 * @note Each time D3PCLK1 changes, this function must be called to update the
\r
1942 * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
\r
1943 * @retval D3PCLK1 frequency
\r
1945 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
\r
1947 /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
\r
1948 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
\r
1951 * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
\r
1952 * @note The PLL2 clock frequencies computed by this function is not the real
\r
1953 * frequency in the chip. It is calculated based on the predefined
\r
1954 * constant and the selected clock source:
\r
1955 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
\r
1956 * @note This function can be used by the user application to compute the
\r
1957 * baud-rate for the communication peripherals or configure other parameters.
\r
1959 * @note Each time PLL2CLK changes, this function must be called to update the
\r
1960 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
\r
1961 * @param PLL2_Clocks structure.
\r
1964 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
\r
1966 uint32_t pllsource, pll2m, pll2fracen, hsivalue;
\r
1967 float_t fracn2, pll2vco;
\r
1969 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
\r
1970 PLL2xCLK = PLL2_VCO / PLL2x
\r
1972 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
\r
1973 pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12) ;
\r
1974 pll2fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN;
\r
1975 fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
\r
1979 switch (pllsource)
\r
1982 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
\r
1984 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
\r
1986 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
\r
1987 pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
\r
1991 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
\r
1995 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
\r
1996 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
\r
1999 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
\r
2000 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
\r
2004 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
\r
2007 PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9) + (float_t)1 )) ;
\r
2008 PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ;
\r
2009 PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ;
\r
2013 PLL2_Clocks->PLL2_P_Frequency = 0U;
\r
2014 PLL2_Clocks->PLL2_Q_Frequency = 0U;
\r
2015 PLL2_Clocks->PLL2_R_Frequency = 0U;
\r
2020 * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
\r
2021 * @note The PLL3 clock frequencies computed by this function is not the real
\r
2022 * frequency in the chip. It is calculated based on the predefined
\r
2023 * constant and the selected clock source:
\r
2024 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
\r
2025 * @note This function can be used by the user application to compute the
\r
2026 * baud-rate for the communication peripherals or configure other parameters.
\r
2028 * @note Each time PLL3CLK changes, this function must be called to update the
\r
2029 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
\r
2030 * @param PLL3_Clocks structure.
\r
2033 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
\r
2035 uint32_t pllsource, pll3m, pll3fracen, hsivalue;
\r
2036 float_t fracn3, pll3vco;
\r
2038 /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
\r
2039 PLL3xCLK = PLL3_VCO / PLLxR
\r
2041 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
\r
2042 pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ;
\r
2043 pll3fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN;
\r
2044 fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
\r
2048 switch (pllsource)
\r
2050 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
\r
2052 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
\r
2054 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
\r
2055 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
\r
2059 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
\r
2062 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
\r
2063 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
\r
2066 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
\r
2067 pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
\r
2071 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
\r
2074 PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9) + (float_t)1 )) ;
\r
2075 PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ;
\r
2076 PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ;
\r
2080 PLL3_Clocks->PLL3_P_Frequency = 0U;
\r
2081 PLL3_Clocks->PLL3_Q_Frequency = 0U;
\r
2082 PLL3_Clocks->PLL3_R_Frequency = 0U;
\r
2088 * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
\r
2089 * @note The PLL1 clock frequencies computed by this function is not the real
\r
2090 * frequency in the chip. It is calculated based on the predefined
\r
2091 * constant and the selected clock source:
\r
2092 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
\r
2093 * @note This function can be used by the user application to compute the
\r
2094 * baud-rate for the communication peripherals or configure other parameters.
\r
2096 * @note Each time PLL1CLK changes, this function must be called to update the
\r
2097 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
\r
2098 * @param PLL1_Clocks structure.
\r
2101 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
\r
2103 uint32_t pllsource, pll1m, pll1fracen, hsivalue;
\r
2104 float_t fracn1, pll1vco;
\r
2106 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
\r
2107 pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
\r
2108 pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
\r
2109 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
\r
2113 switch (pllsource)
\r
2116 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
\r
2118 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
\r
2120 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
\r
2121 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
\r
2125 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
\r
2128 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
\r
2129 pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
\r
2132 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
\r
2133 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
\r
2137 pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
\r
2141 PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + (float_t)1 )) ;
\r
2142 PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ;
\r
2143 PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ;
\r
2147 PLL1_Clocks->PLL1_P_Frequency = 0U;
\r
2148 PLL1_Clocks->PLL1_Q_Frequency = 0U;
\r
2149 PLL1_Clocks->PLL1_R_Frequency = 0U;
\r
2155 * @brief Returns the main Core frequency
\r
2156 * @note Each time core clock changes, this function must be called to update the
\r
2157 * right system core clock value. Otherwise, any configuration based on this function will be incorrect.
\r
2158 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
\r
2159 * and updated within this function
\r
2160 * @retval HCLK frequency
\r
2162 uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
\r
2164 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
\r
2165 return SystemCoreClock;
\r
2169 * @brief Enables the LSE Clock Security System.
\r
2170 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
\r
2171 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
\r
2172 * clock with HAL_RCCEx_PeriphCLKConfig().
\r
2175 void HAL_RCCEx_EnableLSECSS(void)
\r
2177 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
\r
2181 * @brief Disables the LSE Clock Security System.
\r
2182 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
\r
2185 void HAL_RCCEx_DisableLSECSS(void)
\r
2187 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
\r
2188 /* Disable LSE CSS IT if any */
\r
2189 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
\r
2193 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock
\r
2194 * @param WakeUpClk: Wakeup clock
\r
2195 * This parameter can be one of the following values:
\r
2196 * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
\r
2197 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
\r
2198 * @note This function shall not be called after the Clock Security System on HSE has been
\r
2202 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
\r
2204 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
\r
2206 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
\r
2210 * @brief Configure the oscillator Kernel clock source for wakeup from Stop
\r
2211 * @param WakeUpClk: Kernel Wakeup clock
\r
2212 * This parameter can be one of the following values:
\r
2213 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
\r
2214 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
\r
2217 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
\r
2219 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
\r
2221 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
\r
2224 #if defined(DUAL_CORE)
\r
2226 * @brief Enable COREx boot independently of CMx_B option byte value
\r
2227 * @param RCC_BootCx: Boot Core to be enabled
\r
2228 * This parameter can be one of the following values:
\r
2229 * @arg RCC_BOOT_C1: CM7 core selection
\r
2230 * @arg RCC_BOOT_C2: CM4 core selection
\r
2231 * @note This bit can be set by software but is cleared by hardware after a system reset or STANDBY
\r
2235 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
\r
2237 assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
\r
2238 SET_BIT(RCC->GCR, RCC_BootCx) ;
\r
2241 #endif /*DUAL_CORE*/
\r
2243 #if defined(DUAL_CORE)
\r
2245 * @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs
\r
2246 * @param RCC_WWDGx: WWDGx to be configured
\r
2247 * This parameter can be one of the following values:
\r
2248 * @arg RCC_WWDG1: WWDG1 generates system reset
\r
2249 * @arg RCC_WWDG2: WWDG2 generates system reset
\r
2250 * @note This bit can be set by software but is cleared by hardware during a system reset
\r
2254 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
\r
2256 assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
\r
2257 SET_BIT(RCC->GCR, RCC_WWDGx) ;
\r
2263 * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
\r
2264 * @param RCC_WWDGx: WWDGx to be configured
\r
2265 * This parameter can be one of the following values:
\r
2266 * @arg RCC_WWDG1: WWDG1 generates system reset
\r
2267 * @note This bit can be set by software but is cleared by hardware during a system reset
\r
2271 void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
\r
2273 assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
\r
2274 SET_BIT(RCC->GCR, RCC_WWDGx) ;
\r
2277 #endif /*DUAL_CORE*/
\r
2280 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
\r
2281 * @brief Extended Clock Recovery System Control functions
\r
2284 ===============================================================================
\r
2285 ##### Extended Clock Recovery System Control functions #####
\r
2286 ===============================================================================
\r
2288 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
\r
2290 (#) In System clock config, HSI48 needs to be enabled
\r
2292 (#) Enable CRS clock in IP MSP init which will use CRS functions
\r
2294 (#) Call CRS functions as follows:
\r
2295 (##) Prepare synchronization configuration necessary for HSI48 calibration
\r
2296 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
\r
2297 and also HSI48 oscillator smooth trimming.
\r
2298 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
\r
2299 directly reload value with target and synchronization frequencies values
\r
2300 (##) Call function HAL_RCCEx_CRSConfig which
\r
2301 (+++) Resets CRS registers to their default values.
\r
2302 (+++) Configures CRS registers with synchronization configuration
\r
2303 (+++) Enables automatic calibration and frequency error counter feature
\r
2304 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
\r
2305 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
\r
2306 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
\r
2307 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
\r
2308 should be used as SYNC signal.
\r
2310 (##) A polling function is provided to wait for complete synchronization
\r
2311 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
\r
2312 (+++) According to CRS status, user can decide to adjust again the calibration or continue
\r
2313 application if synchronization is OK
\r
2315 (#) User can retrieve information related to synchronization in calling function
\r
2316 HAL_RCCEx_CRSGetSynchronizationInfo()
\r
2318 (#) Regarding synchronization status and synchronization information, user can try a new calibration
\r
2319 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
\r
2320 Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
\r
2321 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
\r
2322 incremented), while when it is detected during the up-counting phase it means that the actual frequency
\r
2323 is higher (and that the TRIM value should be decremented).
\r
2325 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
\r
2326 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
\r
2327 (++) Call function HAL_RCCEx_CRSConfig()
\r
2328 (++) Enable CRS_IRQn (thanks to NVIC functions)
\r
2329 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
\r
2330 (++) Implement CRS status management in the following user callbacks called from
\r
2331 HAL_RCCEx_CRS_IRQHandler():
\r
2332 (+++) HAL_RCCEx_CRS_SyncOkCallback()
\r
2333 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
\r
2334 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
\r
2335 (+++) HAL_RCCEx_CRS_ErrorCallback()
\r
2337 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
\r
2338 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
\r
2345 * @brief Start automatic synchronization for polling mode
\r
2346 * @param pInit Pointer on RCC_CRSInitTypeDef structure
\r
2349 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
\r
2353 /* Check the parameters */
\r
2354 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
\r
2355 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
\r
2356 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
\r
2357 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
\r
2358 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
\r
2359 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
\r
2361 /* CONFIGURATION */
\r
2363 /* Before configuration, reset CRS registers to their default values*/
\r
2364 __HAL_RCC_CRS_FORCE_RESET();
\r
2365 __HAL_RCC_CRS_RELEASE_RESET();
\r
2367 /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
\r
2368 /* Set the SYNCSRC[1:0] bits according to Source value */
\r
2369 /* Set the SYNCSPOL bit according to Polarity value */
\r
2370 if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
\r
2372 /* Use Rev.Y value of USB2 */
\r
2373 value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
\r
2377 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
\r
2379 /* Set the RELOAD[15:0] bits according to ReloadValue value */
\r
2380 value |= pInit->ReloadValue;
\r
2381 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
\r
2382 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
\r
2383 WRITE_REG(CRS->CFGR, value);
\r
2385 /* Adjust HSI48 oscillator smooth trimming */
\r
2386 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
\r
2387 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
\r
2389 /* START AUTOMATIC SYNCHRONIZATION*/
\r
2391 /* Enable Automatic trimming & Frequency error counter */
\r
2392 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
\r
2396 * @brief Generate the software synchronization event
\r
2399 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
\r
2401 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
\r
2405 * @brief Return synchronization info
\r
2406 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
\r
2409 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
\r
2411 /* Check the parameter */
\r
2412 assert_param(pSynchroInfo != (void *)NULL);
\r
2414 /* Get the reload value */
\r
2415 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
\r
2417 /* Get HSI48 oscillator smooth trimming */
\r
2418 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
\r
2420 /* Get Frequency error capture */
\r
2421 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
\r
2423 /* Get Frequency error direction */
\r
2424 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
\r
2428 * @brief Wait for CRS Synchronization status.
\r
2429 * @param Timeout Duration of the time-out
\r
2430 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
\r
2432 * @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
\r
2433 * @retval Combination of Synchronization status
\r
2434 * This parameter can be a combination of the following values:
\r
2435 * @arg @ref RCC_CRS_TIMEOUT
\r
2436 * @arg @ref RCC_CRS_SYNCOK
\r
2437 * @arg @ref RCC_CRS_SYNCWARN
\r
2438 * @arg @ref RCC_CRS_SYNCERR
\r
2439 * @arg @ref RCC_CRS_SYNCMISS
\r
2440 * @arg @ref RCC_CRS_TRIMOVF
\r
2442 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
\r
2444 uint32_t crsstatus = RCC_CRS_NONE;
\r
2445 uint32_t tickstart;
\r
2447 /* Get time-out */
\r
2448 tickstart = HAL_GetTick();
\r
2450 /* Wait for CRS flag or time-out detection */
\r
2453 if(Timeout != HAL_MAX_DELAY)
\r
2455 if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
\r
2457 crsstatus = RCC_CRS_TIMEOUT;
\r
2460 /* Check CRS SYNCOK flag */
\r
2461 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
\r
2463 /* CRS SYNC event OK */
\r
2464 crsstatus |= RCC_CRS_SYNCOK;
\r
2466 /* Clear CRS SYNC event OK bit */
\r
2467 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
\r
2470 /* Check CRS SYNCWARN flag */
\r
2471 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
\r
2473 /* CRS SYNC warning */
\r
2474 crsstatus |= RCC_CRS_SYNCWARN;
\r
2476 /* Clear CRS SYNCWARN bit */
\r
2477 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
\r
2480 /* Check CRS TRIM overflow flag */
\r
2481 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
\r
2483 /* CRS SYNC Error */
\r
2484 crsstatus |= RCC_CRS_TRIMOVF;
\r
2486 /* Clear CRS Error bit */
\r
2487 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
\r
2490 /* Check CRS Error flag */
\r
2491 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
\r
2493 /* CRS SYNC Error */
\r
2494 crsstatus |= RCC_CRS_SYNCERR;
\r
2496 /* Clear CRS Error bit */
\r
2497 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
\r
2500 /* Check CRS SYNC Missed flag */
\r
2501 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
\r
2503 /* CRS SYNC Missed */
\r
2504 crsstatus |= RCC_CRS_SYNCMISS;
\r
2506 /* Clear CRS SYNC Missed bit */
\r
2507 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
\r
2510 /* Check CRS Expected SYNC flag */
\r
2511 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
\r
2513 /* frequency error counter reached a zero value */
\r
2514 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
\r
2516 } while(RCC_CRS_NONE == crsstatus);
\r
2522 * @brief Handle the Clock Recovery System interrupt request.
\r
2525 void HAL_RCCEx_CRS_IRQHandler(void)
\r
2527 uint32_t crserror = RCC_CRS_NONE;
\r
2528 /* Get current IT flags and IT sources values */
\r
2529 uint32_t itflags = READ_REG(CRS->ISR);
\r
2530 uint32_t itsources = READ_REG(CRS->CR);
\r
2532 /* Check CRS SYNCOK flag */
\r
2533 if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
\r
2535 /* Clear CRS SYNC event OK flag */
\r
2536 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
\r
2538 /* user callback */
\r
2539 HAL_RCCEx_CRS_SyncOkCallback();
\r
2541 /* Check CRS SYNCWARN flag */
\r
2542 else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
\r
2544 /* Clear CRS SYNCWARN flag */
\r
2545 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
\r
2547 /* user callback */
\r
2548 HAL_RCCEx_CRS_SyncWarnCallback();
\r
2550 /* Check CRS Expected SYNC flag */
\r
2551 else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
\r
2553 /* frequency error counter reached a zero value */
\r
2554 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
\r
2556 /* user callback */
\r
2557 HAL_RCCEx_CRS_ExpectedSyncCallback();
\r
2559 /* Check CRS Error flags */
\r
2562 if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
\r
2564 if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
\r
2566 crserror |= RCC_CRS_SYNCERR;
\r
2568 if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
\r
2570 crserror |= RCC_CRS_SYNCMISS;
\r
2572 if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
\r
2574 crserror |= RCC_CRS_TRIMOVF;
\r
2577 /* Clear CRS Error flags */
\r
2578 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
\r
2580 /* user error callback */
\r
2581 HAL_RCCEx_CRS_ErrorCallback(crserror);
\r
2587 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
\r
2590 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
\r
2592 /* NOTE : This function should not be modified, when the callback is needed,
\r
2593 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
\r
2598 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
\r
2601 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
\r
2603 /* NOTE : This function should not be modified, when the callback is needed,
\r
2604 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
\r
2609 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
\r
2612 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
\r
2614 /* NOTE : This function should not be modified, when the callback is needed,
\r
2615 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
\r
2620 * @brief RCCEx Clock Recovery System Error interrupt callback.
\r
2621 * @param Error Combination of Error status.
\r
2622 * This parameter can be a combination of the following values:
\r
2623 * @arg @ref RCC_CRS_SYNCERR
\r
2624 * @arg @ref RCC_CRS_SYNCMISS
\r
2625 * @arg @ref RCC_CRS_TRIMOVF
\r
2628 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
\r
2630 /* Prevent unused argument(s) compilation warning */
\r
2633 /* NOTE : This function should not be modified, when the callback is needed,
\r
2634 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
\r
2647 /** @defgroup RCCEx_Private_functions Private Functions
\r
2654 * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
\r
2655 * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that
\r
2656 * contains the configuration parameters as well as VCI, VCO clock ranges.
\r
2657 * @param Divider divider parameter to be updated
\r
2658 * @note PLL2 is temporary disable to apply new parameters
\r
2660 * @retval HAL status
\r
2662 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
\r
2665 uint32_t tickstart;
\r
2666 HAL_StatusTypeDef status = HAL_OK;
\r
2667 assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
\r
2668 assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
\r
2669 assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
\r
2670 assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
\r
2671 assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
\r
2672 assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
\r
2673 assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
\r
2674 assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
\r
2676 /* Check that PLL2 OSC clock source is already set */
\r
2677 if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
\r
2685 /* Disable PLL2. */
\r
2686 __HAL_RCC_PLL2_DISABLE();
\r
2688 /* Get Start Tick*/
\r
2689 tickstart = HAL_GetTick();
\r
2691 /* Wait till PLL is ready */
\r
2692 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
\r
2694 if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
\r
2696 return HAL_TIMEOUT;
\r
2700 /* Configure PLL2 multiplication and division factors. */
\r
2701 __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
\r
2707 /* Select PLL2 input reference frequency range: VCI */
\r
2708 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
\r
2710 /* Select PLL2 output frequency range : VCO */
\r
2711 __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
\r
2713 /* Disable PLL2FRACN . */
\r
2714 __HAL_RCC_PLL2FRACN_DISABLE();
\r
2716 /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
\r
2717 __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
\r
2719 /* Enable PLL2FRACN . */
\r
2720 __HAL_RCC_PLL2FRACN_ENABLE();
\r
2722 /* Enable the PLL2 clock output */
\r
2723 if(Divider == DIVIDER_P_UPDATE)
\r
2725 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
\r
2727 else if(Divider == DIVIDER_Q_UPDATE)
\r
2729 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
\r
2733 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
\r
2736 /* Enable PLL2. */
\r
2737 __HAL_RCC_PLL2_ENABLE();
\r
2739 /* Get Start Tick*/
\r
2740 tickstart = HAL_GetTick();
\r
2742 /* Wait till PLL2 is ready */
\r
2743 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
\r
2745 if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
\r
2747 return HAL_TIMEOUT;
\r
2759 * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
\r
2760 * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that
\r
2761 * contains the configuration parameters as well as VCI, VCO clock ranges.
\r
2762 * @param Divider divider parameter to be updated
\r
2763 * @note PLL3 is temporary disable to apply new parameters
\r
2765 * @retval HAL status
\r
2767 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
\r
2769 uint32_t tickstart;
\r
2770 HAL_StatusTypeDef status = HAL_OK;
\r
2771 assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
\r
2772 assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
\r
2773 assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
\r
2774 assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
\r
2775 assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
\r
2776 assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
\r
2777 assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
\r
2778 assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
\r
2780 /* Check that PLL3 OSC clock source is already set */
\r
2781 if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
\r
2789 /* Disable PLL3. */
\r
2790 __HAL_RCC_PLL3_DISABLE();
\r
2792 /* Get Start Tick*/
\r
2793 tickstart = HAL_GetTick();
\r
2794 /* Wait till PLL3 is ready */
\r
2795 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
\r
2797 if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
\r
2799 return HAL_TIMEOUT;
\r
2803 /* Configure the PLL3 multiplication and division factors. */
\r
2804 __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
\r
2810 /* Select PLL3 input reference frequency range: VCI */
\r
2811 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
\r
2813 /* Select PLL3 output frequency range : VCO */
\r
2814 __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
\r
2816 /* Disable PLL3FRACN . */
\r
2817 __HAL_RCC_PLL3FRACN_DISABLE();
\r
2819 /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
\r
2820 __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
\r
2822 /* Enable PLL3FRACN . */
\r
2823 __HAL_RCC_PLL3FRACN_ENABLE();
\r
2825 /* Enable the PLL3 clock output */
\r
2826 if(Divider == DIVIDER_P_UPDATE)
\r
2828 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
\r
2830 else if(Divider == DIVIDER_Q_UPDATE)
\r
2832 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
\r
2836 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
\r
2839 /* Enable PLL3. */
\r
2840 __HAL_RCC_PLL3_ENABLE();
\r
2842 /* Get Start Tick*/
\r
2843 tickstart = HAL_GetTick();
\r
2845 /* Wait till PLL3 is ready */
\r
2846 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
\r
2848 if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
\r
2850 return HAL_TIMEOUT;
\r
2871 #endif /* HAL_RCC_MODULE_ENABLED */
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2880 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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