1 /******************************************************************************
3 * @brief CMSIS MPU API for ARMv7 MPU
6 ******************************************************************************/
8 * Copyright (c) 2017 ARM Limited. All rights reserved.
10 * SPDX-License-Identifier: Apache-2.0
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
16 * www.apache.org/licenses/LICENSE-2.0
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
25 #ifndef ARM_MPU_ARMV7_H
26 #define ARM_MPU_ARMV7_H
28 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
29 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
30 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
31 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
32 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
33 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
34 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
35 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
36 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
37 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
38 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
39 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
40 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
41 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
42 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
43 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
44 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
45 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
46 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
47 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
48 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
49 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
50 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
51 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
52 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
53 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
54 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
55 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
57 #define ARM_MPU_AP_NONE 0u
58 #define ARM_MPU_AP_PRIV 1u
59 #define ARM_MPU_AP_URO 2u
60 #define ARM_MPU_AP_FULL 3u
61 #define ARM_MPU_AP_PRO 5u
62 #define ARM_MPU_AP_RO 6u
64 /** MPU Region Base Address Register Value
66 * \param Region The region to be configured, number 0 to 15.
67 * \param BaseAddress The base address for the region.
69 #define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
72 * MPU Region Attribut and Size Register Value
74 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
75 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
76 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
77 * \param IsShareable Region is shareable between multiple bus masters.
78 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
79 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
80 * \param SubRegionDisable Sub-region disable field.
81 * \param Size Region size of the region to be configured, for example 4K, 8K.
83 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
84 ((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
85 ((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
86 ((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
87 ((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
88 ((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
89 ((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
90 ((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
91 ((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
92 ((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
96 * Struct for a single MPU Region
98 typedef struct _ARM_MPU_Region_t {
99 uint32_t RBAR; //!< The region base address register value (RBAR)
100 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
104 * \param MPU_Control Default access permissions for unconfigured regions.
106 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
110 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
111 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
112 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
118 __STATIC_INLINE void ARM_MPU_Disable()
122 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
123 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
125 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
128 /** Clear and disable the given MPU region.
129 * \param rnr Region number to be cleared.
131 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
137 /** Configure an MPU region.
138 * \param rbar Value for RBAR register.
139 * \param rsar Value for RSAR register.
141 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
147 /** Configure the given MPU region.
148 * \param rnr Region number to be configured.
149 * \param rbar Value for RBAR register.
150 * \param rsar Value for RSAR register.
152 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
159 /** Memcopy with strictly ordered memory access, e.g. for register targets.
160 * \param dst Destination data is copied to.
161 * \param src Source data is copied from.
162 * \param len Amount of data words to be copied.
164 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
167 for (i = 0u; i < len; ++i)
173 /** Load the given number of MPU regions from a table.
174 * \param table Pointer to the MPU configuration table.
175 * \param cnt Amount of regions to be configured.
177 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
179 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);