1 /**************************************************************************//**
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4 * @brief CAN register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __CAN_REG_H__
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9 #define __CAN_REG_H__
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11 /** @addtogroup REGISTER Control Register
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18 /*---------------------- Controller Area Network Controller -------------------------*/
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20 @addtogroup CAN Controller Area Network Controller(CAN)
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21 Memory Mapped Structure for CAN Controller
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31 * @var CAN_IF_T::CREQ
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32 * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
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33 * ---------------------------------------------------------------------------------------------------
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34 * |Bits |Field |Descriptions
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35 * | :----: | :----: | :---- |
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36 * |[5:0] |MessageNumber|Message Number
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37 * | | |0x01-0x20: Valid Message Number, the Message Object in the Message
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38 * | | |RAM is selected for data transfer.
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39 * | | |0x00: Not a valid Message Number, interpreted as 0x20.
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40 * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
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41 * |[15] |Busy |Busy Flag
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42 * | | |0 = Read/write action has finished.
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43 * | | |1 = Writing to the IFn Command Request Register is in progress.
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44 * | | |This bit can only be read by the software.
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45 * @var CAN_IF_T::CMASK
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46 * Offset: 0x24, 0x84 IFn Command Mask Register
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47 * ---------------------------------------------------------------------------------------------------
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48 * |Bits |Field |Descriptions
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49 * | :----: | :----: | :---- |
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50 * |[0] |DAT_B |Access Data Bytes [7:4]
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51 * | | |Write Operation:
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52 * | | |0 = Data Bytes [7:4] unchanged.
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53 * | | |1 = Transfer Data Bytes [7:4] to Message Object.
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54 * | | |Read Operation:
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55 * | | |0 = Data Bytes [7:4] unchanged.
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56 * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
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57 * |[1] |DAT_A |Access Data Bytes [3:0]
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58 * | | |Write Operation:
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59 * | | |0 = Data Bytes [3:0] unchanged.
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60 * | | |1 = Transfer Data Bytes [3:0] to Message Object.
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61 * | | |Read Operation:
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62 * | | |0 = Data Bytes [3:0] unchanged.
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63 * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
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64 * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
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65 * | | |0 = TxRqst bit unchanged.
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66 * | | |1 = Set TxRqst bit.
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67 * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
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68 * | | |Access New Data Bit when Read Operation.
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69 * | | |0 = NewDat bit remains unchanged.
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70 * | | |1 = Clear NewDat bit in the Message Object.
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71 * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
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72 * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
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73 * |[3] |ClrIntPnd |Clear Interrupt Pending Bit
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74 * | | |Write Operation:
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75 * | | |When writing to a Message Object, this bit is ignored.
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76 * | | |Read Operation:
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77 * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
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78 * | | |1 = Clear IntPnd bit in the Message Object.
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79 * |[4] |Control |Control Access Control Bits
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80 * | | |Write Operation:
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81 * | | |0 = Control Bits unchanged.
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82 * | | |1 = Transfer Control Bits to Message Object.
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83 * | | |Read Operation:
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84 * | | |0 = Control Bits unchanged.
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85 * | | |1 = Transfer Control Bits to IFn Message Buffer Register.
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86 * |[5] |Arb |Access Arbitration Bits
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87 * | | |Write Operation:
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88 * | | |0 = Arbitration bits unchanged.
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89 * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
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90 * | | |Read Operation:
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91 * | | |0 = Arbitration bits unchanged.
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92 * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
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93 * |[6] |Mask |Access Mask Bits
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94 * | | |Write Operation:
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95 * | | |0 = Mask bits unchanged.
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96 * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
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97 * | | |Read Operation:
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98 * | | |0 = Mask bits unchanged.
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99 * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
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100 * |[7] |WR_RD |Write / Read Mode
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101 * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
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102 * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
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103 * @var CAN_IF_T::MASK1
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104 * Offset: 0x28, 0x88 IFn Mask 1 Register
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105 * ---------------------------------------------------------------------------------------------------
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106 * |Bits |Field |Descriptions
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107 * | :----: | :----: | :---- |
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108 * |[15:0] |Msk[15:0] |Identifier Mask 15-0
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109 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
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110 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
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111 * @var CAN_IF_T::MASK2
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112 * Offset: 0x2C, 0x8C IFn Mask 2 Register
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113 * ---------------------------------------------------------------------------------------------------
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114 * |Bits |Field |Descriptions
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115 * | :----: | :----: | :---- |
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116 * |[12:0] |Msk[28:16]|Identifier Mask 28-16
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117 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
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118 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
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119 * |[14] |MDir |Mask Message Direction
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120 * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
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121 * | | |1 = The message direction bit (Dir) is used for acceptance filtering.
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122 * |[15] |MXtd |Mask Extended Identifier
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123 * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
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124 * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
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125 * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
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126 * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
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127 * @var CAN_IF_T::ARB1
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128 * Offset: 0x30, 0x90 IFn Arbitration 1 Register
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129 * ---------------------------------------------------------------------------------------------------
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130 * |Bits |Field |Descriptions
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131 * | :----: | :----: | :---- |
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132 * |[15:0] |ID[15:0] |Message Identifier 15-0
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133 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
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134 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
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135 * @var CAN_IF_T::ARB2
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136 * Offset: 0x34, 0x94 IFn Arbitration 2 Register
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137 * ---------------------------------------------------------------------------------------------------
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138 * |Bits |Field |Descriptions
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139 * | :----: | :----: | :---- |
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140 * |[12:0] |ID[28:16] |Message Identifier 28-16
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141 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
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142 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
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143 * |[13] |Dir |Message Direction
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144 * | | |0 = Direction is receive.
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145 * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
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146 * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
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147 * | | |1 = Direction is transmit.
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148 * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
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149 * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
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150 * |[14] |Xtd |Extended Identifier
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151 * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
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152 * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
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153 * |[15] |MsgVal |Message Valid
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154 * | | |0 = The Message Object is ignored by the Message Handler.
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155 * | | |1 = The Message Object is configured and should be considered by the Message Handler.
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156 * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
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157 * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
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158 * @var CAN_IF_T::MCON
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159 * Offset: 0x38, 0x98 IFn Message Control Register
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160 * ---------------------------------------------------------------------------------------------------
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161 * |Bits |Field |Descriptions
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162 * | :----: | :----: | :---- |
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163 * |[3:0] |DLC |Data Length Code
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164 * | | |0-8: Data Frame has 0-8 data bytes.
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165 * | | |9-15: Data Frame has 8 data bytes
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166 * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
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167 * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
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168 * | | |Data 0: 1st data byte of a CAN Data Frame
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169 * | | |Data 1: 2nd data byte of a CAN Data Frame
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170 * | | |Data 2: 3rd data byte of a CAN Data Frame
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171 * | | |Data 3: 4th data byte of a CAN Data Frame
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172 * | | |Data 4: 5th data byte of a CAN Data Frame
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173 * | | |Data 5: 6th data byte of a CAN Data Frame
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174 * | | |Data 6: 7th data byte of a CAN Data Frame
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175 * | | |Data 7 : 8th data byte of a CAN Data Frame
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176 * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
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177 * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
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178 * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
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179 * |[7] |EoB |End Of Buffer
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180 * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
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181 * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
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182 * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
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183 * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
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184 * |[8] |TxRqst |Transmit Request
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185 * | | |0 = This Message Object is not waiting for transmission.
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186 * | | |1 = The transmission of this Message Object is requested and is not yet done.
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187 * |[9] |RmtEn |Remote Enable Control
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188 * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
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189 * | | |1 = At the reception of a Remote Frame, TxRqst is set.
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190 * |[10] |RxIE |Receive Interrupt Enable Control
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191 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
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192 * | | |1 = IntPnd will be set after a successful reception of a frame.
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193 * |[11] |TxIE |Transmit Interrupt Enable Control
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194 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
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195 * | | |1 = IntPnd will be set after a successful transmission of a frame.
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196 * |[12] |UMask |Use Acceptance Mask
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197 * | | |0 = Mask ignored.
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198 * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
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199 * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
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200 * |[13] |IntPnd |Interrupt Pending
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201 * | | |0 = This message object is not the source of an interrupt.
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202 * | | |1 = This message object is the source of an interrupt.
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203 * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
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204 * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
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205 * | | |0 = No message lost since last time this bit was reset by the CPU.
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206 * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
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207 * |[15] |NewDat |New Data
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208 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
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209 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
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210 * @var CAN_IF_T::DAT_A1
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211 * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
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212 * ---------------------------------------------------------------------------------------------------
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213 * |Bits |Field |Descriptions
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214 * | :----: | :----: | :---- |
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215 * |[7:0] |Data0 |Data Byte 0
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216 * | | |1st data byte of a CAN Data Frame
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217 * |[15:8] |Data1 |Data Byte 1
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218 * | | |2nd data byte of a CAN Data Frame
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219 * @var CAN_IF_T::DAT_A2
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220 * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
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221 * ---------------------------------------------------------------------------------------------------
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222 * |Bits |Field |Descriptions
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223 * | :----: | :----: | :---- |
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224 * |[7:0] |Data2 |Data Byte 2
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225 * | | |3rd data byte of CAN Data Frame
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226 * |[15:8] |Data3 |Data Byte 3
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227 * | | |4th data byte of CAN Data Frame
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228 * @var CAN_IF_T::DAT_B1
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229 * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
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230 * ---------------------------------------------------------------------------------------------------
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231 * |Bits |Field |Descriptions
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232 * | :----: | :----: | :---- |
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233 * |[7:0] |Data4 |Data Byte 4
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234 * | | |5th data byte of CAN Data Frame
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235 * |[15:8] |Data5 |Data Byte 5
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236 * | | |6th data byte of CAN Data Frame
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237 * @var CAN_IF_T::DAT_B2
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238 * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
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239 * ---------------------------------------------------------------------------------------------------
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240 * |Bits |Field |Descriptions
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241 * | :----: | :----: | :---- |
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242 * |[7:0] |Data6 |Data Byte 6
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243 * | | |7th data byte of CAN Data Frame.
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244 * |[15:8] |Data7 |Data Byte 7
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245 * | | |8th data byte of CAN Data Frame.
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248 __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */
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249 __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */
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250 __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */
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251 __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */
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252 __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */
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253 __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */
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254 __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */
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255 __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */
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256 __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */
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257 __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */
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258 __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */
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259 __I uint32_t RESERVE0[13];
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273 * Offset: 0x00 Control Register
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274 * ---------------------------------------------------------------------------------------------------
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275 * |Bits |Field |Descriptions
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276 * | :----: | :----: | :---- |
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277 * |[0] |Init |Init Initialization
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278 * | | |0 = Normal Operation.
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279 * | | |1 = Initialization is started.
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280 * |[1] |IE |Module Interrupt Enable Control
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281 * | | |0 = Disabled.
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282 * | | |1 = Enabled.
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283 * |[2] |SIE |Status Change Interrupt Enable Control
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284 * | | |0 = Disabled - No Status Change Interrupt will be generated.
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285 * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
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286 * |[3] |EIE |Error Interrupt Enable Control
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287 * | | |0 = Disabled - No Error Status Interrupt will be generated.
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288 * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
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289 * |[5] |DAR |Automatic Re-Transmission Disable Control
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290 * | | |0 = Automatic Retransmission of disturbed messages enabled.
\r
291 * | | |1 = Automatic Retransmission disabled.
\r
292 * |[6] |CCE |Configuration Change Enable Control
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293 * | | |0 = No write access to the Bit Timing Register.
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294 * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
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295 * |[7] |Test |Test Mode Enable Control
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296 * | | |0 = Normal Operation.
\r
297 * | | |1 = Test Mode.
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298 * @var CAN_T::STATUS
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299 * Offset: 0x04 Status Register
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300 * ---------------------------------------------------------------------------------------------------
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301 * |Bits |Field |Descriptions
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302 * | :----: | :----: | :---- |
\r
303 * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
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304 * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
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305 * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
\r
306 * | | |The unused code '7' may be written by the CPU to check for updates.
\r
307 * | | |The following table describes the error code.
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308 * |[3] |TxOK |Transmitted A Message Successfully
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309 * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
\r
310 * | | |This bit is never reset by the CAN Core.
\r
311 * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
\r
312 * |[4] |RxOK |Received A Message Successfully
\r
313 * | | |0 = No message has been successfully received since this bit was last reset by the CPU.
\r
314 * | | |This bit is never reset by the CAN Core.
\r
315 * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
\r
316 * |[5] |EPass |Error Passive (Read Only)
\r
317 * | | |0 = The CAN Core is error active.
\r
318 * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
\r
319 * |[6] |EWarn |Error Warning Status (Read Only)
\r
320 * | | |0 = Both error counters are below the error warning limit of 96.
\r
321 * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
\r
322 * |[7] |BOff |Bus-Off Status (Read Only)
\r
323 * | | |0 = The CAN module is not in bus-off state.
\r
324 * | | |1 = The CAN module is in bus-off state.
\r
326 * Offset: 0x08 Error Counter Register
\r
327 * ---------------------------------------------------------------------------------------------------
\r
328 * |Bits |Field |Descriptions
\r
329 * | :----: | :----: | :---- |
\r
330 * |[7:0] |TEC |Transmit Error Counter
\r
331 * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
\r
332 * |[14:8] |REC |Receive Error Counter
\r
333 * | | |Actual state of the Receive Error Counter. Values between 0 and 127.
\r
334 * |[15] |RP |Receive Error Passive
\r
335 * | | |0 = The Receive Error Counter is below the error passive level.
\r
336 * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
\r
337 * @var CAN_T::BTIME
\r
338 * Offset: 0x0C Bit Timing Register
\r
339 * ---------------------------------------------------------------------------------------------------
\r
340 * |Bits |Field |Descriptions
\r
341 * | :----: | :----: | :---- |
\r
342 * |[5:0] |BRP |Baud Rate Prescaler
\r
343 * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
\r
344 * | | |The bit time is built up from a multiple of this quanta.
\r
345 * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
\r
346 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
\r
347 * |[7:6] |SJW |(Re)Synchronization Jump Width
\r
348 * | | |0x0-0x3: Valid programmed values are [0 ... 3].
\r
349 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
\r
350 * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
\r
351 * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
\r
352 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
\r
353 * |[14:12] |TSeg2 |Time Segment After Sample Point
\r
354 * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
\r
355 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
\r
357 * Offset: 0x10 Interrupt Identifier Register
\r
358 * ---------------------------------------------------------------------------------------------------
\r
359 * |Bits |Field |Descriptions
\r
360 * | :----: | :----: | :---- |
\r
361 * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
\r
362 * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
\r
363 * | | |An interrupt remains pending until the application software has cleared it.
\r
364 * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
\r
365 * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
\r
366 * | | |The Status Interrupt has the highest priority.
\r
367 * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
\r
368 * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
\r
369 * | | |The Status Interrupt is cleared by reading the Status Register.
\r
371 * Offset: 0x14 Test Register (Register Map Note 1)
\r
372 * ---------------------------------------------------------------------------------------------------
\r
373 * |Bits |Field |Descriptions
\r
374 * | :----: | :----: | :---- |
\r
375 * |[1:0] |Res |Reserved
\r
376 * | | |There are reserved bits.
\r
377 * | | |These bits are always read as '0' and must always be written with '0'.
\r
378 * |[2] |Basic |Basic Mode
\r
379 * | | |0 = Basic Mode disabled.
\r
380 * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
\r
381 * |[3] |Silent |Silent Mode
\r
382 * | | |0 = Normal operation.
\r
383 * | | |1 = The module is in Silent Mode.
\r
384 * |[4] |LBack |Loop Back Mode Enable Control
\r
385 * | | |0 = Loop Back Mode is disabled.
\r
386 * | | |1 = Loop Back Mode is enabled.
\r
387 * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
\r
388 * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
\r
389 * | | |01 = Sample Point can be monitored at CAN_TX pin.
\r
390 * | | |10 = CAN_TX pin drives a dominant ('0') value.
\r
391 * | | |11 = CAN_TX pin drives a recessive ('1') value.
\r
392 * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
\r
393 * | | |0 = The CAN bus is dominant (CAN_RX = '0').
\r
394 * | | |1 = The CAN bus is recessive (CAN_RX = '1').
\r
396 * Offset: 0x18 Baud Rate Prescaler Extension Register
\r
397 * ---------------------------------------------------------------------------------------------------
\r
398 * |Bits |Field |Descriptions
\r
399 * | :----: | :----: | :---- |
\r
400 * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
\r
401 * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
\r
402 * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
\r
404 * Offset: 0x20~0xFC CAN Interface Registers
\r
405 * ---------------------------------------------------------------------------------------------------
\r
406 * CAN interface structure. Refer to \ref CAN_IF_T for detail information.
\r
408 * @var CAN_T::TXREQ1
\r
409 * Offset: 0x100 Transmission Request Register 1
\r
410 * ---------------------------------------------------------------------------------------------------
\r
411 * |Bits |Field |Descriptions
\r
412 * | :----: | :----: | :---- |
\r
413 * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
\r
414 * | | |0 = This Message Object is not waiting for transmission.
\r
415 * | | |1 = The transmission of this Message Object is requested and is not yet done.
\r
416 * | | |These bits are read only.
\r
417 * @var CAN_T::TXREQ2
\r
418 * Offset: 0x104 Transmission Request Register 2
\r
419 * ---------------------------------------------------------------------------------------------------
\r
420 * |Bits |Field |Descriptions
\r
421 * | :----: | :----: | :---- |
\r
422 * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
\r
423 * | | |0 = This Message Object is not waiting for transmission.
\r
424 * | | |1 = The transmission of this Message Object is requested and is not yet done.
\r
425 * | | |These bits are read only.
\r
426 * @var CAN_T::NDAT1
\r
427 * Offset: 0x120 New Data Register 1
\r
428 * ---------------------------------------------------------------------------------------------------
\r
429 * |Bits |Field |Descriptions
\r
430 * | :----: | :----: | :---- |
\r
431 * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
\r
432 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
\r
433 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
\r
434 * @var CAN_T::NDAT2
\r
435 * Offset: 0x124 New Data Register 2
\r
436 * ---------------------------------------------------------------------------------------------------
\r
437 * |Bits |Field |Descriptions
\r
438 * | :----: | :----: | :---- |
\r
439 * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
\r
440 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
\r
441 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
\r
442 * @var CAN_T::IPND1
\r
443 * Offset: 0x140 Interrupt Pending Register 1
\r
444 * ---------------------------------------------------------------------------------------------------
\r
445 * |Bits |Field |Descriptions
\r
446 * | :----: | :----: | :---- |
\r
447 * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
\r
448 * | | |0 = This message object is not the source of an interrupt.
\r
449 * | | |1 = This message object is the source of an interrupt.
\r
450 * @var CAN_T::IPND2
\r
451 * Offset: 0x144 Interrupt Pending Register 2
\r
452 * ---------------------------------------------------------------------------------------------------
\r
453 * |Bits |Field |Descriptions
\r
454 * | :----: | :----: | :---- |
\r
455 * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
\r
456 * | | |0 = This message object is not the source of an interrupt.
\r
457 * | | |1 = This message object is the source of an interrupt.
\r
458 * @var CAN_T::MVLD1
\r
459 * Offset: 0x160 Message Valid Register 1
\r
460 * ---------------------------------------------------------------------------------------------------
\r
461 * |Bits |Field |Descriptions
\r
462 * | :----: | :----: | :---- |
\r
463 * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
\r
464 * | | |0 = This Message Object is ignored by the Message Handler.
\r
465 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
\r
467 * | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
\r
468 * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
\r
469 * @var CAN_T::MVLD2
\r
470 * Offset: 0x164 Message Valid Register 2
\r
471 * ---------------------------------------------------------------------------------------------------
\r
472 * |Bits |Field |Descriptions
\r
473 * | :----: | :----: | :---- |
\r
474 * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
\r
475 * | | |0 = This Message Object is ignored by the Message Handler.
\r
476 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
\r
477 * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
\r
478 * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
\r
479 * @var CAN_T::WU_EN
\r
480 * Offset: 0x168 Wake-up Enable Register
\r
481 * ---------------------------------------------------------------------------------------------------
\r
482 * |Bits |Field |Descriptions
\r
483 * | :----: | :----: | :---- |
\r
484 * |[0] |WAKUP_EN |Wake-Up Enable Control
\r
485 * | | |0 = The wake-up function Disabled.
\r
486 * | | |1 = The wake-up function Enabled.
\r
487 * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
\r
488 * @var CAN_T::WU_STATUS
\r
489 * Offset: 0x16C Wake-up Status Register
\r
490 * ---------------------------------------------------------------------------------------------------
\r
491 * |Bits |Field |Descriptions
\r
492 * | :----: | :----: | :---- |
\r
493 * |[0] |WAKUP_STS |Wake-Up Status
\r
494 * | | |0 = No wake-up event occurred.
\r
495 * | | |1 = Wake-up event occurred.
\r
496 * | | |Note: This bit can be cleared by writing '0'.
\r
499 __IO uint32_t CON; /* Offset: 0x00 Control Register */
\r
500 __IO uint32_t STATUS; /* Offset: 0x04 Status Register */
\r
501 __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */
\r
502 __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */
\r
503 __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */
\r
504 __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */
\r
505 __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */
\r
506 __I uint32_t RESERVE0[1];
\r
507 __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */
\r
508 __I uint32_t RESERVE1[8];
\r
509 __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */
\r
510 __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */
\r
511 __I uint32_t RESERVE3[6];
\r
512 __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */
\r
513 __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */
\r
514 __I uint32_t RESERVE4[6];
\r
515 __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */
\r
516 __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */
\r
517 __I uint32_t RESERVE5[6];
\r
518 __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */
\r
519 __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */
\r
520 __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */
\r
521 __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */
\r
528 @addtogroup CAN_CONST CAN Bit Field Definition
\r
529 Constant Definitions for CAN Controller
\r
531 /* CAN CON Bit Field Definitions */
\r
532 #define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */
\r
533 #define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */
\r
535 #define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */
\r
536 #define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
\r
538 #define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */
\r
539 #define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
\r
541 #define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */
\r
542 #define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
\r
544 #define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */
\r
545 #define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
\r
547 #define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */
\r
548 #define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
\r
550 #define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */
\r
551 #define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */
\r
553 /* CAN STATUS Bit Field Definitions */
\r
554 #define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */
\r
555 #define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */
\r
557 #define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */
\r
558 #define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */
\r
560 #define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */
\r
561 #define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */
\r
563 #define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */
\r
564 #define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */
\r
566 #define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */
\r
567 #define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */
\r
569 #define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */
\r
570 #define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
\r
572 /* CAN ERR Bit Field Definitions */
\r
573 #define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */
\r
574 #define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
\r
576 #define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */
\r
577 #define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
\r
579 #define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */
\r
580 #define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
\r
582 /* CAN BTIME Bit Field Definitions */
\r
583 #define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */
\r
584 #define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */
\r
586 #define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */
\r
587 #define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */
\r
589 #define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */
\r
590 #define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
\r
592 #define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */
\r
593 #define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
\r
595 /* CAN IIDR Bit Field Definitions */
\r
596 #define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */
\r
597 #define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */
\r
599 /* CAN TEST Bit Field Definitions */
\r
600 #define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */
\r
601 #define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */
\r
603 #define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */
\r
604 #define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */
\r
606 #define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */
\r
607 #define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */
\r
609 #define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */
\r
610 #define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
\r
612 #define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */
\r
613 #define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
\r
615 /* CAN BPRE Bit Field Definitions */
\r
616 #define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */
\r
617 #define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
\r
619 /* CAN IFn_CREQ Bit Field Definitions */
\r
620 #define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */
\r
621 #define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */
\r
623 #define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */
\r
624 #define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */
\r
626 /* CAN IFn_CMASK Bit Field Definitions */
\r
627 #define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */
\r
628 #define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */
\r
630 #define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */
\r
631 #define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */
\r
633 #define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */
\r
634 #define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */
\r
636 #define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */
\r
637 #define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */
\r
639 #define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */
\r
640 #define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
\r
642 #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
\r
643 #define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */
\r
645 #define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */
\r
646 #define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */
\r
648 #define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */
\r
649 #define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */
\r
651 /* CAN IFn_MASK1 Bit Field Definitions */
\r
652 #define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */
\r
653 #define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */
\r
655 /* CAN IFn_MASK2 Bit Field Definitions */
\r
656 #define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */
\r
657 #define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */
\r
659 #define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */
\r
660 #define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */
\r
662 #define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */
\r
663 #define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */
\r
665 /* CAN IFn_ARB1 Bit Field Definitions */
\r
666 #define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */
\r
667 #define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
\r
669 /* CAN IFn_ARB2 Bit Field Definitions */
\r
670 #define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */
\r
671 #define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */
\r
673 #define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */
\r
674 #define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */
\r
676 #define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */
\r
677 #define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */
\r
679 #define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */
\r
680 #define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
\r
682 /* CAN IFn_MCON Bit Field Definitions */
\r
683 #define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */
\r
684 #define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */
\r
686 #define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */
\r
687 #define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */
\r
689 #define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */
\r
690 #define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */
\r
692 #define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */
\r
693 #define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */
\r
695 #define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */
\r
696 #define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */
\r
698 #define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */
\r
699 #define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */
\r
701 #define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */
\r
702 #define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */
\r
704 #define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */
\r
705 #define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */
\r
707 #define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */
\r
708 #define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */
\r
710 #define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */
\r
711 #define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
\r
713 /* CAN IFn_DATA_A1 Bit Field Definitions */
\r
714 #define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */
\r
715 #define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */
\r
717 #define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */
\r
718 #define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */
\r
720 /* CAN IFn_DATA_A2 Bit Field Definitions */
\r
721 #define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */
\r
722 #define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */
\r
724 #define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */
\r
725 #define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */
\r
727 /* CAN IFn_DATA_B1 Bit Field Definitions */
\r
728 #define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */
\r
729 #define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */
\r
731 #define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */
\r
732 #define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */
\r
734 /* CAN IFn_DATA_B2 Bit Field Definitions */
\r
735 #define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */
\r
736 #define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */
\r
738 #define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */
\r
739 #define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */
\r
741 /* CAN IFn_TXRQST1 Bit Field Definitions */
\r
742 #define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */
\r
743 #define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */
\r
745 /* CAN IFn_TXRQST2 Bit Field Definitions */
\r
746 #define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */
\r
747 #define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */
\r
749 /* CAN IFn_NDAT1 Bit Field Definitions */
\r
750 #define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */
\r
751 #define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */
\r
753 /* CAN IFn_NDAT2 Bit Field Definitions */
\r
754 #define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */
\r
755 #define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */
\r
757 /* CAN IFn_IPND1 Bit Field Definitions */
\r
758 #define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */
\r
759 #define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */
\r
761 /* CAN IFn_IPND2 Bit Field Definitions */
\r
762 #define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */
\r
763 #define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */
\r
765 /* CAN IFn_MVLD1 Bit Field Definitions */
\r
766 #define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */
\r
767 #define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */
\r
769 /* CAN IFn_MVLD2 Bit Field Definitions */
\r
770 #define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */
\r
771 #define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */
\r
773 /* CAN WUEN Bit Field Definitions */
\r
774 #define CAN_WU_EN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */
\r
775 #define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
\r
777 /* CAN WUSTATUS Bit Field Definitions */
\r
778 #define CAN_WU_STATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
\r
779 #define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
\r
782 /**@}*/ /* CAN_CONST */
\r
783 /**@}*/ /* end of CAN register group */
\r
784 /**@}*/ /* end of REGISTER group */
\r
787 #endif /* __CAN_REG_H__ */
\r
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