1 /**************************************************************************//**
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4 * @brief CRPT register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __CRPT_REG_H__
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9 #define __CRPT_REG_H__
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12 /** @addtogroup REGISTER Control Register
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19 /*---------------------- Cryptographic Accelerator -------------------------*/
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21 @addtogroup CRPT Cryptographic Accelerator(CRPT)
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22 Memory Mapped Structure for CRPT Controller
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30 * @var CRPT_T::INTEN
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31 * Offset: 0x00 Crypto Interrupt Enable Control Register
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32 * ---------------------------------------------------------------------------------------------------
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33 * |Bits |Field |Descriptions
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34 * | :----: | :----: | :---- |
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35 * |[0] |AESIEN |AES Interrupt Enable Control
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36 * | | |0 = AES interrupt Disabled.
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37 * | | |1 = AES interrupt Enabled.
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38 * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
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39 * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
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40 * |[1] |AESEIEN |AES Error Flag Enable Control
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41 * | | |0 = AES error interrupt flag Disabled.
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42 * | | |1 = AES error interrupt flag Enabled.
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43 * |[8] |TDESIEN |TDES/DES Interrupt Enable Control
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44 * | | |0 = TDES/DES interrupt Disabled.
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45 * | | |1 = TDES/DES interrupt Enabled.
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46 * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.
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47 * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
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48 * |[9] |TDESEIEN |TDES/DES Error Flag Enable Control
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49 * | | |0 = TDES/DES error interrupt flag Disabled.
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50 * | | |1 = TDES/DES error interrupt flag Enabled.
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51 * |[16] |PRNGIEN |PRNG Interrupt Enable Control
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52 * | | |0 = PRNG interrupt Disabled.
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53 * | | |1 = PRNG interrupt Enabled.
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54 * |[22] |ECCIEN |ECC Interrupt Enable Control
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55 * | | |0 = ECC interrupt Disabled.
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56 * | | |1 = ECC interrupt Enabled.
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57 * | | |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine.
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58 * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.
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59 * |[23] |ECCEIEN |ECC Error Interrupt Enable Control
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60 * | | |0 = ECC error interrupt flag Disabled.
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61 * | | |1 = ECC error interrupt flag Enabled.
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62 * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Control
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63 * | | |0 = SHA/HMAC interrupt Disabled.
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64 * | | |1 = SHA/HMAC interrupt Enabled.
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65 * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine
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66 * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation.
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67 * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Control
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68 * | | |0 = SHA/HMAC error interrupt flag Disabled.
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69 * | | |1 = SHA/HMAC error interrupt flag Enabled.
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70 * @var CRPT_T::INTSTS
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71 * Offset: 0x04 Crypto Interrupt Flag
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72 * ---------------------------------------------------------------------------------------------------
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73 * |Bits |Field |Descriptions
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74 * | :----: | :----: | :---- |
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75 * |[0] |AESIF |AES Finish Interrupt Flag
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76 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
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77 * | | |0 = No AES interrupt.
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78 * | | |1 = AES encryption/decryption done interrupt.
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79 * |[1] |AESEIF |AES Error Flag
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80 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
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81 * | | |0 = No AES error.
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82 * | | |1 = AES encryption/decryption done interrupt.
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83 * |[8] |TDESIF |TDES/DES Finish Interrupt Flag
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84 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
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85 * | | |0 = No TDES/DES interrupt.
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86 * | | |1 = TDES/DES encryption/decryption done interrupt.
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87 * |[9] |TDESEIF |TDES/DES Error Flag
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88 * | | |This bit includes the operating and setting error
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89 * | | |The detailed flag is shown in the TDES _FLAG register
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90 * | | |This includes operating and setting error.
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91 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
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92 * | | |0 = No TDES/DES error.
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93 * | | |1 = TDES/DES encryption/decryption error interrupt.
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94 * |[16] |PRNGIF |PRNG Finish Interrupt Flag
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95 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
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96 * | | |0 = No PRNG interrupt.
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97 * | | |1 = PRNG key generation done interrupt.
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98 * |[22] |ECCIF |ECC Finish Interrupt Flag
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99 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
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100 * | | |0 = No ECC interrupt.
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101 * | | |1 = ECC operation done interrupt.
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102 * |[23] |ECCEIF |ECC Error Flag
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103 * | | |This register includes operating and setting error. The detail flag is shown in ECC _FLAG register.
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104 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
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105 * | | |0 = No ECC error.
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106 * | | |1 = ECC error interrupt.
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107 * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag
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108 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
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109 * | | |0 = No SHA/HMAC interrupt.
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110 * | | |1 = SHA/HMAC operation done interrupt.
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111 * |[25] |HMACEIF |SHA/HMAC Error Flag
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112 * | | |This register includes operating and setting error. The detail flag is shown in SHA _FLAG register.
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113 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
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114 * | | |0 = No SHA/HMAC error.
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115 * | | |1 = SHA/HMAC error interrupt.
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116 * @var CRPT_T::PRNG_CTL
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117 * Offset: 0x08 PRNG Control Register
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118 * ---------------------------------------------------------------------------------------------------
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119 * |Bits |Field |Descriptions
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120 * | :----: | :----: | :---- |
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121 * |[0] |START |Start PRNG Engine
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122 * | | |0 = Stop PRNG engine.
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123 * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated.
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124 * |[1] |SEEDRLD |Reload New Seed for PRNG Engine
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125 * | | |0 = Generating key based on the current seed.
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126 * | | |1 = Reload new seed.
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127 * |[3:2] |KEYSZ |PRNG Generate Key Size
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128 * | | |00 = 64 bits.
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129 * | | |01 = 128 bits.
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130 * | | |10 = 192 bits.
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131 * | | |11 = 256 bits.
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132 * |[8] |BUSY |PRNG Busy (Read Only)
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133 * | | |0 = PRNG engine is idle.
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134 * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
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135 * @var CRPT_T::PRNG_SEED
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136 * Offset: 0x0C Seed for PRNG
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137 * ---------------------------------------------------------------------------------------------------
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138 * |Bits |Field |Descriptions
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139 * | :----: | :----: | :---- |
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140 * |[31:0] |SEED |Seed for PRNG (Write Only)
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141 * | | |The bits store the seed for PRNG engine.
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142 * @var CRPT_T::PRNG_KEY[8]
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143 * Offset: 0x10 PRNG Generated Key0~Key7
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144 * ---------------------------------------------------------------------------------------------------
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145 * |Bits |Field |Descriptions
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146 * | :----: | :----: | :---- |
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147 * |[31:0] |KEY |Store PRNG Generated Key (Read Only)
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148 * | | |The bits store the key that is generated by PRNG.
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149 * @var CRPT_T::AES_FDBCK[4]
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150 * Offset: 0x50 AES Engine Output Feedback Data after Cryptographic Operation
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151 * ---------------------------------------------------------------------------------------------------
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152 * |Bits |Field |Descriptions
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153 * | :----: | :----: | :---- |
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154 * |[31:0] |FDBCK |AES Feedback Information
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155 * | | |The feedback value is 128 bits in size.
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156 * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.
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157 * | | |The AES engine outputs feedback information for IV in the next block's operation
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158 * | | |Software can use this feedback information to implement more than four DMA channels
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159 * | | |Software can store that feedback value temporarily
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160 * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
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161 * @var CRPT_T::TDES_FDBCKH
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162 * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation
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163 * ---------------------------------------------------------------------------------------------------
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164 * |Bits |Field |Descriptions
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165 * | :----: | :----: | :---- |
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166 * |[31:0] |FDBCK |TDES/DES Feedback
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167 * | | |The feedback value is 64 bits in size.
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168 * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
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169 * | | |The feedback register is for CBC, CFB, and OFB mode.
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170 * | | |TDES/DES engine outputs feedback information for IV in the next block's operation
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171 * | | |Software can use this feedback information to implement more than four DMA channels
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172 * | | |Software can store that feedback value temporarily
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173 * | | |After switching back, fill the stored feedback value to this register in the same channel operation
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174 * | | |Then can continue the operation with the original setting.
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175 * @var CRPT_T::TDES_FDBCKL
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176 * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation
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177 * ---------------------------------------------------------------------------------------------------
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178 * |Bits |Field |Descriptions
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179 * | :----: | :----: | :---- |
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180 * |[31:0] |FDBCK |TDES/DES Feedback
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181 * | | |The feedback value is 64 bits in size.
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182 * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode
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183 * | | |The feedback register is for CBC, CFB, and OFB mode.
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184 * | | |TDES/DES engine outputs feedback information for IV in the next block's operation
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185 * | | |Software can use this feedback information to implement more than four DMA channels
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186 * | | |Software can store that feedback value temporarily
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187 * | | |After switching back, fill the stored feedback value to this register in the same channel operation
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188 * | | |Then can continue the operation with the original setting.
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189 * @var CRPT_T::AES_CTL
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190 * Offset: 0x100 AES Control Register
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191 * ---------------------------------------------------------------------------------------------------
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192 * |Bits |Field |Descriptions
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193 * | :----: | :----: | :---- |
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194 * |[0] |START |AES Engine Start
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195 * | | |0 = No effect.
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196 * | | |1 = Start AES engine. BUSY flag will be set.
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197 * | | |Note: This bit is always 0 when it's read back.
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198 * |[1] |STOP |AES Engine Stop
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199 * | | |0 = No effect.
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200 * | | |1 = Stop AES engine.
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201 * | | |Note: This bit is always 0 when it's read back.
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202 * |[3:2] |KEYSZ |AES Key Size
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203 * | | |This bit defines three different key size for AES operation.
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204 * | | |2'b00 = 128 bits key.
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205 * | | |2'b01 = 192 bits key.
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206 * | | |2'b10 = 256 bits key.
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207 * | | |2'b11 = Reserved.
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208 * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
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209 * |[5] |DMALAST |AES Last Block
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210 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
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211 * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
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212 * | | |This bit is always 0 when it's read back. Must be written again once START is triggered.
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213 * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode
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214 * | | |0 = DMA cascade function Disabled.
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215 * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
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216 * |[7] |DMAEN |AES Engine DMA Enable Control
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217 * | | |0 = AES DMA engine Disabled.
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218 * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN.
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219 * | | |1 = AES_DMA engine Enabled.
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220 * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
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221 * |[15:8] |OPMODE |AES Engine Operation Modes
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222 * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode).
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223 * | | |0x02 = CFB (Cipher Feedback Mode).
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224 * | | |0x03 = OFB (Output Feedback Mode).
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225 * | | |0x04 = CTR (Counter Mode).
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226 * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
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227 * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
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228 * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
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229 * |[16] |ENCRPT |AES Encryption/Decryption
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230 * | | |0 = AES engine executes decryption operation.
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231 * | | |1 = AES engine executes encryption operation.
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232 * |[22] |OUTSWAP |AES Engine Output Data Swap
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233 * | | |0 = Keep the original order.
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234 * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
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235 * |[23] |INSWAP |AES Engine Input Data Swap
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236 * | | |0 = Keep the original order.
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237 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
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238 * |[25:24] |CHANNEL |AES Engine Working Channel
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239 * | | |00 = Current control register setting is for channel 0.
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240 * | | |01 = Current control register setting is for channel 1.
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241 * | | |10 = Current control register setting is for channel 2.
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242 * | | |11 = Current control register setting is for channel 3.
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243 * |[30:26] |KEYUNPRT |Unprotect Key
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244 * | | |Writing 0 to CRPT_AES_CTL[31] and ...10110 to CRPT_AES_CTL[30:26] is to unprotect the AES key.
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245 * | | |The KEYUNPRT can be read and written
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246 * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
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247 * |[31] |KEYPRT |Protect Key
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248 * | | |Read as a flag to reflect KEYPRT.
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249 * | | |0 = No effect.
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250 * | | |1 = Protect the content of the AES key from reading
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251 * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx
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252 * | | |Once it is set, it can be cleared by asserting KEYUNPRT
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253 * | | |And the key content would be cleared as well.
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254 * @var CRPT_T::AES_STS
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255 * Offset: 0x104 AES Engine Flag
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256 * ---------------------------------------------------------------------------------------------------
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257 * |Bits |Field |Descriptions
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258 * | :----: | :----: | :---- |
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259 * |[0] |BUSY |AES Engine Busy
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260 * | | |0 = The AES engine is idle or finished.
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261 * | | |1 = The AES engine is under processing.
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262 * |[8] |INBUFEMPTY|AES Input Buffer Empty
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263 * | | |0 = There are some data in input buffer waiting for the AES engine to process.
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264 * | | |1 = AES input buffer is empty
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265 * | | |Software needs to feed data to the AES engine
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266 * | | |Otherwise, the AES engine will be pending to wait for input data.
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267 * |[9] |INBUFFULL |AES Input Buffer Full Flag
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268 * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine.
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269 * | | |1 = AES input buffer is full
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270 * | | |Software cannot feed data to the AES engine
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271 * | | |Otherwise, the flag INBUFERR will be set to 1.
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272 * |[10] |INBUFERR |AES Input Buffer Error Flag
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273 * | | |0 = No error.
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274 * | | |1 = Error happens during feeding data to the AES engine.
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275 * |[12] |CNTERR |CRPT_AESn_CNT Setting Error
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276 * | | |0 = No error in CRPT_AESn_CNT setting.
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277 * | | |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode.
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278 * |[16] |OUTBUFEMPTY|AES Out Buffer Empty
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279 * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer.
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280 * | | |1 = AES output buffer is empty
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281 * | | |Software cannot get data from CRPT_AES_DATOUT
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282 * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
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283 * |[17] |OUTBUFFULL|AES Out Buffer Full Flag
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284 * | | |0 = AES output buffer is not full.
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285 * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT
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286 * | | |Otherwise, the AES engine will be pending since the output buffer is full.
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287 * |[18] |OUTBUFERR |AES Out Buffer Error Flag
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288 * | | |0 = No error.
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289 * | | |1 = Error happens during getting the result from AES engine.
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290 * |[20] |BUSERR |AES DMA Access Bus Error Flag
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291 * | | |0 = No error.
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292 * | | |1 = Bus error will stop DMA operation and AES engine.
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293 * @var CRPT_T::AES_DATIN
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294 * Offset: 0x108 AES Engine Data Input Port Register
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295 * ---------------------------------------------------------------------------------------------------
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296 * |Bits |Field |Descriptions
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297 * | :----: | :----: | :---- |
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298 * |[31:0] |DATIN |AES Engine Input Port
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299 * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
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300 * @var CRPT_T::AES_DATOUT
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301 * Offset: 0x10C AES Engine Data Output Port Register
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302 * ---------------------------------------------------------------------------------------------------
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303 * |Bits |Field |Descriptions
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304 * | :----: | :----: | :---- |
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305 * |[31:0] |DATOUT |AES Engine Output Port
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306 * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS
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307 * | | |Get data as OUTBUFEMPTY is 0.
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308 * @var CRPT_T::AES0_KEY[8]
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309 * Offset: 0x110~0x12C AES Key Word 0~7 Register for Channel 0
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310 * ---------------------------------------------------------------------------------------------------
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311 * |Bits |Field |Descriptions
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312 * | :----: | :----: | :---- |
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313 * |[31:0] |KEY |CRPT_AESn_KEYx
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314 * | | |The KEY keeps the security key for AES operation.
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315 * | | |n = 0, 1..3.
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316 * | | |x = 0, 1..7.
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317 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
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318 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
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319 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
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320 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
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321 * @var CRPT_T::AES0_IV[4]
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322 * Offset: 0x130~0x13C AES Initial Vector Word 0~3 Register for Channel 0
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323 * ---------------------------------------------------------------------------------------------------
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324 * |Bits |Field |Descriptions
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325 * | :----: | :----: | :---- |
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326 * |[31:0] |IV |AES Initial Vectors
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327 * | | |n = 0, 1..3.
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328 * | | |x = 0, 1..3.
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329 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
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330 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
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331 * @var CRPT_T::AES0_SADDR
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332 * Offset: 0x140 AES DMA Source Address Register for Channel 0
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333 * ---------------------------------------------------------------------------------------------------
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334 * |Bits |Field |Descriptions
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335 * | :----: | :----: | :---- |
\r
336 * |[31:0] |SADDR |AES DMA Source Address
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337 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
\r
338 * | | |The SADDR keeps the source address of the data buffer where the source text is stored
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339 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
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340 * | | |The start of source address should be located at word boundary
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341 * | | |In other words, bit 1 and 0 of SADDR are ignored.
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342 * | | |SADDR can be read and written
\r
343 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
\r
344 * | | |But the value of SADDR will be updated later on
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345 * | | |Consequently, software can prepare the DMA source address for the next AES operation.
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346 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
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347 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
\r
348 * @var CRPT_T::AES0_DADDR
\r
349 * Offset: 0x144 AES DMA Destination Address Register for Channel 0
\r
350 * ---------------------------------------------------------------------------------------------------
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351 * |Bits |Field |Descriptions
\r
352 * | :----: | :----: | :---- |
\r
353 * |[31:0] |DADDR |AES DMA Destination Address
\r
354 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
\r
355 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
\r
356 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
\r
357 * | | |The start of destination address should be located at word boundary
\r
358 * | | |In other words, bit 1 and 0 of DADDR are ignored.
\r
359 * | | |DADDR can be read and written
\r
360 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
\r
361 * | | |But the value of DADDR will be updated later on
\r
362 * | | |Consequently, software can prepare the destination address for the next AES operation.
\r
363 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
\r
364 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
\r
365 * @var CRPT_T::AES0_CNT
\r
366 * Offset: 0x148 AES Byte Count Register for Channel 0
\r
367 * ---------------------------------------------------------------------------------------------------
\r
368 * |Bits |Field |Descriptions
\r
369 * | :----: | :----: | :---- |
\r
370 * |[31:0] |CNT |AES Byte Count
\r
371 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
\r
372 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
\r
373 * | | |CRPT_AESn_CNT can be read and written
\r
374 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
\r
375 * | | |But the value of CRPT_AESn_CNT will be updated later on
\r
376 * | | |Consequently, software can prepare the byte count of data for the next AES operation.
\r
377 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
\r
378 * | | |Operations that are less than one block will output unexpected result.
\r
379 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
\r
380 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
\r
381 * @var CRPT_T::AES1_KEY[8]
\r
382 * Offset: 0x14C~0x168 AES Key Word 0~7 Register for Channel 1
\r
383 * ---------------------------------------------------------------------------------------------------
\r
384 * |Bits |Field |Descriptions
\r
385 * | :----: | :----: | :---- |
\r
386 * |[31:0] |KEY |CRPT_AESn_KEYx
\r
387 * | | |The KEY keeps the security key for AES operation.
\r
388 * | | |n = 0, 1..3.
\r
389 * | | |x = 0, 1..7.
\r
390 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
\r
391 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
\r
392 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
\r
393 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
\r
394 * @var CRPT_T::AES1_IV[4]
\r
395 * Offset: 0x16C~0x178 AES Initial Vector Word 0~3 Register for Channel 1
\r
396 * ---------------------------------------------------------------------------------------------------
\r
397 * |Bits |Field |Descriptions
\r
398 * | :----: | :----: | :---- |
\r
399 * |[31:0] |IV |AES Initial Vectors
\r
400 * | | |n = 0, 1..3.
\r
401 * | | |x = 0, 1..3.
\r
402 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
\r
403 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
\r
404 * @var CRPT_T::AES1_SADDR
\r
405 * Offset: 0x17C AES DMA Source Address Register for Channel 1
\r
406 * ---------------------------------------------------------------------------------------------------
\r
407 * |Bits |Field |Descriptions
\r
408 * | :----: | :----: | :---- |
\r
409 * |[31:0] |SADDR |AES DMA Source Address
\r
410 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
\r
411 * | | |The SADDR keeps the source address of the data buffer where the source text is stored
\r
412 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
\r
413 * | | |The start of source address should be located at word boundary
\r
414 * | | |In other words, bit 1 and 0 of SADDR are ignored.
\r
415 * | | |SADDR can be read and written
\r
416 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
\r
417 * | | |But the value of SADDR will be updated later on
\r
418 * | | |Consequently, software can prepare the DMA source address for the next AES operation.
\r
419 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
\r
420 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
\r
421 * @var CRPT_T::AES1_DADDR
\r
422 * Offset: 0x180 AES DMA Destination Address Register for Channel 1
\r
423 * ---------------------------------------------------------------------------------------------------
\r
424 * |Bits |Field |Descriptions
\r
425 * | :----: | :----: | :---- |
\r
426 * |[31:0] |DADDR |AES DMA Destination Address
\r
427 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
\r
428 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
\r
429 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
\r
430 * | | |The start of destination address should be located at word boundary
\r
431 * | | |In other words, bit 1 and 0 of DADDR are ignored.
\r
432 * | | |DADDR can be read and written
\r
433 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
\r
434 * | | |But the value of DADDR will be updated later on
\r
435 * | | |Consequently, software can prepare the destination address for the next AES operation.
\r
436 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
\r
437 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
\r
438 * @var CRPT_T::AES1_CNT
\r
439 * Offset: 0x184 AES Byte Count Register for Channel 1
\r
440 * ---------------------------------------------------------------------------------------------------
\r
441 * |Bits |Field |Descriptions
\r
442 * | :----: | :----: | :---- |
\r
443 * |[31:0] |CNT |AES Byte Count
\r
444 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
\r
445 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
\r
446 * | | |CRPT_AESn_CNT can be read and written
\r
447 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
\r
448 * | | |But the value of CRPT_AESn_CNT will be updated later on
\r
449 * | | |Consequently, software can prepare the byte count of data for the next AES operation.
\r
450 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
\r
451 * | | |Operations that are less than one block will output unexpected result.
\r
452 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
\r
453 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
\r
454 * @var CRPT_T::AES2_KEY[8]
\r
455 * Offset: 0x188~0x1A4 AES Key Word 0~7 Register for Channel 2
\r
456 * ---------------------------------------------------------------------------------------------------
\r
457 * |Bits |Field |Descriptions
\r
458 * | :----: | :----: | :---- |
\r
459 * |[31:0] |KEY |CRPT_AESn_KEYx
\r
460 * | | |The KEY keeps the security key for AES operation.
\r
461 * | | |n = 0, 1..3.
\r
462 * | | |x = 0, 1..7.
\r
463 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
\r
464 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
\r
465 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
\r
466 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
\r
467 * @var CRPT_T::AES2_IV[4]
\r
468 * Offset: 0x1A8~0x1B4 AES Initial Vector Word 0~3 Register for Channel 2
\r
469 * ---------------------------------------------------------------------------------------------------
\r
470 * |Bits |Field |Descriptions
\r
471 * | :----: | :----: | :---- |
\r
472 * |[31:0] |IV |AES Initial Vectors
\r
473 * | | |n = 0, 1..3.
\r
474 * | | |x = 0, 1..3.
\r
475 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
\r
476 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
\r
477 * @var CRPT_T::AES2_SADDR
\r
478 * Offset: 0x1B8 AES DMA Source Address Register for Channel 2
\r
479 * ---------------------------------------------------------------------------------------------------
\r
480 * |Bits |Field |Descriptions
\r
481 * | :----: | :----: | :---- |
\r
482 * |[31:0] |SADDR |AES DMA Source Address
\r
483 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
\r
484 * | | |The SADDR keeps the source address of the data buffer where the source text is stored
\r
485 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
\r
486 * | | |The start of source address should be located at word boundary
\r
487 * | | |In other words, bit 1 and 0 of SADDR are ignored.
\r
488 * | | |SADDR can be read and written
\r
489 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
\r
490 * | | |But the value of SADDR will be updated later on
\r
491 * | | |Consequently, software can prepare the DMA source address for the next AES operation.
\r
492 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
\r
493 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
\r
494 * @var CRPT_T::AES2_DADDR
\r
495 * Offset: 0x1BC AES DMA Destination Address Register for Channel 2
\r
496 * ---------------------------------------------------------------------------------------------------
\r
497 * |Bits |Field |Descriptions
\r
498 * | :----: | :----: | :---- |
\r
499 * |[31:0] |DADDR |AES DMA Destination Address
\r
500 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
\r
501 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
\r
502 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
\r
503 * | | |The start of destination address should be located at word boundary
\r
504 * | | |In other words, bit 1 and 0 of DADDR are ignored.
\r
505 * | | |DADDR can be read and written
\r
506 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
\r
507 * | | |But the value of DADDR will be updated later on
\r
508 * | | |Consequently, software can prepare the destination address for the next AES operation.
\r
509 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
\r
510 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
\r
511 * @var CRPT_T::AES2_CNT
\r
512 * Offset: 0x1C0 AES Byte Count Register for Channel 2
\r
513 * ---------------------------------------------------------------------------------------------------
\r
514 * |Bits |Field |Descriptions
\r
515 * | :----: | :----: | :---- |
\r
516 * |[31:0] |CNT |AES Byte Count
\r
517 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
\r
518 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
\r
519 * | | |CRPT_AESn_CNT can be read and written
\r
520 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
\r
521 * | | |But the value of CRPT_AESn_CNT will be updated later on
\r
522 * | | |Consequently, software can prepare the byte count of data for the next AES operation.
\r
523 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
\r
524 * | | |Operations that are less than one block will output unexpected result.
\r
525 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
\r
526 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
\r
527 * @var CRPT_T::AES3_KEY[8]
\r
528 * Offset: 0x1C4~0x1E0 AES Key Word 0~7 Register for Channel 3
\r
529 * ---------------------------------------------------------------------------------------------------
\r
530 * |Bits |Field |Descriptions
\r
531 * | :----: | :----: | :---- |
\r
532 * |[31:0] |KEY |CRPT_AESn_KEYx
\r
533 * | | |The KEY keeps the security key for AES operation.
\r
534 * | | |n = 0, 1..3.
\r
535 * | | |x = 0, 1..7.
\r
536 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key
\r
537 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation
\r
538 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation
\r
539 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
\r
540 * @var CRPT_T::AES3_IV[4]
\r
541 * Offset: 0x1E4~0x1F0 AES Initial Vector Word 0~3 Register for Channel 3
\r
542 * ---------------------------------------------------------------------------------------------------
\r
543 * |Bits |Field |Descriptions
\r
544 * | :----: | :----: | :---- |
\r
545 * |[31:0] |IV |AES Initial Vectors
\r
546 * | | |n = 0, 1..3.
\r
547 * | | |x = 0, 1..3.
\r
548 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode
\r
549 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
\r
550 * @var CRPT_T::AES3_SADDR
\r
551 * Offset: 0x1F4 AES DMA Source Address Register for Channel 3
\r
552 * ---------------------------------------------------------------------------------------------------
\r
553 * |Bits |Field |Descriptions
\r
554 * | :----: | :----: | :---- |
\r
555 * |[31:0] |SADDR |AES DMA Source Address
\r
556 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
\r
557 * | | |The SADDR keeps the source address of the data buffer where the source text is stored
\r
558 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation
\r
559 * | | |The start of source address should be located at word boundary
\r
560 * | | |In other words, bit 1 and 0 of SADDR are ignored.
\r
561 * | | |SADDR can be read and written
\r
562 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation
\r
563 * | | |But the value of SADDR will be updated later on
\r
564 * | | |Consequently, software can prepare the DMA source address for the next AES operation.
\r
565 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.
\r
566 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
\r
567 * @var CRPT_T::AES3_DADDR
\r
568 * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3
\r
569 * ---------------------------------------------------------------------------------------------------
\r
570 * |Bits |Field |Descriptions
\r
571 * | :----: | :----: | :---- |
\r
572 * |[31:0] |DADDR |AES DMA Destination Address
\r
573 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
\r
574 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored
\r
575 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished
\r
576 * | | |The start of destination address should be located at word boundary
\r
577 * | | |In other words, bit 1 and 0 of DADDR are ignored.
\r
578 * | | |DADDR can be read and written
\r
579 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation
\r
580 * | | |But the value of DADDR will be updated later on
\r
581 * | | |Consequently, software can prepare the destination address for the next AES operation.
\r
582 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START.
\r
583 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
\r
584 * @var CRPT_T::AES3_CNT
\r
585 * Offset: 0x1FC AES Byte Count Register for Channel 3
\r
586 * ---------------------------------------------------------------------------------------------------
\r
587 * |Bits |Field |Descriptions
\r
588 * | :----: | :----: | :---- |
\r
589 * |[31:0] |CNT |AES Byte Count
\r
590 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode
\r
591 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
\r
592 * | | |CRPT_AESn_CNT can be read and written
\r
593 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation
\r
594 * | | |But the value of CRPT_AESn_CNT will be updated later on
\r
595 * | | |Consequently, software can prepare the byte count of data for the next AES operation.
\r
596 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block
\r
597 * | | |Operations that are less than one block will output unexpected result.
\r
598 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data
\r
599 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
\r
600 * @var CRPT_T::TDES_CTL
\r
601 * Offset: 0x200 TDES/DES Control Register
\r
602 * ---------------------------------------------------------------------------------------------------
\r
603 * |Bits |Field |Descriptions
\r
604 * | :----: | :----: | :---- |
\r
605 * |[0] |START |TDES/DES Engine Start
\r
606 * | | |0 = No effect.
\r
607 * | | |1 = Start TDES/DES engine. The flag BUSY would be set.
\r
608 * | | |Note: The bit is always 0 when it's read back.
\r
609 * |[1] |STOP |TDES/DES Engine Stop
\r
610 * | | |0 = No effect.
\r
611 * | | |1 = Stop TDES/DES engine.
\r
612 * | | |Note: The bit is always 0 when it's read back.
\r
613 * |[2] |TMODE |TDES/DES Engine Operating Mode
\r
614 * | | |0 = Set DES mode for TDES/DES engine.
\r
615 * | | |1 = Set Triple DES mode for TDES/DES engine.
\r
616 * |[3] |3KEYS |TDES/DES Key Number
\r
617 * | | |0 = Select KEY1 and KEY2 in TDES/DES engine.
\r
618 * | | |1 = Triple keys in TDES/DES engine Enabled.
\r
619 * |[5] |DMALAST |TDES/DES Engine Start for the Last Block
\r
620 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
\r
621 * | | |In Non-DMA mode, this bit must be set as feeding in last block of data.
\r
622 * |[6] |DMACSCAD |TDES/DES Engine DMA with Cascade Mode
\r
623 * | | |0 = DMA cascade function Disabled.
\r
624 * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
\r
625 * |[7] |DMAEN |TDES/DES Engine DMA Enable Control
\r
626 * | | |0 = TDES_DMA engine Disabled.
\r
627 * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN.
\r
628 * | | |1 = TDES_DMA engine Enabled.
\r
629 * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
\r
630 * |[10:8] |OPMODE |TDES/DES Engine Operation Mode
\r
631 * | | |0x00 = ECB (Electronic Codebook Mode).
\r
632 * | | |0x01 = CBC (Cipher Block Chaining Mode).
\r
633 * | | |0x02 = CFB (Cipher Feedback Mode).
\r
634 * | | |0x03 = OFB (Output Feedback Mode).
\r
635 * | | |0x04 = CTR (Counter Mode).
\r
636 * | | |Others = CTR (Counter Mode).
\r
637 * |[16] |ENCRPT |TDES/DES Encryption/Decryption
\r
638 * | | |0 = TDES engine executes decryption operation.
\r
639 * | | |1 = TDES engine executes encryption operation.
\r
640 * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap
\r
641 * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}.
\r
642 * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.
\r
643 * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap
\r
644 * | | |0 = Keep the original order.
\r
645 * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
\r
646 * |[23] |INSWAP |TDES/DES Engine Input Data Swap
\r
647 * | | |0 = Keep the original order.
\r
648 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
\r
649 * |[25:24] |CHANNEL |TDES/DES Engine Working Channel
\r
650 * | | |00 = Current control register setting is for channel 0.
\r
651 * | | |01 = Current control register setting is for channel 1.
\r
652 * | | |10 = Current control register setting is for channel 2.
\r
653 * | | |11 = Current control register setting is for channel 3.
\r
654 * |[30:26] |KEYUNPRT |Unprotect Key
\r
655 * | | |Writing 0 to CRPT_TDES_CTL [31] and ...10110 to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
\r
656 * | | |The KEYUNPRT can be read and written
\r
657 * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
\r
658 * |[31] |KEYPRT |Protect Key
\r
659 * | | |Read as a flag to reflect KEYPRT.
\r
660 * | | |0 = No effect.
\r
661 * | | |1 = This bit is to protect the content of TDES key from reading
\r
662 * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L
\r
663 * | | |Once it is set, it can be cleared by asserting KEYUNPRT
\r
664 * | | |The key content would be cleared as well.
\r
665 * @var CRPT_T::TDES_STS
\r
666 * Offset: 0x204 TDES/DES Engine Flag
\r
667 * ---------------------------------------------------------------------------------------------------
\r
668 * |Bits |Field |Descriptions
\r
669 * | :----: | :----: | :---- |
\r
670 * |[0] |BUSY |TDES/DES Engine Busy
\r
671 * | | |0 = TDES/DES engine is idle or finished.
\r
672 * | | |1 = TDES/DES engine is under processing.
\r
673 * |[8] |INBUFEMPTY|TDES/DES in Buffer Empty
\r
674 * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process.
\r
675 * | | |1 = TDES/DES input buffer is empty
\r
676 * | | |Software needs to feed data to the TDES/DES engine
\r
677 * | | |Otherwise, the TDES/DES engine will be pending to wait for input data.
\r
678 * |[9] |INBUFFULL |TDES/DES in Buffer Full Flag
\r
679 * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine.
\r
680 * | | |1 = TDES input buffer is full
\r
681 * | | |Software cannot feed data to the TDES/DES engine
\r
682 * | | |Otherwise, the flag INBUFERR will be set to 1.
\r
683 * |[10] |INBUFERR |TDES/DES in Buffer Error Flag
\r
684 * | | |0 = No error.
\r
685 * | | |1 = Error happens during feeding data to the TDES/DES engine.
\r
686 * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag
\r
687 * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer.
\r
688 * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT
\r
689 * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty.
\r
690 * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag
\r
691 * | | |0 = TDES/DES output buffer is not full.
\r
692 * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT
\r
693 * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full.
\r
694 * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag
\r
695 * | | |0 = No error.
\r
696 * | | |1 = Error happens during getting test result from TDES/DES engine.
\r
697 * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag
\r
698 * | | |0 = No error.
\r
699 * | | |1 = Bus error will stop DMA operation and TDES/DES engine.
\r
700 * @var CRPT_T::TDES0_KEY1H
\r
701 * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0
\r
702 * ---------------------------------------------------------------------------------------------------
\r
703 * |Bits |Field |Descriptions
\r
704 * | :----: | :----: | :---- |
\r
705 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
706 * | | |The key registers for TDES/DES algorithm calculation
\r
707 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
708 * | | |Thus, it needs two 32-bit registers to store a security key
\r
709 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
710 * @var CRPT_T::TDES0_KEY1L
\r
711 * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0
\r
712 * ---------------------------------------------------------------------------------------------------
\r
713 * |Bits |Field |Descriptions
\r
714 * | :----: | :----: | :---- |
\r
715 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
716 * | | |The key registers for TDES/DES algorithm calculation
\r
717 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
718 * | | |Thus, it needs two 32-bit registers to store a security key
\r
719 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
720 * @var CRPT_T::TDES0_KEY2H
\r
721 * Offset: 0x210 TDES Key 2 High Word Register for Channel 0
\r
722 * ---------------------------------------------------------------------------------------------------
\r
723 * |Bits |Field |Descriptions
\r
724 * | :----: | :----: | :---- |
\r
725 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
726 * | | |The key registers for TDES/DES algorithm calculation
\r
727 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
728 * | | |Thus, it needs two 32-bit registers to store a security key
\r
729 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
730 * @var CRPT_T::TDES0_KEY2L
\r
731 * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0
\r
732 * ---------------------------------------------------------------------------------------------------
\r
733 * |Bits |Field |Descriptions
\r
734 * | :----: | :----: | :---- |
\r
735 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
736 * | | |The key registers for TDES/DES algorithm calculation
\r
737 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
738 * | | |Thus, it needs two 32-bit registers to store a security key
\r
739 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
740 * @var CRPT_T::TDES0_KEY3H
\r
741 * Offset: 0x218 TDES Key 3 High Word Register for Channel 0
\r
742 * ---------------------------------------------------------------------------------------------------
\r
743 * |Bits |Field |Descriptions
\r
744 * | :----: | :----: | :---- |
\r
745 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
746 * | | |The key registers for TDES/DES algorithm calculation
\r
747 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
748 * | | |Thus, it needs two 32-bit registers to store a security key
\r
749 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
750 * @var CRPT_T::TDES0_KEY3L
\r
751 * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0
\r
752 * ---------------------------------------------------------------------------------------------------
\r
753 * |Bits |Field |Descriptions
\r
754 * | :----: | :----: | :---- |
\r
755 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
756 * | | |The key registers for TDES/DES algorithm calculation
\r
757 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
758 * | | |Thus, it needs two 32-bit registers to store a security key
\r
759 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
760 * @var CRPT_T::TDES0_IVH
\r
761 * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0
\r
762 * ---------------------------------------------------------------------------------------------------
\r
763 * |Bits |Field |Descriptions
\r
764 * | :----: | :----: | :---- |
\r
765 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word
\r
766 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
\r
767 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
\r
768 * @var CRPT_T::TDES0_IVL
\r
769 * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0
\r
770 * ---------------------------------------------------------------------------------------------------
\r
771 * |Bits |Field |Descriptions
\r
772 * | :----: | :----: | :---- |
\r
773 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word
\r
774 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
\r
775 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
\r
776 * @var CRPT_T::TDES0_SADDR
\r
777 * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0
\r
778 * ---------------------------------------------------------------------------------------------------
\r
779 * |Bits |Field |Descriptions
\r
780 * | :----: | :----: | :---- |
\r
781 * |[31:0] |SA |TDES/DES DMA Source Address
\r
782 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
\r
783 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
\r
784 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
\r
785 * | | |The start of source address should be located at word boundary
\r
786 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
\r
787 * | | |CRPT_TDESn_SA can be read and written
\r
788 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
789 * | | |But the value of CRPT_TDESn_SA will be updated later on
\r
790 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
\r
791 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
\r
792 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
\r
793 * @var CRPT_T::TDES0_DADDR
\r
794 * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0
\r
795 * ---------------------------------------------------------------------------------------------------
\r
796 * |Bits |Field |Descriptions
\r
797 * | :----: | :----: | :---- |
\r
798 * |[31:0] |DA |TDES/DES DMA Destination Address
\r
799 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
\r
800 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
\r
801 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
\r
802 * | | |The start of destination address should be located at word boundary
\r
803 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
\r
804 * | | |CRPT_TDESn_DA can be read and written
\r
805 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
806 * | | |But the value of CRPT_TDESn_DA will be updated later on
\r
807 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
\r
808 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
\r
809 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
\r
810 * @var CRPT_T::TDES0_CNT
\r
811 * Offset: 0x230 TDES/DES Byte Count Register for Channel 0
\r
812 * ---------------------------------------------------------------------------------------------------
\r
813 * |Bits |Field |Descriptions
\r
814 * | :----: | :----: | :---- |
\r
815 * |[31:0] |CNT |TDES/DES Byte Count
\r
816 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
\r
817 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
\r
818 * | | |CRPT_TDESn_CNT can be read and written
\r
819 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
820 * | | |But the value of CRPT_TDESn_CNT will be updated later on
\r
821 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
\r
822 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
\r
823 * @var CRPT_T::TDES_DATIN
\r
824 * Offset: 0x234 TDES/DES Engine Input data Word Register
\r
825 * ---------------------------------------------------------------------------------------------------
\r
826 * |Bits |Field |Descriptions
\r
827 * | :----: | :----: | :---- |
\r
828 * |[31:0] |DATIN |TDES/DES Engine Input Port
\r
829 * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS
\r
830 * | | |Feed data as INBUFFULL is 0.
\r
831 * @var CRPT_T::TDES_DATOUT
\r
832 * Offset: 0x238 TDES/DES Engine Output data Word Register
\r
833 * ---------------------------------------------------------------------------------------------------
\r
834 * |Bits |Field |Descriptions
\r
835 * | :----: | :----: | :---- |
\r
836 * |[31:0] |DATOUT |TDES/DES Engine Output Port
\r
837 * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS
\r
838 * | | |Get data as OUTBUFEMPTY is 0.
\r
839 * @var CRPT_T::TDES1_KEY1H
\r
840 * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1
\r
841 * ---------------------------------------------------------------------------------------------------
\r
842 * |Bits |Field |Descriptions
\r
843 * | :----: | :----: | :---- |
\r
844 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
845 * | | |The key registers for TDES/DES algorithm calculation
\r
846 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
847 * | | |Thus, it needs two 32-bit registers to store a security key
\r
848 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
849 * @var CRPT_T::TDES1_KEY1L
\r
850 * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1
\r
851 * ---------------------------------------------------------------------------------------------------
\r
852 * |Bits |Field |Descriptions
\r
853 * | :----: | :----: | :---- |
\r
854 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
855 * | | |The key registers for TDES/DES algorithm calculation
\r
856 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
857 * | | |Thus, it needs two 32-bit registers to store a security key
\r
858 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
859 * @var CRPT_T::TDES1_KEY2H
\r
860 * Offset: 0x250 TDES Key 2 High Word Register for Channel 1
\r
861 * ---------------------------------------------------------------------------------------------------
\r
862 * |Bits |Field |Descriptions
\r
863 * | :----: | :----: | :---- |
\r
864 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
865 * | | |The key registers for TDES/DES algorithm calculation
\r
866 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
867 * | | |Thus, it needs two 32-bit registers to store a security key
\r
868 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
869 * @var CRPT_T::TDES1_KEY2L
\r
870 * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1
\r
871 * ---------------------------------------------------------------------------------------------------
\r
872 * |Bits |Field |Descriptions
\r
873 * | :----: | :----: | :---- |
\r
874 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
875 * | | |The key registers for TDES/DES algorithm calculation
\r
876 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
877 * | | |Thus, it needs two 32-bit registers to store a security key
\r
878 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
879 * @var CRPT_T::TDES1_KEY3H
\r
880 * Offset: 0x258 TDES Key 3 High Word Register for Channel 1
\r
881 * ---------------------------------------------------------------------------------------------------
\r
882 * |Bits |Field |Descriptions
\r
883 * | :----: | :----: | :---- |
\r
884 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
885 * | | |The key registers for TDES/DES algorithm calculation
\r
886 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
887 * | | |Thus, it needs two 32-bit registers to store a security key
\r
888 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
889 * @var CRPT_T::TDES1_KEY3L
\r
890 * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1
\r
891 * ---------------------------------------------------------------------------------------------------
\r
892 * |Bits |Field |Descriptions
\r
893 * | :----: | :----: | :---- |
\r
894 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
895 * | | |The key registers for TDES/DES algorithm calculation
\r
896 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
897 * | | |Thus, it needs two 32-bit registers to store a security key
\r
898 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
899 * @var CRPT_T::TDES1_IVH
\r
900 * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1
\r
901 * ---------------------------------------------------------------------------------------------------
\r
902 * |Bits |Field |Descriptions
\r
903 * | :----: | :----: | :---- |
\r
904 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word
\r
905 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
\r
906 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
\r
907 * @var CRPT_T::TDES1_IVL
\r
908 * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1
\r
909 * ---------------------------------------------------------------------------------------------------
\r
910 * |Bits |Field |Descriptions
\r
911 * | :----: | :----: | :---- |
\r
912 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word
\r
913 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
\r
914 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
\r
915 * @var CRPT_T::TDES1_SADDR
\r
916 * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1
\r
917 * ---------------------------------------------------------------------------------------------------
\r
918 * |Bits |Field |Descriptions
\r
919 * | :----: | :----: | :---- |
\r
920 * |[31:0] |SA |TDES/DES DMA Source Address
\r
921 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
\r
922 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
\r
923 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
\r
924 * | | |The start of source address should be located at word boundary
\r
925 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
\r
926 * | | |CRPT_TDESn_SA can be read and written
\r
927 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
928 * | | |But the value of CRPT_TDESn_SA will be updated later on
\r
929 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
\r
930 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
\r
931 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
\r
932 * @var CRPT_T::TDES1_DADDR
\r
933 * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1
\r
934 * ---------------------------------------------------------------------------------------------------
\r
935 * |Bits |Field |Descriptions
\r
936 * | :----: | :----: | :---- |
\r
937 * |[31:0] |DA |TDES/DES DMA Destination Address
\r
938 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
\r
939 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
\r
940 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
\r
941 * | | |The start of destination address should be located at word boundary
\r
942 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
\r
943 * | | |CRPT_TDESn_DA can be read and written
\r
944 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
945 * | | |But the value of CRPT_TDESn_DA will be updated later on
\r
946 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
\r
947 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
\r
948 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
\r
949 * @var CRPT_T::TDES1_CNT
\r
950 * Offset: 0x270 TDES/DES Byte Count Register for Channel 1
\r
951 * ---------------------------------------------------------------------------------------------------
\r
952 * |Bits |Field |Descriptions
\r
953 * | :----: | :----: | :---- |
\r
954 * |[31:0] |CNT |TDES/DES Byte Count
\r
955 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
\r
956 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
\r
957 * | | |CRPT_TDESn_CNT can be read and written
\r
958 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
959 * | | |But the value of CRPT_TDESn_CNT will be updated later on
\r
960 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
\r
961 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
\r
962 * @var CRPT_T::TDES2_KEY1H
\r
963 * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2
\r
964 * ---------------------------------------------------------------------------------------------------
\r
965 * |Bits |Field |Descriptions
\r
966 * | :----: | :----: | :---- |
\r
967 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
968 * | | |The key registers for TDES/DES algorithm calculation
\r
969 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
970 * | | |Thus, it needs two 32-bit registers to store a security key
\r
971 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
972 * @var CRPT_T::TDES2_KEY1L
\r
973 * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2
\r
974 * ---------------------------------------------------------------------------------------------------
\r
975 * |Bits |Field |Descriptions
\r
976 * | :----: | :----: | :---- |
\r
977 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
978 * | | |The key registers for TDES/DES algorithm calculation
\r
979 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
980 * | | |Thus, it needs two 32-bit registers to store a security key
\r
981 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
982 * @var CRPT_T::TDES2_KEY2H
\r
983 * Offset: 0x290 TDES Key 2 High Word Register for Channel 2
\r
984 * ---------------------------------------------------------------------------------------------------
\r
985 * |Bits |Field |Descriptions
\r
986 * | :----: | :----: | :---- |
\r
987 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
988 * | | |The key registers for TDES/DES algorithm calculation
\r
989 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
990 * | | |Thus, it needs two 32-bit registers to store a security key
\r
991 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
992 * @var CRPT_T::TDES2_KEY2L
\r
993 * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2
\r
994 * ---------------------------------------------------------------------------------------------------
\r
995 * |Bits |Field |Descriptions
\r
996 * | :----: | :----: | :---- |
\r
997 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
998 * | | |The key registers for TDES/DES algorithm calculation
\r
999 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
1000 * | | |Thus, it needs two 32-bit registers to store a security key
\r
1001 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
1002 * @var CRPT_T::TDES2_KEY3H
\r
1003 * Offset: 0x298 TDES Key 3 High Word Register for Channel 2
\r
1004 * ---------------------------------------------------------------------------------------------------
\r
1005 * |Bits |Field |Descriptions
\r
1006 * | :----: | :----: | :---- |
\r
1007 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
1008 * | | |The key registers for TDES/DES algorithm calculation
\r
1009 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
1010 * | | |Thus, it needs two 32-bit registers to store a security key
\r
1011 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
1012 * @var CRPT_T::TDES2_KEY3L
\r
1013 * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2
\r
1014 * ---------------------------------------------------------------------------------------------------
\r
1015 * |Bits |Field |Descriptions
\r
1016 * | :----: | :----: | :---- |
\r
1017 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
1018 * | | |The key registers for TDES/DES algorithm calculation
\r
1019 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
1020 * | | |Thus, it needs two 32-bit registers to store a security key
\r
1021 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
1022 * @var CRPT_T::TDES2_IVH
\r
1023 * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2
\r
1024 * ---------------------------------------------------------------------------------------------------
\r
1025 * |Bits |Field |Descriptions
\r
1026 * | :----: | :----: | :---- |
\r
1027 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word
\r
1028 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
\r
1029 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
\r
1030 * @var CRPT_T::TDES2_IVL
\r
1031 * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2
\r
1032 * ---------------------------------------------------------------------------------------------------
\r
1033 * |Bits |Field |Descriptions
\r
1034 * | :----: | :----: | :---- |
\r
1035 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word
\r
1036 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
\r
1037 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
\r
1038 * @var CRPT_T::TDES2_SADDR
\r
1039 * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2
\r
1040 * ---------------------------------------------------------------------------------------------------
\r
1041 * |Bits |Field |Descriptions
\r
1042 * | :----: | :----: | :---- |
\r
1043 * |[31:0] |SA |TDES/DES DMA Source Address
\r
1044 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
\r
1045 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
\r
1046 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
\r
1047 * | | |The start of source address should be located at word boundary
\r
1048 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
\r
1049 * | | |CRPT_TDESn_SA can be read and written
\r
1050 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
1051 * | | |But the value of CRPT_TDESn_SA will be updated later on
\r
1052 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
\r
1053 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
\r
1054 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
\r
1055 * @var CRPT_T::TDES2_DADDR
\r
1056 * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2
\r
1057 * ---------------------------------------------------------------------------------------------------
\r
1058 * |Bits |Field |Descriptions
\r
1059 * | :----: | :----: | :---- |
\r
1060 * |[31:0] |DA |TDES/DES DMA Destination Address
\r
1061 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
\r
1062 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
\r
1063 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
\r
1064 * | | |The start of destination address should be located at word boundary
\r
1065 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
\r
1066 * | | |CRPT_TDESn_DA can be read and written
\r
1067 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
1068 * | | |But the value of CRPT_TDESn_DA will be updated later on
\r
1069 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
\r
1070 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
\r
1071 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
\r
1072 * @var CRPT_T::TDES2_CNT
\r
1073 * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2
\r
1074 * ---------------------------------------------------------------------------------------------------
\r
1075 * |Bits |Field |Descriptions
\r
1076 * | :----: | :----: | :---- |
\r
1077 * |[31:0] |CNT |TDES/DES Byte Count
\r
1078 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
\r
1079 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
\r
1080 * | | |CRPT_TDESn_CNT can be read and written
\r
1081 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
1082 * | | |But the value of CRPT_TDESn_CNT will be updated later on
\r
1083 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
\r
1084 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
\r
1085 * @var CRPT_T::TDES3_KEY1H
\r
1086 * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3
\r
1087 * ---------------------------------------------------------------------------------------------------
\r
1088 * |Bits |Field |Descriptions
\r
1089 * | :----: | :----: | :---- |
\r
1090 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
1091 * | | |The key registers for TDES/DES algorithm calculation
\r
1092 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
1093 * | | |Thus, it needs two 32-bit registers to store a security key
\r
1094 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
1095 * @var CRPT_T::TDES3_KEY1L
\r
1096 * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3
\r
1097 * ---------------------------------------------------------------------------------------------------
\r
1098 * |Bits |Field |Descriptions
\r
1099 * | :----: | :----: | :---- |
\r
1100 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
1101 * | | |The key registers for TDES/DES algorithm calculation
\r
1102 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
1103 * | | |Thus, it needs two 32-bit registers to store a security key
\r
1104 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
1105 * @var CRPT_T::TDES3_KEY2H
\r
1106 * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3
\r
1107 * ---------------------------------------------------------------------------------------------------
\r
1108 * |Bits |Field |Descriptions
\r
1109 * | :----: | :----: | :---- |
\r
1110 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
1111 * | | |The key registers for TDES/DES algorithm calculation
\r
1112 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
1113 * | | |Thus, it needs two 32-bit registers to store a security key
\r
1114 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
1115 * @var CRPT_T::TDES3_KEY2L
\r
1116 * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3
\r
1117 * ---------------------------------------------------------------------------------------------------
\r
1118 * |Bits |Field |Descriptions
\r
1119 * | :----: | :----: | :---- |
\r
1120 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
1121 * | | |The key registers for TDES/DES algorithm calculation
\r
1122 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
1123 * | | |Thus, it needs two 32-bit registers to store a security key
\r
1124 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
1125 * @var CRPT_T::TDES3_KEY3H
\r
1126 * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3
\r
1127 * ---------------------------------------------------------------------------------------------------
\r
1128 * |Bits |Field |Descriptions
\r
1129 * | :----: | :----: | :---- |
\r
1130 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
1131 * | | |The key registers for TDES/DES algorithm calculation
\r
1132 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
1133 * | | |Thus, it needs two 32-bit registers to store a security key
\r
1134 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
1135 * @var CRPT_T::TDES3_KEY3L
\r
1136 * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3
\r
1137 * ---------------------------------------------------------------------------------------------------
\r
1138 * |Bits |Field |Descriptions
\r
1139 * | :----: | :----: | :---- |
\r
1140 * |[31:0] |KEY |TDES/DES Key High/Low Word
\r
1141 * | | |The key registers for TDES/DES algorithm calculation
\r
1142 * | | |The security key for the TDES/DES accelerator is 64 bits
\r
1143 * | | |Thus, it needs two 32-bit registers to store a security key
\r
1144 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
\r
1145 * @var CRPT_T::TDES3_IVH
\r
1146 * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3
\r
1147 * ---------------------------------------------------------------------------------------------------
\r
1148 * |Bits |Field |Descriptions
\r
1149 * | :----: | :----: | :---- |
\r
1150 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word
\r
1151 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
\r
1152 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
\r
1153 * @var CRPT_T::TDES3_IVL
\r
1154 * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3
\r
1155 * ---------------------------------------------------------------------------------------------------
\r
1156 * |Bits |Field |Descriptions
\r
1157 * | :----: | :----: | :---- |
\r
1158 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word
\r
1159 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode
\r
1160 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
\r
1161 * @var CRPT_T::TDES3_SADDR
\r
1162 * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3
\r
1163 * ---------------------------------------------------------------------------------------------------
\r
1164 * |Bits |Field |Descriptions
\r
1165 * | :----: | :----: | :---- |
\r
1166 * |[31:0] |SA |TDES/DES DMA Source Address
\r
1167 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
\r
1168 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored
\r
1169 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation
\r
1170 * | | |The start of source address should be located at word boundary
\r
1171 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored.
\r
1172 * | | |CRPT_TDESn_SA can be read and written
\r
1173 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
1174 * | | |But the value of CRPT_TDESn_SA will be updated later on
\r
1175 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
\r
1176 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START.
\r
1177 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value.
\r
1178 * @var CRPT_T::TDES3_DADDR
\r
1179 * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3
\r
1180 * ---------------------------------------------------------------------------------------------------
\r
1181 * |Bits |Field |Descriptions
\r
1182 * | :----: | :----: | :---- |
\r
1183 * |[31:0] |DA |TDES/DES DMA Destination Address
\r
1184 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO
\r
1185 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored
\r
1186 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished
\r
1187 * | | |The start of destination address should be located at word boundary
\r
1188 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored.
\r
1189 * | | |CRPT_TDESn_DA can be read and written
\r
1190 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
1191 * | | |But the value of CRPT_TDESn_DA will be updated later on
\r
1192 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
\r
1193 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START.
\r
1194 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value.
\r
1195 * @var CRPT_T::TDES3_CNT
\r
1196 * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3
\r
1197 * ---------------------------------------------------------------------------------------------------
\r
1198 * |Bits |Field |Descriptions
\r
1199 * | :----: | :----: | :---- |
\r
1200 * |[31:0] |CNT |TDES/DES Byte Count
\r
1201 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode
\r
1202 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.
\r
1203 * | | |CRPT_TDESn_CNT can be read and written
\r
1204 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation
\r
1205 * | | |But the value of CRPT_TDESn_CNT will be updated later on
\r
1206 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
\r
1207 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
\r
1208 * @var CRPT_T::HMAC_CTL
\r
1209 * Offset: 0x300 SHA/HMAC Control Register
\r
1210 * ---------------------------------------------------------------------------------------------------
\r
1211 * |Bits |Field |Descriptions
\r
1212 * | :----: | :----: | :---- |
\r
1213 * |[0] |START |SHA/HMAC Engine Start
\r
1214 * | | |0 = No effect.
\r
1215 * | | |1 = Start SHA/HMAC engine. BUSY flag will be set.
\r
1216 * | | |This bit is always 0 when it's read back.
\r
1217 * |[1] |STOP |SHA/HMAC Engine Stop
\r
1218 * | | |0 = No effect.
\r
1219 * | | |1 = Stop SHA/HMAC engine.
\r
1220 * | | |This bit is always 0 when it's read back.
\r
1221 * |[5] |DMALAST |SHA/HMAC Last Block
\r
1222 * | | |This bit must be set as feeding in last byte of data.
\r
1223 * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Control
\r
1224 * | | |0 = SHA/HMAC DMA engine Disabled.
\r
1225 * | | |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN.
\r
1226 * | | |1 = SHA/HMAC DMA engine Enabled.
\r
1227 * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
\r
1228 * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes
\r
1229 * | | |0x0xx: SHA160
\r
1230 * | | |0x100: SHA256
\r
1231 * | | |0x101: SHA224
\r
1232 * | | |0x110: SHA512
\r
1233 * | | |0x111: SHA384
\r
1234 * | | |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1.
\r
1235 * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap
\r
1236 * | | |0 = Keep the original order.
\r
1237 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
\r
1238 * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap
\r
1239 * | | |0 = Keep the original order.
\r
1240 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
\r
1241 * @var CRPT_T::HMAC_STS
\r
1242 * Offset: 0x304 SHA/HMAC Status Flag
\r
1243 * ---------------------------------------------------------------------------------------------------
\r
1244 * |Bits |Field |Descriptions
\r
1245 * | :----: | :----: | :---- |
\r
1246 * |[0] |BUSY |SHA/HMAC Engine Busy
\r
1247 * | | |0 = SHA/HMAC engine is idle or finished.
\r
1248 * | | |1 = SHA/HMAC engine is busy.
\r
1249 * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag
\r
1250 * | | |0 = SHA/HMAC DMA engine is idle or finished.
\r
1251 * | | |1 = SHA/HMAC DMA engine is busy.
\r
1252 * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag
\r
1253 * | | |0 = Show the SHA/HMAC engine access normal.
\r
1254 * | | |1 = Show the SHA/HMAC engine access error.
\r
1255 * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request
\r
1256 * | | |0 = No effect.
\r
1257 * | | |1 = Request SHA/HMAC Non-DMA mode data input.
\r
1258 * @var CRPT_T::HMAC_DGST[16]
\r
1259 * Offset: 0x308~0x344 SHA/HMAC Digest Message 0~15
\r
1260 * ---------------------------------------------------------------------------------------------------
\r
1261 * |Bits |Field |Descriptions
\r
1262 * | :----: | :----: | :---- |
\r
1263 * |[31:0] |DGST |SHA/HMAC Digest Message Output Register
\r
1264 * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4.
\r
1265 * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6.
\r
1266 * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7.
\r
1267 * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11.
\r
1268 * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15.
\r
1269 * @var CRPT_T::HMAC_KEYCNT
\r
1270 * Offset: 0x348 SHA/HMAC Key Byte Count Register
\r
1271 * ---------------------------------------------------------------------------------------------------
\r
1272 * |Bits |Field |Descriptions
\r
1273 * | :----: | :----: | :---- |
\r
1274 * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count
\r
1275 * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates
\r
1276 * | | |The register is 32-bit and the maximum byte count is 4G bytes
\r
1277 * | | |It can be read and written.
\r
1278 * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation
\r
1279 * | | |But the value of CRPT_SHA _KEYCNT will be updated later on
\r
1280 * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation.
\r
1281 * @var CRPT_T::HMAC_SADDR
\r
1282 * Offset: 0x34C SHA/HMAC DMA Source Address Register
\r
1283 * ---------------------------------------------------------------------------------------------------
\r
1284 * |Bits |Field |Descriptions
\r
1285 * | :----: | :----: | :---- |
\r
1286 * |[31:0] |SADDR |SHA/HMAC DMA Source Address
\r
1287 * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO
\r
1288 * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored
\r
1289 * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation
\r
1290 * | | |The start of source address should be located at word boundary
\r
1291 * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored.
\r
1292 * | | |CRPT_HMAC_SADDR can be read and written
\r
1293 * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
\r
1294 * | | |But the value of CRPT_HMAC_SADDR will be updated later on
\r
1295 * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation.
\r
1296 * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START.
\r
1297 * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value.
\r
1298 * @var CRPT_T::HMAC_DMACNT
\r
1299 * Offset: 0x350 SHA/HMAC Byte Count Register
\r
1300 * ---------------------------------------------------------------------------------------------------
\r
1301 * |Bits |Field |Descriptions
\r
1302 * | :----: | :----: | :---- |
\r
1303 * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count
\r
1304 * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode
\r
1305 * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
\r
1306 * | | |CRPT_HMAC_DMACNT can be read and written
\r
1307 * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation
\r
1308 * | | |But the value of CRPT_HMAC_DMACNT will be updated later on
\r
1309 * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation.
\r
1310 * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
\r
1311 * @var CRPT_T::HMAC_DATIN
\r
1312 * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register
\r
1313 * ---------------------------------------------------------------------------------------------------
\r
1314 * |Bits |Field |Descriptions
\r
1315 * | :----: | :----: | :---- |
\r
1316 * |[31:0] |DATIN |SHA/HMAC Engine Input Port
\r
1317 * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS
\r
1318 * | | |Feed data as DATINREQ is 1.
\r
1319 * @var CRPT_T::ECC_CTL
\r
1320 * Offset: 0x800 ECC Control Register
\r
1321 * ---------------------------------------------------------------------------------------------------
\r
1322 * |Bits |Field |Descriptions
\r
1323 * | :----: | :----: | :---- |
\r
1324 * |[0] |START |ECC Accelerator Start
\r
1325 * | | |0 = No effect.
\r
1326 * | | |1 = Start ECC accelerator. BUSY flag will be set.
\r
1327 * | | |This bit is always 0 when it's read back.
\r
1328 * | | |ECC accelerator will ignore this START signal when BUSY flag is 1.
\r
1329 * |[1] |STOP |ECC Accelerator Stop
\r
1330 * | | |0 = No effect.
\r
1331 * | | |1 = Abort ECC accelerator and make it into idle state.
\r
1332 * | | |This bit is always 0 when it's read back.
\r
1333 * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator.
\r
1334 * |[7] |DMAEN |ECC Accelerator DMA Enable Control
\r
1335 * | | |0 = ECC DMA engine Disabled.
\r
1336 * | | |1 = ECC DMA engine Enabled.
\r
1337 * | | |Only when START and DMAEN are 1, ECC DMA engine will be active
\r
1338 * |[8] |FSEL |Field Selection
\r
1339 * | | |0 = Binary Field (GF(2m )).
\r
1340 * | | |1 = Prime Field (GF(p)).
\r
1341 * |[10:9] |ECCOP |Point Operation for BF and PF
\r
1342 * | | |00 = Point multiplication :
\r
1343 * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1).
\r
1344 * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]).
\r
1345 * | | |10 = Point addition :
\r
1346 * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +.
\r
1347 * | | |(POINTX2, POINTY2)
\r
1348 * | | |11 = Point doubling :
\r
1349 * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1).
\r
1350 * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11
\r
1351 * |[12:11] |MODOP |Modulus Operation for PF
\r
1352 * | | |00 = Division :
\r
1353 * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN.
\r
1354 * | | |01 = Multiplication :
\r
1355 * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN.
\r
1356 * | | |10 = Addition :
\r
1357 * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN.
\r
1358 * | | |11 = Subtraction :
\r
1359 * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN.
\r
1360 * | | |MODOP is active only when ECCOP = 01.
\r
1361 * |[16] |LDP1 |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1)
\r
1362 * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user.
\r
1363 * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user.
\r
1364 * |[17] |LDP2 |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2)
\r
1365 * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user.
\r
1366 * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user.
\r
1367 * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve
\r
1368 * | | |0 = The register for CURVEA is not modified by DMA or user.
\r
1369 * | | |1 = The register for CURVEA is modified by DMA or user.
\r
1370 * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve
\r
1371 * | | |0 = The register for CURVEB is not modified by DMA or user.
\r
1372 * | | |1 = The register for CURVEB is modified by DMA or user.
\r
1373 * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve
\r
1374 * | | |0 = The register for CURVEN is not modified by DMA or user.
\r
1375 * | | |1 = The register for CURVEN is modified by DMA or user.
\r
1376 * |[21] |LDK |The Control Signal of Register for SCALARK
\r
1377 * | | |0 = The register for SCALARK is not modified by DMA or user.
\r
1378 * | | |1 = The register for SCALARK is modified by DMA or user.
\r
1379 * |[31:22] |CURVEM |The key length of elliptic curve.
\r
1380 * @var CRPT_T::ECC_STS
\r
1381 * Offset: 0x804 ECC Status Register
\r
1382 * ---------------------------------------------------------------------------------------------------
\r
1383 * |Bits |Field |Descriptions
\r
1384 * | :----: | :----: | :---- |
\r
1385 * |[0] |BUSY |ECC Accelerator Busy Flag
\r
1386 * | | |0 = The ECC accelerator is idle or finished.
\r
1387 * | | |1 = The ECC accelerator is under processing and protects all registers.
\r
1388 * | | |Remember to clear ECC interrupt flag after ECC accelerator finished
\r
1389 * |[1] |DMABUSY |ECC DMA Busy Flag
\r
1390 * | | |0 = ECC DMA is idle or finished.
\r
1391 * | | |1 = ECC DMA is busy.
\r
1392 * |[16] |BUSERR |ECC DMA Access Bus Error Flag
\r
1393 * | | |0 = No error.
\r
1394 * | | |1 = Bus error will stop DMA operation and ECC accelerator.
\r
1395 * @var CRPT_T::ECC_X1[18]
\r
1396 * Offset: 0x808~0x84C ECC The X-coordinate word 0~17 of the first point
\r
1397 * ---------------------------------------------------------------------------------------------------
\r
1398 * |Bits |Field |Descriptions
\r
1399 * | :----: | :----: | :---- |
\r
1400 * |[31:0] |POINTX1 |ECC the x-coordinate Value of the First Point (POINTX1)
\r
1401 * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
\r
1402 * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
\r
1403 * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08
\r
1404 * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12
\r
1405 * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17
\r
1406 * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
\r
1407 * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06
\r
1408 * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
\r
1409 * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11
\r
1410 * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16
\r
1411 * @var CRPT_T::ECC_Y1[18]
\r
1412 * Offset: 0x850~0x894 ECC The Y-coordinate word 0~17 of the first point
\r
1413 * ---------------------------------------------------------------------------------------------------
\r
1414 * |Bits |Field |Descriptions
\r
1415 * | :----: | :----: | :---- |
\r
1416 * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point (POINTY1)
\r
1417 * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
\r
1418 * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
\r
1419 * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08
\r
1420 * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12
\r
1421 * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17
\r
1422 * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
\r
1423 * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06
\r
1424 * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
\r
1425 * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11
\r
1426 * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16
\r
1427 * @var CRPT_T::ECC_X2[18]
\r
1428 * Offset: 0x898~0x8DC ECC The X-coordinate word 0~17 of the second point
\r
1429 * ---------------------------------------------------------------------------------------------------
\r
1430 * |Bits |Field |Descriptions
\r
1431 * | :----: | :----: | :---- |
\r
1432 * |[31:0] |POINTX2 |ECC the x-coordinate Value of the Second Point (POINTX2)
\r
1433 * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
\r
1434 * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
\r
1435 * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08
\r
1436 * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12
\r
1437 * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17
\r
1438 * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
\r
1439 * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06
\r
1440 * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
\r
1441 * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11
\r
1442 * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16
\r
1443 * @var CRPT_T::ECC_Y2[18]
\r
1444 * Offset: 0x8E0~0x924 ECC The Y-coordinate word 0~17 of the second point
\r
1445 * ---------------------------------------------------------------------------------------------------
\r
1446 * |Bits |Field |Descriptions
\r
1447 * | :----: | :----: | :---- |
\r
1448 * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point (POINTY2)
\r
1449 * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
\r
1450 * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
\r
1451 * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08
\r
1452 * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12
\r
1453 * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17
\r
1454 * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
\r
1455 * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06
\r
1456 * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
\r
1457 * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11
\r
1458 * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16
\r
1459 * @var CRPT_T::ECC_A[18]
\r
1460 * Offset: 0x928~0x96C ECC The parameter CURVEA word 0~17 of elliptic curve
\r
1461 * ---------------------------------------------------------------------------------------------------
\r
1462 * |Bits |Field |Descriptions
\r
1463 * | :----: | :----: | :---- |
\r
1464 * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)
\r
1465 * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m).
\r
1466 * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
\r
1467 * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
\r
1468 * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08
\r
1469 * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12
\r
1470 * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17
\r
1471 * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
\r
1472 * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06
\r
1473 * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
\r
1474 * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11
\r
1475 * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16
\r
1476 * @var CRPT_T::ECC_B[18]
\r
1477 * Offset: 0x970~0x9B4 ECC The parameter CURVEB word 0~17 of elliptic curve
\r
1478 * ---------------------------------------------------------------------------------------------------
\r
1479 * |Bits |Field |Descriptions
\r
1480 * | :----: | :----: | :---- |
\r
1481 * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)
\r
1482 * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m).
\r
1483 * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
\r
1484 * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
\r
1485 * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08
\r
1486 * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12
\r
1487 * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17
\r
1488 * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
\r
1489 * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06
\r
1490 * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
\r
1491 * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11
\r
1492 * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16
\r
1493 * @var CRPT_T::ECC_N[18]
\r
1494 * Offset: 0x9B8~0x9FC ECC The parameter CURVEN word 0~17 of elliptic curve
\r
1495 * ---------------------------------------------------------------------------------------------------
\r
1496 * |Bits |Field |Descriptions
\r
1497 * | :----: | :----: | :---- |
\r
1498 * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)
\r
1499 * | | |In GF(p), CURVEN is the prime p.
\r
1500 * | | |In GF(2m), CURVEN is the irreducible polynomial.
\r
1501 * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
\r
1502 * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
\r
1503 * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08
\r
1504 * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12
\r
1505 * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17
\r
1506 * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05
\r
1507 * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06
\r
1508 * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07
\r
1509 * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11
\r
1510 * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16
\r
1511 * @var CRPT_T::ECC_K[18]
\r
1512 * Offset: 0xA00~0xA44 ECC The scalar SCALARK word 0~17 of point multiplication
\r
1513 * ---------------------------------------------------------------------------------------------------
\r
1514 * |Bits |Field |Descriptions
\r
1515 * | :----: | :----: | :---- |
\r
1516 * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)
\r
1517 * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK.
\r
1518 * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
\r
1519 * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
\r
1520 * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08
\r
1521 * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12
\r
1522 * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17
\r
1523 * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05
\r
1524 * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06
\r
1525 * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07
\r
1526 * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11
\r
1527 * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16
\r
1528 * @var CRPT_T::ECC_SADDR
\r
1529 * Offset: 0xA48 ECC DMA Source Address Register
\r
1530 * ---------------------------------------------------------------------------------------------------
\r
1531 * |Bits |Field |Descriptions
\r
1532 * | :----: | :----: | :---- |
\r
1533 * @var CRPT_T::ECC_DADDR
\r
1534 * Offset: 0xA4C ECC DMA Destination Address Register
\r
1535 * ---------------------------------------------------------------------------------------------------
\r
1536 * |Bits |Field |Descriptions
\r
1537 * | :----: | :----: | :---- |
\r
1538 * |[31:0] |DADDR |ECC DMA Destination Address
\r
1539 * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator
\r
1540 * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored
\r
1541 * | | |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished
\r
1542 * | | |The start of destination address should be located at word boundary
\r
1543 * | | |That is, bit 1 and 0 of DADDR are ignored
\r
1544 * | | |DADDR can be read and written
\r
1545 * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START
\r
1546 * @var CRPT_T::ECC_STARTREG
\r
1547 * Offset: 0xA50 ECC Starting Address of Updated Registers
\r
1548 * ---------------------------------------------------------------------------------------------------
\r
1549 * |Bits |Field |Descriptions
\r
1550 * | :----: | :----: | :---- |
\r
1551 * |[31:0] |STARTREG |ECC Starting Address of Updated Registers
\r
1552 * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine
\r
1553 * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG
\r
1554 * | | |For example, we want to updated input data from register CRPT_ECC POINTX1
\r
1555 * | | |Thus, the value of STARTREG is 0x808.
\r
1556 * @var CRPT_T::ECC_WORDCNT
\r
1557 * Offset: 0xA54 ECC DMA Word Count
\r
1558 * ---------------------------------------------------------------------------------------------------
\r
1559 * |Bits |Field |Descriptions
\r
1560 * | :----: | :----: | :---- |
\r
1561 * |[31:0] |WORDCNT |ECC DMA Word Count
\r
1562 * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode
\r
1563 * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words
\r
1564 * | | |CRPT_ECC_WORDCNT can be read and written
\r
1566 __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */
\r
1567 __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */
\r
1568 __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */
\r
1569 __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */
\r
1570 __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */
\r
1571 __I uint32_t RESERVE0[8];
\r
1572 __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */
\r
1573 __I uint32_t TDES_FDBCKH; /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */
\r
1574 __I uint32_t TDES_FDBCKL; /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */
\r
1575 __I uint32_t RESERVE1[38];
\r
1576 __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */
\r
1577 __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */
\r
1578 __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */
\r
1579 __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */
\r
1580 __IO uint32_t AES0_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */
\r
1581 __IO uint32_t AES0_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */
\r
1582 __IO uint32_t AES0_SADDR; /*!< [0x0140] AES DMA Source Address Register for Channel 0 */
\r
1583 __IO uint32_t AES0_DADDR; /*!< [0x0144] AES DMA Destination Address Register for Channel 0 */
\r
1584 __IO uint32_t AES0_CNT; /*!< [0x0148] AES Byte Count Register for Channel 0 */
\r
1585 __IO uint32_t AES1_KEY[8]; /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1 */
\r
1586 __IO uint32_t AES1_IV[4]; /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1 */
\r
1587 __IO uint32_t AES1_SADDR; /*!< [0x017c] AES DMA Source Address Register for Channel 1 */
\r
1588 __IO uint32_t AES1_DADDR; /*!< [0x0180] AES DMA Destination Address Register for Channel 1 */
\r
1589 __IO uint32_t AES1_CNT; /*!< [0x0184] AES Byte Count Register for Channel 1 */
\r
1590 __IO uint32_t AES2_KEY[8]; /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2 */
\r
1591 __IO uint32_t AES2_IV[4]; /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2 */
\r
1592 __IO uint32_t AES2_SADDR; /*!< [0x01b8] AES DMA Source Address Register for Channel 2 */
\r
1593 __IO uint32_t AES2_DADDR; /*!< [0x01bc] AES DMA Destination Address Register for Channel 2 */
\r
1594 __IO uint32_t AES2_CNT; /*!< [0x01c0] AES Byte Count Register for Channel 2 */
\r
1595 __IO uint32_t AES3_KEY[8]; /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3 */
\r
1596 __IO uint32_t AES3_IV[4]; /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3 */
\r
1597 __IO uint32_t AES3_SADDR; /*!< [0x01f4] AES DMA Source Address Register for Channel 3 */
\r
1598 __IO uint32_t AES3_DADDR; /*!< [0x01f8] AES DMA Destination Address Register for Channel 3 */
\r
1599 __IO uint32_t AES3_CNT; /*!< [0x01fc] AES Byte Count Register for Channel 3 */
\r
1600 __IO uint32_t TDES_CTL; /*!< [0x0200] TDES/DES Control Register */
\r
1601 __I uint32_t TDES_STS; /*!< [0x0204] TDES/DES Engine Flag */
\r
1602 __IO uint32_t TDES0_KEY1H; /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0 */
\r
1603 __IO uint32_t TDES0_KEY1L; /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0 */
\r
1604 __IO uint32_t TDES0_KEY2H; /*!< [0x0210] TDES Key 2 High Word Register for Channel 0 */
\r
1605 __IO uint32_t TDES0_KEY2L; /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0 */
\r
1606 __IO uint32_t TDES0_KEY3H; /*!< [0x0218] TDES Key 3 High Word Register for Channel 0 */
\r
1607 __IO uint32_t TDES0_KEY3L; /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0 */
\r
1608 __IO uint32_t TDES0_IVH; /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0 */
\r
1609 __IO uint32_t TDES0_IVL; /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0 */
\r
1610 __IO uint32_t TDES0_SADDR; /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0 */
\r
1611 __IO uint32_t TDES0_DADDR; /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0 */
\r
1612 __IO uint32_t TDES0_CNT; /*!< [0x0230] TDES/DES Byte Count Register for Channel 0 */
\r
1613 __IO uint32_t TDES_DATIN; /*!< [0x0234] TDES/DES Engine Input data Word Register */
\r
1614 __I uint32_t TDES_DATOUT; /*!< [0x0238] TDES/DES Engine Output data Word Register */
\r
1615 __I uint32_t RESERVE2[3];
\r
1616 __IO uint32_t TDES1_KEY1H; /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1 */
\r
1617 __IO uint32_t TDES1_KEY1L; /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1 */
\r
1618 __IO uint32_t TDES1_KEY2H; /*!< [0x0250] TDES Key 2 High Word Register for Channel 1 */
\r
1619 __IO uint32_t TDES1_KEY2L; /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1 */
\r
1620 __IO uint32_t TDES1_KEY3H; /*!< [0x0258] TDES Key 3 High Word Register for Channel 1 */
\r
1621 __IO uint32_t TDES1_KEY3L; /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1 */
\r
1622 __IO uint32_t TDES1_IVH; /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1 */
\r
1623 __IO uint32_t TDES1_IVL; /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1 */
\r
1624 __IO uint32_t TDES1_SADDR; /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1 */
\r
1625 __IO uint32_t TDES1_DADDR; /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1 */
\r
1626 __IO uint32_t TDES1_CNT; /*!< [0x0270] TDES/DES Byte Count Register for Channel 1 */
\r
1627 __I uint32_t RESERVE3[5];
\r
1628 __IO uint32_t TDES2_KEY1H; /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2 */
\r
1629 __IO uint32_t TDES2_KEY1L; /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2 */
\r
1630 __IO uint32_t TDES2_KEY2H; /*!< [0x0290] TDES Key 2 High Word Register for Channel 2 */
\r
1631 __IO uint32_t TDES2_KEY2L; /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2 */
\r
1632 __IO uint32_t TDES2_KEY3H; /*!< [0x0298] TDES Key 3 High Word Register for Channel 2 */
\r
1633 __IO uint32_t TDES2_KEY3L; /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2 */
\r
1634 __IO uint32_t TDES2_IVH; /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2 */
\r
1635 __IO uint32_t TDES2_IVL; /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2 */
\r
1636 __IO uint32_t TDES2_SADDR; /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2 */
\r
1637 __IO uint32_t TDES2_DADDR; /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2 */
\r
1638 __IO uint32_t TDES2_CNT; /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2 */
\r
1639 __I uint32_t RESERVE4[5];
\r
1640 __IO uint32_t TDES3_KEY1H; /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3 */
\r
1641 __IO uint32_t TDES3_KEY1L; /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3 */
\r
1642 __IO uint32_t TDES3_KEY2H; /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3 */
\r
1643 __IO uint32_t TDES3_KEY2L; /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3 */
\r
1644 __IO uint32_t TDES3_KEY3H; /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3 */
\r
1645 __IO uint32_t TDES3_KEY3L; /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3 */
\r
1646 __IO uint32_t TDES3_IVH; /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3 */
\r
1647 __IO uint32_t TDES3_IVL; /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3 */
\r
1648 __IO uint32_t TDES3_SADDR; /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3 */
\r
1649 __IO uint32_t TDES3_DADDR; /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3 */
\r
1650 __IO uint32_t TDES3_CNT; /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3 */
\r
1651 __I uint32_t RESERVE5[3];
\r
1652 __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */
\r
1653 __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */
\r
1654 __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */
\r
1655 __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */
\r
1656 __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */
\r
1657 __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */
\r
1658 __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */
\r
1659 __I uint32_t RESERVE6[298];
\r
1660 __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */
\r
1661 __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */
\r
1662 __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point */
\r
1663 __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */
\r
1664 __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */
\r
1665 __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */
\r
1666 __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */
\r
1667 __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */
\r
1668 __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */
\r
1669 __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */
\r
1670 __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */
\r
1671 __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */
\r
1672 __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */
\r
1673 __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */
\r
1678 @addtogroup CRPT_CONST CRPT Bit Field Definition
\r
1679 Constant Definitions for CRPT Controller
\r
1682 #define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */
\r
1683 #define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */
\r
1685 #define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */
\r
1686 #define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */
\r
1688 #define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT_T::INTEN: TDESIEN Position */
\r
1689 #define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT_T::INTEN: TDESIEN Mask */
\r
1691 #define CRPT_INTEN_TDESEIEN_Pos (9) /*!< CRPT_T::INTEN: TDESEIEN Position */
\r
1692 #define CRPT_INTEN_TDESEIEN_Msk (0x1ul << CRPT_INTEN_TDESEIEN_Pos) /*!< CRPT_T::INTEN: TDESEIEN Mask */
\r
1694 #define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */
\r
1695 #define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */
\r
1697 #define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */
\r
1698 #define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */
\r
1700 #define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */
\r
1701 #define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */
\r
1703 #define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */
\r
1704 #define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */
\r
1706 #define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */
\r
1707 #define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */
\r
1709 #define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */
\r
1710 #define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */
\r
1712 #define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */
\r
1713 #define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */
\r
1715 #define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT_T::INTSTS: TDESIF Position */
\r
1716 #define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT_T::INTSTS: TDESIF Mask */
\r
1718 #define CRPT_INTSTS_TDESEIF_Pos (9) /*!< CRPT_T::INTSTS: TDESEIF Position */
\r
1719 #define CRPT_INTSTS_TDESEIF_Msk (0x1ul << CRPT_INTSTS_TDESEIF_Pos) /*!< CRPT_T::INTSTS: TDESEIF Mask */
\r
1721 #define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */
\r
1722 #define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */
\r
1724 #define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */
\r
1725 #define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */
\r
1727 #define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */
\r
1728 #define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */
\r
1730 #define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */
\r
1731 #define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */
\r
1733 #define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */
\r
1734 #define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */
\r
1736 #define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */
\r
1737 #define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */
\r
1739 #define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */
\r
1740 #define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */
\r
1742 #define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */
\r
1743 #define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */
\r
1745 #define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */
\r
1746 #define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */
\r
1748 #define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */
\r
1749 #define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */
\r
1751 #define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */
\r
1752 #define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY[8]: KEY Mask */
\r
1754 #define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */
\r
1755 #define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */
\r
1757 #define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKH: FDBCK Position */
\r
1758 #define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask */
\r
1760 #define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKL: FDBCK Position */
\r
1761 #define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask */
\r
1763 #define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */
\r
1764 #define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */
\r
1766 #define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */
\r
1767 #define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */
\r
1769 #define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */
\r
1770 #define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */
\r
1772 #define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */
\r
1773 #define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */
\r
1775 #define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */
\r
1776 #define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */
\r
1778 #define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */
\r
1779 #define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */
\r
1781 #define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */
\r
1782 #define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */
\r
1784 #define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */
\r
1785 #define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */
\r
1787 #define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */
\r
1788 #define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */
\r
1790 #define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */
\r
1791 #define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */
\r
1793 #define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::AES_CTL: CHANNEL Position */
\r
1794 #define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT_T::AES_CTL: CHANNEL Mask */
\r
1796 #define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */
\r
1797 #define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */
\r
1799 #define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */
\r
1800 #define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */
\r
1802 #define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */
\r
1803 #define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */
\r
1805 #define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */
\r
1806 #define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */
\r
1808 #define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */
\r
1809 #define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */
\r
1811 #define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */
\r
1812 #define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */
\r
1814 #define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */
\r
1815 #define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */
\r
1817 #define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */
\r
1818 #define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */
\r
1820 #define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */
\r
1821 #define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */
\r
1823 #define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */
\r
1824 #define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */
\r
1826 #define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */
\r
1827 #define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */
\r
1829 #define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */
\r
1830 #define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */
\r
1832 #define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */
\r
1833 #define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */
\r
1835 #define CRPT_AES0_KEYx_KEY_Pos (0) /*!< CRPT_T::AES0_KEY[8]: KEY Position */
\r
1836 #define CRPT_AES0_KEYx_KEY_Msk (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos) /*!< CRPT_T::AES0_KEY[8]: KEY Mask */
\r
1838 #define CRPT_AES0_IVx_IV_Pos (0) /*!< CRPT_T::AES0_IV[4]: IV Position */
\r
1839 #define CRPT_AES0_IVx_IV_Msk (0xfffffffful << CRPT_AES0_IVx_IV_Pos) /*!< CRPT_T::AES0_IV[4]: IV Mask */
\r
1841 #define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES0_SADDR: SADDR Position */
\r
1842 #define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT_T::AES0_SADDR: SADDR Mask */
\r
1844 #define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES0_DADDR: DADDR Position */
\r
1845 #define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT_T::AES0_DADDR: DADDR Mask */
\r
1847 #define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT_T::AES0_CNT: CNT Position */
\r
1848 #define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT_T::AES0_CNT: CNT Mask */
\r
1850 #define CRPT_AES1_KEYx_KEY_Pos (0) /*!< CRPT_T::AES1_KEY[8]: KEY Position */
\r
1851 #define CRPT_AES1_KEYx_KEY_Msk (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos) /*!< CRPT_T::AES1_KEY[8]: KEY Mask */
\r
1853 #define CRPT_AES1_IVx_IV_Pos (0) /*!< CRPT_T::AES1_IV[4]: IV Position */
\r
1854 #define CRPT_AES1_IVx_IV_Msk (0xfffffffful << CRPT_AES1_IVx_IV_Pos) /*!< CRPT_T::AES1_IV[4]: IV Mask */
\r
1856 #define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES1_SADDR: SADDR Position */
\r
1857 #define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT_T::AES1_SADDR: SADDR Mask */
\r
1859 #define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES1_DADDR: DADDR Position */
\r
1860 #define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT_T::AES1_DADDR: DADDR Mask */
\r
1862 #define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT_T::AES1_CNT: CNT Position */
\r
1863 #define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT_T::AES1_CNT: CNT Mask */
\r
1865 #define CRPT_AES2_KEYx_KEY_Pos (0) /*!< CRPT_T::AES2_KEYx: KEY Position */
\r
1866 #define CRPT_AES2_KEYx_KEY_Msk (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos) /*!< CRPT_T::AES2_KEYx: KEY Mask */
\r
1868 #define CRPT_AES2_IVx_IV_Pos (0) /*!< CRPT_T::AES2_IVx: IV Position */
\r
1869 #define CRPT_AES2_IVx_IV_Msk (0xfffffffful << CRPT_AES2_IVx_IV_Pos) /*!< CRPT_T::AES2_IVx: IV Mask */
\r
1871 #define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES2_SADDR: SADDR Position */
\r
1872 #define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT_T::AES2_SADDR: SADDR Mask */
\r
1874 #define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES2_DADDR: DADDR Position */
\r
1875 #define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT_T::AES2_DADDR: DADDR Mask */
\r
1877 #define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT_T::AES2_CNT: CNT Position */
\r
1878 #define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT_T::AES2_CNT: CNT Mask */
\r
1880 #define CRPT_AES3_KEYx_KEY_Pos (0) /*!< CRPT_T::AES3_KEY[8]: KEY Position */
\r
1881 #define CRPT_AES3_KEYx_KEY_Msk (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos) /*!< CRPT_T::AES3_KEY[8]: KEY Mask */
\r
1883 #define CRPT_AES3_IVx_IV_Pos (0) /*!< CRPT_T::AES3_IV[4]: IV Position */
\r
1884 #define CRPT_AES3_IVx_IV_Msk (0xfffffffful << CRPT_AES3_IVx_IV_Pos) /*!< CRPT_T::AES3_IV[4]: IV Mask */
\r
1886 #define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES3_SADDR: SADDR Position */
\r
1887 #define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT_T::AES3_SADDR: SADDR Mask */
\r
1889 #define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES3_DADDR: DADDR Position */
\r
1890 #define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT_T::AES3_DADDR: DADDR Mask */
\r
1892 #define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT_T::AES3_CNT: CNT Position */
\r
1893 #define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT_T::AES3_CNT: CNT Mask */
\r
1895 #define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT_T::TDES_CTL: START Position */
\r
1896 #define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT_T::TDES_CTL: START Mask */
\r
1898 #define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT_T::TDES_CTL: STOP Position */
\r
1899 #define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT_T::TDES_CTL: STOP Mask */
\r
1901 #define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT_T::TDES_CTL: TMODE Position */
\r
1902 #define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT_T::TDES_CTL: TMODE Mask */
\r
1904 #define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT_T::TDES_CTL: 3KEYS Position */
\r
1905 #define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT_T::TDES_CTL: 3KEYS Mask */
\r
1907 #define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT_T::TDES_CTL: DMALAST Position */
\r
1908 #define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT_T::TDES_CTL: DMALAST Mask */
\r
1910 #define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::TDES_CTL: DMACSCAD Position */
\r
1911 #define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT_T::TDES_CTL: DMACSCAD Mask */
\r
1913 #define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT_T::TDES_CTL: DMAEN Position */
\r
1914 #define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT_T::TDES_CTL: DMAEN Mask */
\r
1916 #define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT_T::TDES_CTL: OPMODE Position */
\r
1917 #define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT_T::TDES_CTL: OPMODE Mask */
\r
1919 #define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::TDES_CTL: ENCRPT Position */
\r
1920 #define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT_T::TDES_CTL: ENCRPT Mask */
\r
1922 #define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT_T::TDES_CTL: BLKSWAP Position */
\r
1923 #define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT_T::TDES_CTL: BLKSWAP Mask */
\r
1925 #define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::TDES_CTL: OUTSWAP Position */
\r
1926 #define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT_T::TDES_CTL: OUTSWAP Mask */
\r
1928 #define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT_T::TDES_CTL: INSWAP Position */
\r
1929 #define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT_T::TDES_CTL: INSWAP Mask */
\r
1931 #define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::TDES_CTL: CHANNEL Position */
\r
1932 #define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT_T::TDES_CTL: CHANNEL Mask */
\r
1934 #define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::TDES_CTL: KEYUNPRT Position */
\r
1935 #define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask */
\r
1937 #define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::TDES_CTL: KEYPRT Position */
\r
1938 #define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYPRT Mask */
\r
1940 #define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT_T::TDES_STS: BUSY Position */
\r
1941 #define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT_T::TDES_STS: BUSY Mask */
\r
1943 #define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::TDES_STS: INBUFEMPTY Position */
\r
1944 #define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask */
\r
1946 #define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::TDES_STS: INBUFFULL Position */
\r
1947 #define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT_T::TDES_STS: INBUFFULL Mask */
\r
1949 #define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT_T::TDES_STS: INBUFERR Position */
\r
1950 #define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT_T::TDES_STS: INBUFERR Mask */
\r
1952 #define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */
\r
1953 #define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask */
\r
1955 #define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::TDES_STS: OUTBUFFULL Position */
\r
1956 #define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask */
\r
1958 #define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::TDES_STS: OUTBUFERR Position */
\r
1959 #define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT_T::TDES_STS: OUTBUFERR Mask */
\r
1961 #define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT_T::TDES_STS: BUSERR Position */
\r
1962 #define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT_T::TDES_STS: BUSERR Mask */
\r
1964 #define CRPT_TDES0_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxH: KEY Position */
\r
1965 #define CRPT_TDES0_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos) /*!< CRPT_T::TDES0_KEYxH: KEY Mask */
\r
1967 #define CRPT_TDES0_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxL: KEY Position */
\r
1968 #define CRPT_TDES0_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos) /*!< CRPT_T::TDES0_KEYxL: KEY Mask */
\r
1970 #define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT_T::TDES0_IVH: IV Position */
\r
1971 #define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT_T::TDES0_IVH: IV Mask */
\r
1973 #define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT_T::TDES0_IVL: IV Position */
\r
1974 #define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT_T::TDES0_IVL: IV Mask */
\r
1976 #define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES0_SADDR: SADDR Position */
\r
1977 #define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT_T::TDES0_SADDR: SADDR Mask */
\r
1979 #define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES0_DADDR: DADDR Position */
\r
1980 #define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT_T::TDES0_DADDR: DADDR Mask */
\r
1982 #define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT_T::TDES0_CNT: CNT Position */
\r
1983 #define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT_T::TDES0_CNT: CNT Mask */
\r
1985 #define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT_T::TDES_DATIN: DATIN Position */
\r
1986 #define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT_T::TDES_DATIN: DATIN Mask */
\r
1988 #define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::TDES_DATOUT: DATOUT Position */
\r
1989 #define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT_T::TDES_DATOUT: DATOUT Mask */
\r
1991 #define CRPT_TDES1_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxH: KEY Position */
\r
1992 #define CRPT_TDES1_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos) /*!< CRPT_T::TDES1_KEYxH: KEY Mask */
\r
1994 #define CRPT_TDES1_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxL: KEY Position */
\r
1995 #define CRPT_TDES1_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT_T::TDES1_KEYxL: KEY Mask */
\r
1997 #define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT_T::TDES1_IVH: IV Position */
\r
1998 #define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT_T::TDES1_IVH: IV Mask */
\r
2000 #define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT_T::TDES1_IVL: IV Position */
\r
2001 #define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT_T::TDES1_IVL: IV Mask */
\r
2003 #define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES1_SADDR: SADDR Position */
\r
2004 #define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT_T::TDES1_SADDR: SADDR Mask */
\r
2006 #define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES1_DADDR: DADDR Position */
\r
2007 #define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT_T::TDES1_DADDR: DADDR Mask */
\r
2009 #define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT_T::TDES1_CNT: CNT Position */
\r
2010 #define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT_T::TDES1_CNT: CNT Mask */
\r
2012 #define CRPT_TDES2_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxH: KEY Position */
\r
2013 #define CRPT_TDES2_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos) /*!< CRPT_T::TDES2_KEYxH: KEY Mask */
\r
2015 #define CRPT_TDES2_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxL: KEY Position */
\r
2016 #define CRPT_TDES2_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos) /*!< CRPT_T::TDES2_KEYxL: KEY Mask */
\r
2018 #define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT_T::TDES2_IVH: IV Position */
\r
2019 #define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT_T::TDES2_IVH: IV Mask */
\r
2021 #define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT_T::TDES2_IVL: IV Position */
\r
2022 #define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT_T::TDES2_IVL: IV Mask */
\r
2024 #define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES2_SADDR: SADDR Position */
\r
2025 #define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT_T::TDES2_SADDR: SADDR Mask */
\r
2027 #define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES2_DADDR: DADDR Position */
\r
2028 #define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT_T::TDES2_DADDR: DADDR Mask */
\r
2030 #define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT_T::TDES2_CNT: CNT Position */
\r
2031 #define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT_T::TDES2_CNT: CNT Mask */
\r
2033 #define CRPT_TDES3_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxH: KEY Position */
\r
2034 #define CRPT_TDES3_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos) /*!< CRPT_T::TDES3_KEYxH: KEY Mask */
\r
2036 #define CRPT_TDES3_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxL: KEY Position */
\r
2037 #define CRPT_TDES3_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos) /*!< CRPT_T::TDES3_KEYxL: KEY Mask */
\r
2039 #define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT_T::TDES3_IVH: IV Position */
\r
2040 #define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT_T::TDES3_IVH: IV Mask */
\r
2042 #define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT_T::TDES3_IVL: IV Position */
\r
2043 #define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT_T::TDES3_IVL: IV Mask */
\r
2045 #define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES3_SADDR: SADDR Position */
\r
2046 #define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT_T::TDES3_SADDR: SADDR Mask */
\r
2048 #define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES3_DADDR: DADDR Position */
\r
2049 #define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT_T::TDES3_DADDR: DADDR Mask */
\r
2051 #define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT_T::TDES3_CNT: CNT Position */
\r
2052 #define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT_T::TDES3_CNT: CNT Mask */
\r
2054 #define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */
\r
2055 #define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */
\r
2057 #define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */
\r
2058 #define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */
\r
2060 #define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */
\r
2061 #define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */
\r
2063 #define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */
\r
2064 #define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */
\r
2066 #define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */
\r
2067 #define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */
\r
2069 #define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */
\r
2070 #define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */
\r
2072 #define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */
\r
2073 #define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */
\r
2075 #define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */
\r
2076 #define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */
\r
2078 #define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */
\r
2079 #define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */
\r
2081 #define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */
\r
2082 #define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */
\r
2084 #define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */
\r
2085 #define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */
\r
2087 #define CRPT_HMAC_DGSTx_DGST_Pos (0) /*!< CRPT_T::HMAC_DGSTx: DGST Position */
\r
2088 #define CRPT_HMAC_DGSTx_DGST_Msk (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos) /*!< CRPT_T::HMAC_DGSTx: DGST Mask */
\r
2090 #define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */
\r
2091 #define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */
\r
2093 #define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */
\r
2094 #define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */
\r
2096 #define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */
\r
2097 #define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */
\r
2099 #define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */
\r
2100 #define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */
\r
2102 #define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */
\r
2103 #define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */
\r
2105 #define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */
\r
2106 #define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */
\r
2108 #define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */
\r
2109 #define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */
\r
2111 #define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */
\r
2112 #define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */
\r
2114 #define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */
\r
2115 #define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */
\r
2117 #define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */
\r
2118 #define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */
\r
2120 #define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */
\r
2121 #define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */
\r
2123 #define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */
\r
2124 #define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */
\r
2126 #define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */
\r
2127 #define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */
\r
2129 #define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */
\r
2130 #define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */
\r
2132 #define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */
\r
2133 #define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */
\r
2135 #define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */
\r
2136 #define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */
\r
2138 #define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */
\r
2139 #define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */
\r
2141 #define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */
\r
2142 #define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */
\r
2144 #define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */
\r
2145 #define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */
\r
2147 #define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */
\r
2148 #define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */
\r
2150 #define CRPT_ECC_X1_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1: POINTX1 Position */
\r
2151 #define CRPT_ECC_X1_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos) /*!< CRPT_T::ECC_X1: POINTX1 Mask */
\r
2153 #define CRPT_ECC_Y1_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1: POINTY1 Position */
\r
2154 #define CRPT_ECC_Y1_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos) /*!< CRPT_T::ECC_Y1: POINTY1 Mask */
\r
2156 #define CRPT_ECC_X2_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2: POINTX2 Position */
\r
2157 #define CRPT_ECC_X2_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos) /*!< CRPT_T::ECC_X2: POINTX2 Mask */
\r
2159 #define CRPT_ECC_Y2_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2: POINTY2 Position */
\r
2160 #define CRPT_ECC_Y2_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos) /*!< CRPT_T::ECC_Y2: POINTY2 Mask */
\r
2162 #define CRPT_ECC_A_CURVEA_Pos (0) /*!< CRPT_T::ECC_A: CURVEA Position */
\r
2163 #define CRPT_ECC_A_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_CURVEA_Pos) /*!< CRPT_T::ECC_A: CURVEA Mask */
\r
2165 #define CRPT_ECC_B_CURVEB_Pos (0) /*!< CRPT_T::ECC_B: CURVEB Position */
\r
2166 #define CRPT_ECC_B_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_CURVEB_Pos) /*!< CRPT_T::ECC_B: CURVEB Mask */
\r
2168 #define CRPT_ECC_N_CURVEN_Pos (0) /*!< CRPT_T::ECC_N: CURVEN Position */
\r
2169 #define CRPT_ECC_N_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_CURVEN_Pos) /*!< CRPT_T::ECC_N: CURVEN Mask */
\r
2171 #define CRPT_ECC_K_SCALARK_Pos (0) /*!< CRPT_T::ECC_K: SCALARK Position */
\r
2172 #define CRPT_ECC_K_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_SCALARK_Pos) /*!< CRPT_T::ECC_K: SCALARK Mask */
\r
2174 #define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */
\r
2175 #define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */
\r
2177 #define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/
\r
2178 #define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */
\r
2180 #define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */
\r
2181 #define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */
\r
2183 /**@}*/ /* CRPT_CONST */
\r
2184 /**@}*/ /* end of CRPT register group */
\r
2185 /**@}*/ /* end of REGISTER group */
\r
2188 #endif /* __CRPT_REG_H__ */
\r
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