1 /**************************************************************************//**
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4 * @brief ECAP register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __ECAP_REG_H__
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9 #define __ECAP_REG_H__
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11 /** @addtogroup REGISTER Control Register
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17 /*---------------------- Enhanced Input Capture Timer -------------------------*/
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19 @addtogroup ECAP Enhanced Input Capture Timer(ECAP)
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20 Memory Mapped Structure for ECAP Controller
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28 * Offset: 0x00 Input Capture Counter (24-bit up counter)
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29 * ---------------------------------------------------------------------------------------------------
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30 * |Bits |Field |Descriptions
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31 * | :----: | :----: | :---- |
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32 * |[23:0] |CNT |Input Capture Timer/Counter
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33 * | | |The input Capture Timer/Counter is a 24-bit up-counting counter
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34 * | | |The clock source for the counter is from the clock divider
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36 * Offset: 0x04 Input Capture Hold Register 0
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37 * ---------------------------------------------------------------------------------------------------
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38 * |Bits |Field |Descriptions
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39 * | :----: | :----: | :---- |
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40 * |[23:0] |HOLD |Input Capture Counter Hold Register
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41 * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
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42 * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
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44 * Offset: 0x08 Input Capture Hold Register 1
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45 * ---------------------------------------------------------------------------------------------------
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46 * |Bits |Field |Descriptions
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47 * | :----: | :----: | :---- |
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48 * |[23:0] |HOLD |Input Capture Counter Hold Register
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49 * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
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50 * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
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52 * Offset: 0x0C Input Capture Hold Register 2
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53 * ---------------------------------------------------------------------------------------------------
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54 * |Bits |Field |Descriptions
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55 * | :----: | :----: | :---- |
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56 * |[23:0] |HOLD |Input Capture Counter Hold Register
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57 * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
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58 * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
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59 * @var ECAP_T::CNTCMP
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60 * Offset: 0x10 Input Capture Compare Register
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61 * ---------------------------------------------------------------------------------------------------
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62 * |Bits |Field |Descriptions
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63 * | :----: | :----: | :---- |
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64 * |[23:0] |CNTCMP |Input Capture Counter Compare Register
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65 * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
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66 * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
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68 * Offset: 0x14 Input Capture Control Register 0
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69 * ---------------------------------------------------------------------------------------------------
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70 * |Bits |Field |Descriptions
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71 * | :----: | :----: | :---- |
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72 * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
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73 * | | |To determine the sampling frequency of the Noise Filter clock
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74 * | | |000 = CAP_CLK.
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75 * | | |001 = CAP_CLK/2.
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76 * | | |010 = CAP_CLK/4.
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77 * | | |011 = CAP_CLK/16.
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78 * | | |100 = CAP_CLK/32.
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79 * | | |101 = CAP_CLK/64.
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80 * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control
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81 * | | |0 = Noise filter of Input Capture Enabled.
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82 * | | |1 = Noise filter of Input Capture Disabled (Bypass).
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83 * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control
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84 * | | |0 = IC0 input to Input Capture Unit Disabled.
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85 * | | |1 = IC0 input to Input Capture Unit Enabled.
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86 * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control
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87 * | | |0 = IC1 input to Input Capture Unit Disabled.
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88 * | | |1 = IC1 input to Input Capture Unit Enabled.
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89 * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control
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90 * | | |0 = IC2 input to Input Capture Unit Disabled.
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91 * | | |1 = IC2 input to Input Capture Unit Enabled.
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92 * |[9:8] |CAPSEL0 |CAP0 Input Source Selection
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93 * | | |00 = CAP0 input is from port pin ICAP0.
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94 * | | |01 = Reserved.
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95 * | | |10 = CAP0 input is from signal CHA of QEI controller unit n.
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96 * | | |11 = Reserved.
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97 * | | |Note: Input capture unit n matches QEIn, where n = 0~1.
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98 * |[11:10] |CAPSEL1 |CAP1 Input Source Selection
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99 * | | |00 = CAP1 input is from port pin ICAP1.
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100 * | | |01 = Reserved.
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101 * | | |10 = CAP1 input is from signal CHB of QEI controller unit n.
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102 * | | |11 = Reserved.
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103 * | | |Note: Input capture unit n matches QEIn, where n = 0~1.
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104 * |[13:12] |CAPSEL2 |CAP2 Input Source Selection
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105 * | | |00 = CAP2 input is from port pin ICAP2.
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106 * | | |01 = Reserved.
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107 * | | |10 = CAP2 input is from signal CHX of QEI controller unit n.
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108 * | | |11 = Reserved.
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109 * | | |Note: Input capture unit n matches QEIn, where n = 0~1.
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110 * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
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111 * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
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112 * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
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113 * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
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114 * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
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115 * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
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116 * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
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117 * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
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118 * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
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119 * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control
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120 * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
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121 * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
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122 * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control
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123 * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
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124 * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
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125 * |[24] |CNTEN |Input Capture Counter Start Counting Control
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126 * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
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127 * | | |0 = ECAP_CNT stop counting.
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128 * | | |1 = ECAP_CNT starts up-counting.
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129 * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control
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130 * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
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131 * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
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132 * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
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133 * |[28] |CMPEN |Compare Function Enable Control
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134 * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
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135 * | | |0 = The compare function Disabled.
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136 * | | |1 = The compare function Enabled.
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137 * |[29] |CAPEN |Input Capture Timer/Counter Enable Control
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138 * | | |0 = Input Capture function Disabled.
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139 * | | |1 = Input Capture function Enabled.
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140 * @var ECAP_T::CTL1
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141 * Offset: 0x18 Input Capture Control Register 1
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142 * ---------------------------------------------------------------------------------------------------
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143 * |Bits |Field |Descriptions
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144 * | :----: | :----: | :---- |
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145 * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection
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146 * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change
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147 * | | |00 = Detect rising edge only.
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148 * | | |01 = Detect falling edge only.
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149 * | | |1x = Detect both rising and falling edge.
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150 * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection
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151 * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change
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152 * | | |00 = Detect rising edge only.
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153 * | | |01 = Detect falling edge only.
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154 * | | |1x = Detect both rising and falling edge.
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155 * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection
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156 * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
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157 * | | |00 = Detect rising edge only.
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158 * | | |01 = Detect falling edge only.
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159 * | | |1x = Detect both rising and falling edge.
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160 * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
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161 * | | |0 = The reload triggered by Event CAPTE0 Disabled.
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162 * | | |1 = The reload triggered by Event CAPTE0 Enabled.
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163 * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
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164 * | | |0 = The reload triggered by Event CAPTE1 Disabled.
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165 * | | |1 = The reload triggered by Event CAPTE1 Enabled.
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166 * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
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167 * | | |0 = The reload triggered by Event CAPTE2 Disabled.
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168 * | | |1 = The reload triggered by Event CAPTE2 Enabled.
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169 * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
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170 * | | |0 = The reload triggered by CAPOV Disabled.
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171 * | | |1 = The reload triggered by CAPOV Enabled.
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172 * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection
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173 * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
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174 * | | |000 = CAP_CLK/1.
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175 * | | |001 = CAP_CLK/4.
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176 * | | |010 = CAP_CLK/16.
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177 * | | |011 = CAP_CLK/32.
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178 * | | |100 = CAP_CLK/64.
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179 * | | |101 = CAP_CLK/96.
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180 * | | |110 = CAP_CLK/112.
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181 * | | |111 = CAP_CLK/128.
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182 * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
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183 * | | |Select the capture timer/counter clock source.
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184 * | | |00 = CAP_CLK (default).
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188 * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
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189 * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
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190 * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
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191 * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
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192 * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
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193 * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
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194 * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
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195 * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
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196 * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
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197 * @var ECAP_T::STATUS
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198 * Offset: 0x1C Input Capture Status Register
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199 * ---------------------------------------------------------------------------------------------------
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200 * |Bits |Field |Descriptions
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201 * | :----: | :----: | :---- |
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202 * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag
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203 * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
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204 * | | |0 = No valid edge change has been detected at CAP0 input since last clear.
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205 * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.
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206 * | | |Note: This bit is only cleared by writing 1 to it.
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207 * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag
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208 * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
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209 * | | |0 = No valid edge change has been detected at CAP1 input since last clear.
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210 * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.
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211 * | | |Note: This bit is only cleared by writing 1 to it.
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212 * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag
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213 * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
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214 * | | |0 = No valid edge change has been detected at CAP2 input since last clear.
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215 * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.
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216 * | | |Note: This bit is only cleared by writing 1 to it.
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217 * |[4] |CAPCMPF |Input Capture Compare-match Flag
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218 * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
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219 * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
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220 * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
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221 * | | |Note: This bit is only cleared by writing 1 to it.
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222 * |[5] |CAPOVF |Input Capture Counter Overflow Flag
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223 * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
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224 * | | |0 = No overflow event has occurred since last clear.
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225 * | | |1 = Overflow event(s) has/have occurred since last clear.
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226 * | | |Note: This bit is only cleared by writing 1 to it.
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227 * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)
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228 * | | |Reflecting the value of input channel 0, CAP0
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229 * | | |(The bit is read only and write is ignored)
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230 * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)
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231 * | | |Reflecting the value of input channel 1, CAP1
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232 * | | |(The bit is read only and write is ignored)
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233 * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)
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234 * | | |Reflecting the value of input channel 2, CAP2.
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235 * | | |(The bit is read only and write is ignored)
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237 __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */
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238 __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */
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239 __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */
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240 __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */
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241 __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */
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242 __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */
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243 __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */
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244 __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */
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249 @addtogroup ECAP_CONST ECAP Bit Field Definition
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250 Constant Definitions for ECAP Controller
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253 #define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */
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254 #define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */
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256 #define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */
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257 #define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */
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259 #define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */
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260 #define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */
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262 #define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */
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263 #define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */
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265 #define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */
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266 #define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */
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268 #define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */
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269 #define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */
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271 #define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */
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272 #define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */
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274 #define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */
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275 #define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */
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277 #define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */
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278 #define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */
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280 #define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */
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281 #define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */
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283 #define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */
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284 #define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */
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286 #define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */
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287 #define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */
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289 #define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */
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290 #define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */
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292 #define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */
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293 #define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */
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295 #define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */
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296 #define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */
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298 #define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */
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299 #define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */
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301 #define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */
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302 #define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */
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304 #define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */
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305 #define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */
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307 #define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */
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308 #define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */
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310 #define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */
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311 #define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */
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313 #define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */
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314 #define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */
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316 #define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */
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317 #define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */
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319 #define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */
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320 #define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */
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322 #define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */
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323 #define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */
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325 #define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */
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326 #define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */
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328 #define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */
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329 #define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */
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331 #define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */
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332 #define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */
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334 #define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */
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335 #define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */
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337 #define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */
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338 #define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */
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340 #define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */
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341 #define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */
\r
343 #define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */
\r
344 #define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */
\r
346 #define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */
\r
347 #define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */
\r
349 #define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */
\r
350 #define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */
\r
352 #define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */
\r
353 #define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */
\r
355 #define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */
\r
356 #define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */
\r
358 #define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */
\r
359 #define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */
\r
361 #define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */
\r
362 #define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */
\r
364 #define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */
\r
365 #define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */
\r
367 #define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */
\r
368 #define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */
\r
370 #define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */
\r
371 #define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */
\r
373 #define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */
\r
374 #define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */
\r
376 #define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */
\r
377 #define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */
\r
379 /**@}*/ /* ECAP_CONST */
\r
380 /**@}*/ /* end of ECAP register group */
\r
381 /**@}*/ /* end of REGISTER group */
\r
384 #endif /* __ECAP_REG_H__ */
\r
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