1 /**************************************************************************//**
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4 * @brief EPWM register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __EPWM_REG_H__
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9 #define __EPWM_REG_H__
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11 /** @addtogroup REGISTER Control Register
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18 /*---------------------- Enhanced Pulse Width Modulation Controller -------------------------*/
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20 @addtogroup EPWM Enhanced Pulse Width Modulation Controller(EPWM)
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21 Memory Mapped Structure for EPWM Controller
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27 * @var ECAPDAT_T::RCAPDAT
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28 * Offset: 0x20C EPWM Rising Capture Data Register 0~5
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29 * ---------------------------------------------------------------------------------------------------
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30 * |Bits |Field |Descriptions
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31 * | :----: | :----: | :---- |
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32 * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only)
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33 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register.
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34 * @var ECAPDAT_T::FCAPDAT
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35 * Offset: 0x210 EPWM Falling Capture Data Register 0~5
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36 * ---------------------------------------------------------------------------------------------------
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37 * |Bits |Field |Descriptions
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38 * | :----: | :----: | :---- |
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39 * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only)
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40 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register.
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42 __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */
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43 __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */
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52 * Offset: 0x00 EPWM Control Register 0
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53 * ---------------------------------------------------------------------------------------------------
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54 * |Bits |Field |Descriptions
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55 * | :----: | :----: | :---- |
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56 * |[0] |CTRLD0 |Center Re-load
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57 * | | |In up-down counter type, PERIOD0 register will load to PBUF0 register at the end point of each period.
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58 * | | |CMPDAT0 register will load to CMPBUF0 register at the center point of a period.
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59 * |[1] |CTRLD1 |Center Re-load
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60 * | | |In up-down counter type, PERIOD1 register will load to PBUF1 register at the end point of each period.
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61 * | | |CMPDAT1 register will load to CMPBUF1 register at the center point of a period.
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62 * |[2] |CTRLD2 |Center Re-load
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63 * | | |In up-down counter type, PERIOD2 register will load to PBUF2 register at the end point of each period.
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64 * | | |CMPDAT2 register will load to CMPBUF2 register at the center point of a period.
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65 * |[3] |CTRLD3 |Center Re-load
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66 * | | |In up-down counter type, PERIOD3 register will load to PBUF3 register at the end point of each period.
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67 * | | |CMPDAT3 register will load to CMPBUF3 register at the center point of a period.
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68 * |[4] |CTRLD4 |Center Re-load
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69 * | | |In up-down counter type, PERIOD4 register will load to PBUF4 register at the end point of each period.
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70 * | | |CMPDAT4 register will load to CMPBUF4 register at the center point of a period.
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71 * |[5] |CTRLD5 |Center Re-load
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72 * | | |In up-down counter type, PERIOD5 register will load to PBUF5 register at the end point of each period.
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73 * | | |CMPDAT5 register will load to CMPBUF5 register at the center point of a period.
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74 * |[8] |WINLDEN0 |Window Load Enable Bits
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75 * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period.
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76 * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit.
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77 * | | |1 = PERIOD0 register will load to PBUF0 and CMPDAT0 registers will load to CMPBUF0 register at the end point of each period when valid reload window is set.
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78 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
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79 * |[9] |WINLDEN1 |Window Load Enable Bits
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80 * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period.
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81 * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit.
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82 * | | |1 = PERIOD1 register will load to PBUF1 and CMPDAT1 registers will load to CMPBUF1 register at the end point of each period when valid reload window is set.
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83 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
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84 * |[10] |WINLDEN2 |Window Load Enable Bits
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85 * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period.
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86 * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit.
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87 * | | |1 = PERIOD2 register will load to PBUF2 and CMPDAT2 registers will load to CMPBUF2 register at the end point of each period when valid reload window is set.
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88 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
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89 * |[11] |WINLDEN3 |Window Load Enable Bits
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90 * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period.
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91 * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit.
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92 * | | |1 = PERIOD3 register will load to PBUF3 and CMPDAT3 registers will load to CMPBUF3 register at the end point of each period when valid reload window is set.
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93 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
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94 * |[12] |WINLDEN4 |Window Load Enable Bits
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95 * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period.
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96 * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit.
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97 * | | |1 = PERIOD4 register will load to PBUF4 and CMPDAT4 registers will load to CMPBUF4 register at the end point of each period when valid reload window is set.
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98 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
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99 * |[13] |WINLDEN5 |Window Load Enable Bits
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100 * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period.
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101 * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit.
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102 * | | |1 = PERIOD5 register will load to PBUF5 and CMPDAT5 registers will load to CMPBUF5 register at the end point of each period when valid reload window is set.
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103 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
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104 * |[16] |IMMLDEN0 |Immediately Load Enable Bits
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105 * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period.
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106 * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit.
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107 * | | |1 = PERIOD0/CMPDAT0 registers will load to PBUF0 and CMPBUF0 register immediately when software update PERIOD0/CMPDAT0 register.
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108 * | | |Note: If IMMLDEN0 bit is enabled, WINLDEN0 bit and CTRLD0 bits will be invalid.
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109 * |[17] |IMMLDEN1 |Immediately Load Enable Bits
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110 * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period.
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111 * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit.
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112 * | | |1 = PERIOD1/CMPDAT1 registers will load to PBUF1 and CMPBUF1 register immediately when software update PERIOD1/CMPDAT1 register.
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113 * | | |Note: If IMMLDEN1 bit is enabled, WINLDEN1 bit and CTRLD1 bits will be invalid.
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114 * |[18] |IMMLDEN2 |Immediately Load Enable Bits
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115 * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period.
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116 * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit.
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117 * | | |1 = PERIOD2/CMPDAT2 registers will load to PBUF2 and CMPBUF2 register immediately when software update PERIOD2/CMPDAT2 register.
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118 * | | |Note: If IMMLDEN2 bit is enabled, WINLDEN2 bit and CTRLD2 bits will be invalid.
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119 * |[19] |IMMLDEN3 |Immediately Load Enable Bits
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120 * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period.
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121 * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit.
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122 * | | |1 = PERIOD3/CMPDAT3 registers will load to PBUF3 and CMPBUF3 register immediately when software update PERIOD3/CMPDAT3 register.
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123 * | | |Note: If IMMLDEN3 bit is enabled, WINLDEN3 bit and CTRLD3 bits will be invalid.
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124 * |[20] |IMMLDEN4 |Immediately Load Enable Bits
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125 * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period.
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126 * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit.
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127 * | | |1 = PERIOD4/CMPDAT4 registers will load to PBUF4 and CMPBUF4 register immediately when software update PERIOD4/CMPDAT4 register.
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128 * | | |Note: If IMMLDEN4 bit is enabled, WINLDEN4 bit and CTRLD4 bits will be invalid.
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129 * |[21] |IMMLDEN5 |Immediately Load Enable Bits
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130 * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period.
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131 * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit.
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132 * | | |1 = PERIOD5/CMPDAT5 registers will load to PBUF5 and CMPBUF5 register immediately when software update PERIOD5/CMPDAT5 register.
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133 * | | |Note: If IMMLDEN5 bit is enabled, WINLDEN5 bit and CTRLD5 bits will be invalid.
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134 * |[24] |GROUPEN |Group Function Enable Bit
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135 * | | |0 = The output waveform of each EPWM channel are independent.
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136 * | | |1 = Unify the EPWMx_CH2 and EPWMx_CH4 to output the same waveform as EPWMx_CH0 and unify the EPWMx_CH3 and EPWMx_CH5 to output the same waveform as EPWMx_CH1.
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137 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
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138 * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode.
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139 * | | |0 = ICE debug mode counter halt disable.
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140 * | | |1 = ICE debug mode counter halt enable.
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141 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
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142 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
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143 * | | |0 = ICE debug mode acknowledgement effects EPWM output.
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144 * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged.
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145 * | | |1 = ICE debug mode acknowledgement disabled.
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146 * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not.
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147 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
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148 * @var EPWM_T::CTL1
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149 * Offset: 0x04 EPWM Control Register 1
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150 * ---------------------------------------------------------------------------------------------------
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151 * |Bits |Field |Descriptions
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152 * | :----: | :----: | :---- |
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153 * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type
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154 * | | |00 = Up counter type (supports in capture mode).
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155 * | | |01 = Down count type (supports in capture mode).
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156 * | | |10 = Up-down counter type.
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157 * | | |11 = Reserved.
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158 * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type
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159 * | | |00 = Up counter type (supports in capture mode).
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160 * | | |01 = Down count type (supports in capture mode).
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161 * | | |10 = Up-down counter type.
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162 * | | |11 = Reserved.
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163 * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type
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164 * | | |00 = Up counter type (supports in capture mode).
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165 * | | |01 = Down count type (supports in capture mode).
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166 * | | |10 = Up-down counter type.
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167 * | | |11 = Reserved.
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168 * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type
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169 * | | |00 = Up counter type (supports in capture mode).
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170 * | | |01 = Down count type (supports in capture mode).
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171 * | | |10 = Up-down counter type.
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172 * | | |11 = Reserved.
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173 * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type
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174 * | | |00 = Up counter type (supports in capture mode).
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175 * | | |01 = Down count type (supports in capture mode).
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176 * | | |10 = Up-down counter type.
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177 * | | |11 = Reserved.
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178 * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type
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179 * | | |00 = Up counter type (supports in capture mode).
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180 * | | |01 = Down count type (supports in capture mode).
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181 * | | |10 = Up-down counter type.
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182 * | | |11 = Reserved.
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183 * |[16] |CNTMODE0 |EPWM Counter Mode
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184 * | | |0 = Auto-reload mode.
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185 * | | |1 = One-shot mode.
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186 * |[17] |CNTMODE1 |EPWM Counter Mode
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187 * | | |0 = Auto-reload mode.
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188 * | | |1 = One-shot mode.
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189 * |[18] |CNTMODE2 |EPWM Counter Mode
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190 * | | |0 = Auto-reload mode.
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191 * | | |1 = One-shot mode.
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192 * |[19] |CNTMODE3 |EPWM Counter Mode
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193 * | | |0 = Auto-reload mode.
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194 * | | |1 = One-shot mode.
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195 * |[20] |CNTMODE4 |EPWM Counter Mode
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196 * | | |0 = Auto-reload mode.
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197 * | | |1 = One-shot mode.
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198 * |[21] |CNTMODE5 |EPWM Counter Mode
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199 * | | |0 = Auto-reload mode.
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200 * | | |1 = One-shot mode.
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201 * |[24] |OUTMODE0 |EPWM Output Mode
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202 * | | |Each bit n controls the output mode of corresponding EPWM channel n.
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203 * | | |0 = EPWM independent mode.
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204 * | | |1 = EPWM complementary mode.
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205 * | | |Note: When operating in group function, these bits must all set to the same mode.
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206 * |[25] |OUTMODE2 |EPWM Output Mode
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207 * | | |Each bit n controls the output mode of corresponding EPWM channel n.
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208 * | | |0 = EPWM independent mode.
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209 * | | |1 = EPWM complementary mode.
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210 * | | |Note: When operating in group function, these bits must all set to the same mode.
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211 * |[26] |OUTMODE4 |EPWM Output Mode
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212 * | | |Each bit n controls the output mode of corresponding EPWM channel n.
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213 * | | |0 = EPWM independent mode.
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214 * | | |1 = EPWM complementary mode.
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215 * | | |Note: When operating in group function, these bits must all set to the same mode.
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216 * @var EPWM_T::SYNC
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217 * Offset: 0x08 EPWM Synchronization Register
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218 * ---------------------------------------------------------------------------------------------------
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219 * |Bits |Field |Descriptions
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220 * | :----: | :----: | :---- |
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221 * |[0] |PHSEN0 |SYNC Phase Enable Bits
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222 * | | |0 = EPWM counter disable to load PHS value.
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223 * | | |1 = EPWM counter enable to load PHS value.
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224 * |[1] |PHSEN2 |SYNC Phase Enable Bits
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225 * | | |0 = EPWM counter disable to load PHS value.
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226 * | | |1 = EPWM counter enable to load PHS value.
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227 * |[2] |PHSEN4 |SYNC Phase Enable Bits
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228 * | | |0 = EPWM counter disable to load PHS value.
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229 * | | |1 = EPWM counter enable to load PHS value.
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230 * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection
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231 * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
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232 * | | |01 = Counter equal to 0.
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233 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
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234 * | | |11 = SYNC_OUT will not be generated.
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235 * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection
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236 * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
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237 * | | |01 = Counter equal to 0.
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238 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
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239 * | | |11 = SYNC_OUT will not be generated.
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240 * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection
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241 * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
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242 * | | |01 = Counter equal to 0.
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243 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
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244 * | | |11 = SYNC_OUT will not be generated.
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245 * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits
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246 * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled.
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247 * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled.
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248 * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection
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249 * | | |000 = Filter clock = HCLK.
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250 * | | |001 = Filter clock = HCLK/2.
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251 * | | |010 = Filter clock = HCLK/4.
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252 * | | |011 = Filter clock = HCLK/8.
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253 * | | |100 = Filter clock = HCLK/16.
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254 * | | |101 = Filter clock = HCLK/32.
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255 * | | |110 = Filter clock = HCLK/64.
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256 * | | |111 = Filter clock = HCLK/128.
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257 * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count
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258 * | | |The register bits control the counter number of edge detector.
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259 * |[23] |SINPINV |SYNC Input Pin Inverse
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260 * | | |0 = The state of pin EPWM0_SYNC_IN is passed to the negative edge detector.
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261 * | | |1 = The inverse state of pin EPWM0_SYNC_IN is passed to the negative edge detector.
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262 * |[24] |PHSDIR0 |EPWM Phase Direction Control
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263 * | | |0 = Control EPWM counter count decrement after synchronizing.
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264 * | | |1 = Control EPWM counter count increment after synchronizing.
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265 * |[25] |PHSDIR2 |EPWM Phase Direction Control
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266 * | | |0 = Control EPWM counter count decrement after synchronizing.
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267 * | | |1 = Control EPWM counter count increment after synchronizing.
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268 * |[26] |PHSDIR4 |EPWM Phase Direction Control
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269 * | | |0 = Control EPWM counter count decrement after synchronizing.
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270 * | | |1 = Control EPWM counter count increment after synchronizing.
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271 * @var EPWM_T::SWSYNC
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272 * Offset: 0x0C EPWM Software Control Synchronization Register
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273 * ---------------------------------------------------------------------------------------------------
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274 * |Bits |Field |Descriptions
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275 * | :----: | :----: | :---- |
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276 * |[0] |SWSYNC0 |Software SYNC Function
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277 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
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278 * |[1] |SWSYNC2 |Software SYNC Function
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279 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
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280 * |[2] |SWSYNC4 |Software SYNC Function
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281 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
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282 * @var EPWM_T::CLKSRC
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283 * Offset: 0x10 EPWM Clock Source Register
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284 * ---------------------------------------------------------------------------------------------------
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285 * |Bits |Field |Descriptions
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286 * | :----: | :----: | :---- |
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287 * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select
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288 * | | |000 = EPWMx_CLK, x denotes 0 or 1.
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289 * | | |001 = TIMER0 overflow.
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290 * | | |010 = TIMER1 overflow.
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291 * | | |011 = TIMER2 overflow.
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292 * | | |100 = TIMER3 overflow.
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293 * | | |Others = Reserved.
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294 * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select
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295 * | | |000 = EPWMx_CLK, x denotes 0 or 1.
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296 * | | |001 = TIMER0 overflow.
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297 * | | |010 = TIMER1 overflow.
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298 * | | |011 = TIMER2 overflow.
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299 * | | |100 = TIMER3 overflow.
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300 * | | |Others = Reserved.
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301 * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select
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302 * | | |000 = EPWMx_CLK, x denotes 0 or 1.
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303 * | | |001 = TIMER0 overflow.
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304 * | | |010 = TIMER1 overflow.
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305 * | | |011 = TIMER2 overflow.
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306 * | | |100 = TIMER3 overflow.
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307 * | | |Others = Reserved.
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308 * @var EPWM_T::CLKPSC[3]
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309 * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5
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310 * ---------------------------------------------------------------------------------------------------
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311 * |Bits |Field |Descriptions
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312 * | :----: | :----: | :---- |
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313 * |[11:0] |CLKPSC |EPWM Counter Clock Prescale
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314 * | | |The clock of EPWM counter is decided by clock prescaler
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315 * | | |Each EPWM pair share one EPWM counter clock prescaler
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316 * | | |The clock of EPWM counter is divided by (CLKPSC+ 1)
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317 * @var EPWM_T::CNTEN
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318 * Offset: 0x20 EPWM Counter Enable Register
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319 * ---------------------------------------------------------------------------------------------------
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320 * |Bits |Field |Descriptions
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321 * | :----: | :----: | :---- |
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322 * |[0] |CNTEN0 |EPWM Counter Enable Bits
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323 * | | |0 = EPWM Counter and clock prescaler Stop Running.
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324 * | | |1 = EPWM Counter and clock prescaler Start Running.
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325 * |[1] |CNTEN1 |EPWM Counter Enable Bits
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326 * | | |0 = EPWM Counter and clock prescaler Stop Running.
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327 * | | |1 = EPWM Counter and clock prescaler Start Running.
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328 * |[2] |CNTEN2 |EPWM Counter Enable Bits
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329 * | | |0 = EPWM Counter and clock prescaler Stop Running.
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330 * | | |1 = EPWM Counter and clock prescaler Start Running.
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331 * |[3] |CNTEN3 |EPWM Counter Enable Bits
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332 * | | |0 = EPWM Counter and clock prescaler Stop Running.
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333 * | | |1 = EPWM Counter and clock prescaler Start Running.
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334 * |[4] |CNTEN4 |EPWM Counter Enable Bits
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335 * | | |0 = EPWM Counter and clock prescaler Stop Running.
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336 * | | |1 = EPWM Counter and clock prescaler Start Running.
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337 * |[5] |CNTEN5 |EPWM Counter Enable Bits
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338 * | | |0 = EPWM Counter and clock prescaler Stop Running.
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339 * | | |1 = EPWM Counter and clock prescaler Start Running.
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340 * @var EPWM_T::CNTCLR
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341 * Offset: 0x24 EPWM Clear Counter Register
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342 * ---------------------------------------------------------------------------------------------------
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343 * |Bits |Field |Descriptions
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344 * | :----: | :----: | :---- |
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345 * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit
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346 * | | |It is automatically cleared by hardware.
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347 * | | |0 = No effect.
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348 * | | |1 = Clear 16-bit EPWM counter to 0000H.
\r
349 * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit
\r
350 * | | |It is automatically cleared by hardware.
\r
351 * | | |0 = No effect.
\r
352 * | | |1 = Clear 16-bit EPWM counter to 0000H.
\r
353 * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit
\r
354 * | | |It is automatically cleared by hardware.
\r
355 * | | |0 = No effect.
\r
356 * | | |1 = Clear 16-bit EPWM counter to 0000H.
\r
357 * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit
\r
358 * | | |It is automatically cleared by hardware.
\r
359 * | | |0 = No effect.
\r
360 * | | |1 = Clear 16-bit EPWM counter to 0000H.
\r
361 * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit
\r
362 * | | |It is automatically cleared by hardware.
\r
363 * | | |0 = No effect.
\r
364 * | | |1 = Clear 16-bit EPWM counter to 0000H.
\r
365 * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit
\r
366 * | | |It is automatically cleared by hardware.
\r
367 * | | |0 = No effect.
\r
368 * | | |1 = Clear 16-bit EPWM counter to 0000H.
\r
369 * @var EPWM_T::LOAD
\r
370 * Offset: 0x28 EPWM Load Register
\r
371 * ---------------------------------------------------------------------------------------------------
\r
372 * |Bits |Field |Descriptions
\r
373 * | :----: | :----: | :---- |
\r
374 * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
\r
375 * | | |This bit is software write, hardware clear when current EPWM period end.
\r
376 * | | |Write Operation:
\r
377 * | | |0 = No effect.
\r
378 * | | |1 = Set load window of window loading mode.
\r
379 * | | |Read Operation:
\r
380 * | | |0 = No load window is set.
\r
381 * | | |1 = Load window is set.
\r
382 * | | |Note: This bit only use in window loading mode, WINLDEN0(EPWM_CTL0[13:8]) = 1.
\r
383 * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
\r
384 * | | |This bit is software write, hardware clear when current EPWM period end.
\r
385 * | | |Write Operation:
\r
386 * | | |0 = No effect.
\r
387 * | | |1 = Set load window of window loading mode.
\r
388 * | | |Read Operation:
\r
389 * | | |0 = No load window is set.
\r
390 * | | |1 = Load window is set.
\r
391 * | | |Note: This bit only use in window loading mode, WINLDEN1(EPWM_CTL0[13:8]) = 1.
\r
392 * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
\r
393 * | | |This bit is software write, hardware clear when current EPWM period end.
\r
394 * | | |Write Operation:
\r
395 * | | |0 = No effect.
\r
396 * | | |1 = Set load window of window loading mode.
\r
397 * | | |Read Operation:
\r
398 * | | |0 = No load window is set.
\r
399 * | | |1 = Load window is set.
\r
400 * | | |Note: This bit only use in window loading mode, WINLDEN2(EPWM_CTL0[13:8]) = 1.
\r
401 * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
\r
402 * | | |This bit is software write, hardware clear when current EPWM period end.
\r
403 * | | |Write Operation:
\r
404 * | | |0 = No effect.
\r
405 * | | |1 = Set load window of window loading mode.
\r
406 * | | |Read Operation:
\r
407 * | | |0 = No load window is set.
\r
408 * | | |1 = Load window is set.
\r
409 * | | |Note: This bit only use in window loading mode, WINLDEN3(EPWM_CTL0[13:8]) = 1.
\r
410 * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
\r
411 * | | |This bit is software write, hardware clear when current EPWM period end.
\r
412 * | | |Write Operation:
\r
413 * | | |0 = No effect.
\r
414 * | | |1 = Set load window of window loading mode.
\r
415 * | | |Read Operation:
\r
416 * | | |0 = No load window is set.
\r
417 * | | |1 = Load window is set.
\r
418 * | | |Note: This bit only use in window loading mode, WINLDEN4(EPWM_CTL0[13:8]) = 1.
\r
419 * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit
\r
420 * | | |This bit is software write, hardware clear when current EPWM period end.
\r
421 * | | |Write Operation:
\r
422 * | | |0 = No effect.
\r
423 * | | |1 = Set load window of window loading mode.
\r
424 * | | |Read Operation:
\r
425 * | | |0 = No load window is set.
\r
426 * | | |1 = Load window is set.
\r
427 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
\r
428 * @var EPWM_T::PERIOD[6]
\r
429 * Offset: 0x30 EPWM Period Register 0~5
\r
430 * ---------------------------------------------------------------------------------------------------
\r
431 * |Bits |Field |Descriptions
\r
432 * | :----: | :----: | :---- |
\r
433 * |[15:0] |PERIOD |EPWM Period Register
\r
434 * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0.
\r
435 * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD.
\r
436 * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period.
\r
437 * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
\r
438 * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period.
\r
439 * @var EPWM_T::CMPDAT[6]
\r
440 * Offset: 0x50 EPWM Comparator Register 0
\r
441 * ---------------------------------------------------------------------------------------------------
\r
442 * |Bits |Field |Descriptions
\r
443 * | :----: | :----: | :---- |
\r
444 * |[15:0] |CMP |EPWM Comparator Register
\r
445 * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC.
\r
446 * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.
\r
447 * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
\r
448 * @var EPWM_T::DTCTL[3]
\r
449 * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5
\r
450 * ---------------------------------------------------------------------------------------------------
\r
451 * |Bits |Field |Descriptions
\r
452 * | :----: | :----: | :---- |
\r
453 * |[11:0] |DTCNT |Dead-time Counter (Write Protect)
\r
454 * | | |The dead-time can be calculated from the following formula:
\r
455 * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period.
\r
456 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
457 * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)
\r
458 * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled
\r
459 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
\r
460 * | | |0 = Dead-time insertion Disabled on the pin pair.
\r
461 * | | |1 = Dead-time insertion Enabled on the pin pair.
\r
462 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
463 * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect)
\r
464 * | | |0 = Dead-time clock source from EPWM_CLK.
\r
465 * | | |1 = Dead-time clock source from prescaler output.
\r
466 * | | |Note: This register is write protected. Refer toREGWRPROT register.
\r
467 * @var EPWM_T::PHS[3]
\r
468 * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5
\r
469 * ---------------------------------------------------------------------------------------------------
\r
470 * |Bits |Field |Descriptions
\r
471 * | :----: | :----: | :---- |
\r
472 * |[15:0] |PHS |EPWM Synchronous Start Phase Bits
\r
473 * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function.
\r
474 * @var EPWM_T::CNT[6]
\r
475 * Offset: 0x90 EPWM Counter Register 0~5
\r
476 * ---------------------------------------------------------------------------------------------------
\r
477 * |Bits |Field |Descriptions
\r
478 * | :----: | :----: | :---- |
\r
479 * |[15:0] |CNT |EPWM Data Register (Read Only)
\r
480 * | | |User can monitor CNTR to know the current value in 16-bit period counter.
\r
481 * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only)
\r
482 * | | |0 = Counter is Down count.
\r
483 * | | |1 = Counter is UP count.
\r
484 * @var EPWM_T::WGCTL0
\r
485 * Offset: 0xB0 EPWM Generation Register 0
\r
486 * ---------------------------------------------------------------------------------------------------
\r
487 * |Bits |Field |Descriptions
\r
488 * | :----: | :----: | :---- |
\r
489 * |[1:0] |ZPCTL0 |EPWM Zero Point Control
\r
490 * | | |00 = Do nothing.
\r
491 * | | |01 = EPWM zero point output Low.
\r
492 * | | |10 = EPWM zero point output High.
\r
493 * | | |11 = EPWM zero point output Toggle.
\r
494 * | | |EPWM can control output level when EPWM counter count to zero.
\r
495 * |[3:2] |ZPCTL1 |EPWM Zero Point Control
\r
496 * | | |00 = Do nothing.
\r
497 * | | |01 = EPWM zero point output Low.
\r
498 * | | |10 = EPWM zero point output High.
\r
499 * | | |11 = EPWM zero point output Toggle.
\r
500 * | | |EPWM can control output level when EPWM counter count to zero.
\r
501 * |[5:4] |ZPCTL2 |EPWM Zero Point Control
\r
502 * | | |00 = Do nothing.
\r
503 * | | |01 = EPWM zero point output Low.
\r
504 * | | |10 = EPWM zero point output High.
\r
505 * | | |11 = EPWM zero point output Toggle.
\r
506 * | | |EPWM can control output level when EPWM counter count to zero.
\r
507 * |[7:6] |ZPCTL3 |EPWM Zero Point Control
\r
508 * | | |00 = Do nothing.
\r
509 * | | |01 = EPWM zero point output Low.
\r
510 * | | |10 = EPWM zero point output High.
\r
511 * | | |11 = EPWM zero point output Toggle.
\r
512 * | | |EPWM can control output level when EPWM counter count to zero.
\r
513 * |[9:8] |ZPCTL4 |EPWM Zero Point Control
\r
514 * | | |00 = Do nothing.
\r
515 * | | |01 = EPWM zero point output Low.
\r
516 * | | |10 = EPWM zero point output High.
\r
517 * | | |11 = EPWM zero point output Toggle.
\r
518 * | | |EPWM can control output level when EPWM counter count to zero.
\r
519 * |[11:10] |ZPCTL5 |EPWM Zero Point Control
\r
520 * | | |00 = Do nothing.
\r
521 * | | |01 = EPWM zero point output Low.
\r
522 * | | |10 = EPWM zero point output High.
\r
523 * | | |11 = EPWM zero point output Toggle.
\r
524 * | | |EPWM can control output level when EPWM counter count to zero.
\r
525 * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control
\r
526 * | | |00 = Do nothing.
\r
527 * | | |01 = EPWM period (center) point output Low.
\r
528 * | | |10 = EPWM period (center) point output High.
\r
529 * | | |11 = EPWM period (center) point output Toggle.
\r
530 * | | |EPWM can control output level when EPWM counter count to (PERIOD0+1).
\r
531 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
\r
532 * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control
\r
533 * | | |00 = Do nothing.
\r
534 * | | |01 = EPWM period (center) point output Low.
\r
535 * | | |10 = EPWM period (center) point output High.
\r
536 * | | |11 = EPWM period (center) point output Toggle.
\r
537 * | | |EPWM can control output level when EPWM counter count to (PERIOD1+1).
\r
538 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
\r
539 * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control
\r
540 * | | |00 = Do nothing.
\r
541 * | | |01 = EPWM period (center) point output Low.
\r
542 * | | |10 = EPWM period (center) point output High.
\r
543 * | | |11 = EPWM period (center) point output Toggle.
\r
544 * | | |EPWM can control output level when EPWM counter count to (PERIOD2+1).
\r
545 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
\r
546 * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control
\r
547 * | | |00 = Do nothing.
\r
548 * | | |01 = EPWM period (center) point output Low.
\r
549 * | | |10 = EPWM period (center) point output High.
\r
550 * | | |11 = EPWM period (center) point output Toggle.
\r
551 * | | |EPWM can control output level when EPWM counter count to (PERIOD3+1).
\r
552 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
\r
553 * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control
\r
554 * | | |00 = Do nothing.
\r
555 * | | |01 = EPWM period (center) point output Low.
\r
556 * | | |10 = EPWM period (center) point output High.
\r
557 * | | |11 = EPWM period (center) point output Toggle.
\r
558 * | | |EPWM can control output level when EPWM counter count to (PERIOD4+1).
\r
559 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
\r
560 * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control
\r
561 * | | |00 = Do nothing.
\r
562 * | | |01 = EPWM period (center) point output Low.
\r
563 * | | |10 = EPWM period (center) point output High.
\r
564 * | | |11 = EPWM period (center) point output Toggle.
\r
565 * | | |EPWM can control output level when EPWM counter count to (PERIOD5+1).
\r
566 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type.
\r
567 * @var EPWM_T::WGCTL1
\r
568 * Offset: 0xB4 EPWM Generation Register 1
\r
569 * ---------------------------------------------------------------------------------------------------
\r
570 * |Bits |Field |Descriptions
\r
571 * | :----: | :----: | :---- |
\r
572 * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control
\r
573 * | | |00 = Do nothing.
\r
574 * | | |01 = EPWM compare up point output Low.
\r
575 * | | |10 = EPWM compare up point output High.
\r
576 * | | |11 = EPWM compare up point output Toggle.
\r
577 * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
\r
578 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
\r
579 * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control
\r
580 * | | |00 = Do nothing.
\r
581 * | | |01 = EPWM compare up point output Low.
\r
582 * | | |10 = EPWM compare up point output High.
\r
583 * | | |11 = EPWM compare up point output Toggle.
\r
584 * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
\r
585 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
\r
586 * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control
\r
587 * | | |00 = Do nothing.
\r
588 * | | |01 = EPWM compare up point output Low.
\r
589 * | | |10 = EPWM compare up point output High.
\r
590 * | | |11 = EPWM compare up point output Toggle.
\r
591 * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
\r
592 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
\r
593 * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control
\r
594 * | | |00 = Do nothing.
\r
595 * | | |01 = EPWM compare up point output Low.
\r
596 * | | |10 = EPWM compare up point output High.
\r
597 * | | |11 = EPWM compare up point output Toggle.
\r
598 * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
\r
599 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
\r
600 * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control
\r
601 * | | |00 = Do nothing.
\r
602 * | | |01 = EPWM compare up point output Low.
\r
603 * | | |10 = EPWM compare up point output High.
\r
604 * | | |11 = EPWM compare up point output Toggle.
\r
605 * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
\r
606 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
\r
607 * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control
\r
608 * | | |00 = Do nothing.
\r
609 * | | |01 = EPWM compare up point output Low.
\r
610 * | | |10 = EPWM compare up point output High.
\r
611 * | | |11 = EPWM compare up point output Toggle.
\r
612 * | | |EPWM can control output level when EPWM counter up count to CMPDAT.
\r
613 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
\r
614 * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control
\r
615 * | | |00 = Do nothing.
\r
616 * | | |01 = EPWM compare down point output Low.
\r
617 * | | |10 = EPWM compare down point output High.
\r
618 * | | |11 = EPWM compare down point output Toggle.
\r
619 * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
\r
620 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
\r
621 * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control
\r
622 * | | |00 = Do nothing.
\r
623 * | | |01 = EPWM compare down point output Low.
\r
624 * | | |10 = EPWM compare down point output High.
\r
625 * | | |11 = EPWM compare down point output Toggle.
\r
626 * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
\r
627 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
\r
628 * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control
\r
629 * | | |00 = Do nothing.
\r
630 * | | |01 = EPWM compare down point output Low.
\r
631 * | | |10 = EPWM compare down point output High.
\r
632 * | | |11 = EPWM compare down point output Toggle.
\r
633 * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
\r
634 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
\r
635 * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control
\r
636 * | | |00 = Do nothing.
\r
637 * | | |01 = EPWM compare down point output Low.
\r
638 * | | |10 = EPWM compare down point output High.
\r
639 * | | |11 = EPWM compare down point output Toggle.
\r
640 * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
\r
641 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
\r
642 * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control
\r
643 * | | |00 = Do nothing.
\r
644 * | | |01 = EPWM compare down point output Low.
\r
645 * | | |10 = EPWM compare down point output High.
\r
646 * | | |11 = EPWM compare down point output Toggle.
\r
647 * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
\r
648 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
\r
649 * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control
\r
650 * | | |00 = Do nothing.
\r
651 * | | |01 = EPWM compare down point output Low.
\r
652 * | | |10 = EPWM compare down point output High.
\r
653 * | | |11 = EPWM compare down point output Toggle.
\r
654 * | | |EPWM can control output level when EPWM counter down count to CMPDAT.
\r
655 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
\r
656 * @var EPWM_T::MSKEN
\r
657 * Offset: 0xB8 EPWM Mask Enable Register
\r
658 * ---------------------------------------------------------------------------------------------------
\r
659 * |Bits |Field |Descriptions
\r
660 * | :----: | :----: | :---- |
\r
661 * |[0] |MSKEN0 |EPWM Mask Enable Bits
\r
662 * | | |The EPWM output signal will be masked when this bit is enabled.
\r
663 * | | |The corresponding EPWM channel 0 will output MSKDAT0 (EPWM_MSK[5:0]) data.
\r
664 * | | |0 = EPWM output signal is non-masked.
\r
665 * | | |1 = EPWM output signal is masked and output MSKDAT0 data.
\r
666 * |[1] |MSKEN1 |EPWM Mask Enable Bits
\r
667 * | | |The EPWM output signal will be masked when this bit is enabled.
\r
668 * | | |The corresponding EPWM channel 1 will output MSKDAT1 (EPWM_MSK[5:0]) data.
\r
669 * | | |0 = EPWM output signal is non-masked.
\r
670 * | | |1 = EPWM output signal is masked and output MSKDAT1 data.
\r
671 * |[2] |MSKEN2 |EPWM Mask Enable Bits
\r
672 * | | |The EPWM output signal will be masked when this bit is enabled.
\r
673 * | | |The corresponding EPWM channel 2 will output MSKDAT2 (EPWM_MSK[5:0]) data.
\r
674 * | | |0 = EPWM output signal is non-masked.
\r
675 * | | |1 = EPWM output signal is masked and output MSKDAT2 data.
\r
676 * |[3] |MSKEN3 |EPWM Mask Enable Bits
\r
677 * | | |The EPWM output signal will be masked when this bit is enabled.
\r
678 * | | |The corresponding EPWM channel 3 will output MSKDAT3 (EPWM_MSK[5:0]) data.
\r
679 * | | |0 = EPWM output signal is non-masked.
\r
680 * | | |1 = EPWM output signal is masked and output MSKDAT3 data.
\r
681 * |[4] |MSKEN4 |EPWM Mask Enable Bits
\r
682 * | | |The EPWM output signal will be masked when this bit is enabled.
\r
683 * | | |The corresponding EPWM channel 4 will output MSKDAT4 (EPWM_MSK[5:0]) data.
\r
684 * | | |0 = EPWM output signal is non-masked.
\r
685 * | | |1 = EPWM output signal is masked and output MSKDAT4 data.
\r
686 * |[5] |MSKEN5 |EPWM Mask Enable Bits
\r
687 * | | |The EPWM output signal will be masked when this bit is enabled.
\r
688 * | | |The corresponding EPWM channel 5 will output MSKDAT5 (EPWM_MSK[5:0]) data.
\r
689 * | | |0 = EPWM output signal is non-masked.
\r
690 * | | |1 = EPWM output signal is masked and output MSKDAT5 data.
\r
692 * Offset: 0xBC EPWM Mask Data Register
\r
693 * ---------------------------------------------------------------------------------------------------
\r
694 * |Bits |Field |Descriptions
\r
695 * | :----: | :----: | :---- |
\r
696 * |[0] |MSKDAT0 |EPWM Mask Data Bit
\r
697 * | | |This data bit control the state of EPWM_CH0 output pin, if corresponding mask function is enabled.
\r
698 * | | |0 = Output logic low to EPWM_CH0.
\r
699 * | | |1 = Output logic high to EPWM_CH0.
\r
700 * |[1] |MSKDAT1 |EPWM Mask Data Bit
\r
701 * | | |This data bit control the state of EPWM_CH1 output pin, if corresponding mask function is enabled.
\r
702 * | | |0 = Output logic low to EPWM_CH1.
\r
703 * | | |1 = Output logic high to EPWM_CH1.
\r
704 * |[2] |MSKDAT2 |EPWM Mask Data Bit
\r
705 * | | |This data bit control the state of EPWM_CH2 output pin, if corresponding mask function is enabled.
\r
706 * | | |0 = Output logic low to EPWM_CH2.
\r
707 * | | |1 = Output logic high to EPWM_CH2.
\r
708 * |[3] |MSKDAT3 |EPWM Mask Data Bit
\r
709 * | | |This data bit control the state of EPWM_CH3 output pin, if corresponding mask function is enabled.
\r
710 * | | |0 = Output logic low to EPWM_CH3.
\r
711 * | | |1 = Output logic high to EPWM_CH3.
\r
712 * |[4] |MSKDAT4 |EPWM Mask Data Bit
\r
713 * | | |This data bit control the state of EPWM_CH4 output pin, if corresponding mask function is enabled.
\r
714 * | | |0 = Output logic low to EPWM_CH4.
\r
715 * | | |1 = Output logic high to EPWM_CH4.
\r
716 * |[5] |MSKDAT5 |EPWM Mask Data Bit
\r
717 * | | |This data bit control the state of EPWM_CH5 output pin, if corresponding mask function is enabled.
\r
718 * | | |0 = Output logic low to EPWM_CH5.
\r
719 * | | |1 = Output logic high to EPWM_CH5.
\r
721 * Offset: 0xC0 EPWM Brake Noise Filter Register
\r
722 * ---------------------------------------------------------------------------------------------------
\r
723 * |Bits |Field |Descriptions
\r
724 * | :----: | :----: | :---- |
\r
725 * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit
\r
726 * | | |0 = Noise filter of EPWM Brake 0 Disabled.
\r
727 * | | |1 = Noise filter of EPWM Brake 0 Enabled.
\r
728 * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
\r
729 * | | |000 = Filter clock = HCLK.
\r
730 * | | |001 = Filter clock = HCLK/2.
\r
731 * | | |010 = Filter clock = HCLK/4.
\r
732 * | | |011 = Filter clock = HCLK/8.
\r
733 * | | |100 = Filter clock = HCLK/16.
\r
734 * | | |101 = Filter clock = HCLK/32.
\r
735 * | | |110 = Filter clock = HCLK/64.
\r
736 * | | |111 = Filter clock = HCLK/128.
\r
737 * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count
\r
738 * | | |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT.
\r
739 * |[7] |BRK0PINV |Brake 0 Pin Inverse
\r
740 * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector.
\r
741 * | | |1 = The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector.
\r
742 * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit
\r
743 * | | |0 = Noise filter of EPWM Brake 1 Disabled.
\r
744 * | | |1 = Noise filter of EPWM Brake 1 Enabled.
\r
745 * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
\r
746 * | | |000 = Filter clock = HCLK.
\r
747 * | | |001 = Filter clock = HCLK/2.
\r
748 * | | |010 = Filter clock = HCLK/4.
\r
749 * | | |011 = Filter clock = HCLK/8.
\r
750 * | | |100 = Filter clock = HCLK/16.
\r
751 * | | |101 = Filter clock = HCLK/32.
\r
752 * | | |110 = Filter clock = HCLK/64.
\r
753 * | | |111 = Filter clock = HCLK/128.
\r
754 * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count
\r
755 * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
\r
756 * |[15] |BRK1PINV |Brake 1 Pin Inverse
\r
757 * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
\r
758 * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
\r
759 * |[16] |BK0SRC |Brake 0 Pin Source Select
\r
760 * | | |For EPWM0 setting:
\r
761 * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0.
\r
762 * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0.
\r
763 * | | |For EPWM1 setting:
\r
764 * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0.
\r
765 * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0.
\r
766 * |[24] |BK1SRC |Brake 1 Pin Source Select
\r
767 * | | |For EPWM0 setting:
\r
768 * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1.
\r
769 * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1.
\r
770 * | | |For EPWM1 setting:
\r
771 * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1.
\r
772 * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1.
\r
773 * @var EPWM_T::FAILBRK
\r
774 * Offset: 0xC4 EPWM System Fail Brake Control Register
\r
775 * ---------------------------------------------------------------------------------------------------
\r
776 * |Bits |Field |Descriptions
\r
777 * | :----: | :----: | :---- |
\r
778 * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit
\r
779 * | | |0 = Brake Function triggered by CSS detection Disabled.
\r
780 * | | |1 = Brake Function triggered by CSS detection Enabled.
\r
781 * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit
\r
782 * | | |0 = Brake Function triggered by BOD Disabled.
\r
783 * | | |1 = Brake Function triggered by BOD Enabled.
\r
784 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit
\r
785 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
\r
786 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
\r
787 * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit
\r
788 * | | |0 = Brake Function triggered by Core lockup detection Disabled.
\r
789 * | | |1 = Brake Function triggered by Core lockup detection Enabled.
\r
790 * @var EPWM_T::BRKCTL[3]
\r
791 * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5
\r
792 * ---------------------------------------------------------------------------------------------------
\r
793 * |Bits |Field |Descriptions
\r
794 * | :----: | :----: | :---- |
\r
795 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
\r
796 * | | |0 = ACMP0_O as edge-detect brake source Disabled.
\r
797 * | | |1 = ACMP0_O as edge-detect brake source Enabled.
\r
798 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
799 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
\r
800 * | | |0 = ACMP1_O as edge-detect brake source Disabled.
\r
801 * | | |1 = ACMP1_O as edge-detect brake source Enabled.
\r
802 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
803 * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)
\r
804 * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled.
\r
805 * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled.
\r
806 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
807 * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)
\r
808 * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled.
\r
809 * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled.
\r
810 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
811 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect)
\r
812 * | | |0 = System Fail condition as edge-detect brake source Disabled.
\r
813 * | | |1 = System Fail condition as edge-detect brake source Enabled.
\r
814 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
815 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
\r
816 * | | |0 = ACMP0_O as level-detect brake source Disabled.
\r
817 * | | |1 = ACMP0_O as level-detect brake source Enabled.
\r
818 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
819 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
\r
820 * | | |0 = ACMP1_O as level-detect brake source Disabled.
\r
821 * | | |1 = ACMP1_O as level-detect brake source Enabled.
\r
822 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
823 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
\r
824 * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled.
\r
825 * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled.
\r
826 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
827 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
\r
828 * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled.
\r
829 * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled.
\r
830 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
831 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect)
\r
832 * | | |0 = System Fail condition as level-detect brake source Disabled.
\r
833 * | | |1 = System Fail condition as level-detect brake source Enabled.
\r
834 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
835 * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect)
\r
836 * | | |00 = EPWMx brake event will not affect even channels output.
\r
837 * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened.
\r
838 * | | |10 = EPWM even channel output low level when EPWMx brake event happened.
\r
839 * | | |11 = EPWM even channel output high level when EPWMx brake event happened.
\r
840 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
841 * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect)
\r
842 * | | |00 = EPWMx brake event will not affect odd channels output.
\r
843 * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened.
\r
844 * | | |10 = EPWM odd channel output low level when EPWMx brake event happened.
\r
845 * | | |11 = EPWM odd channel output high level when EPWMx brake event happened.
\r
846 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
847 * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)
\r
848 * | | |0 = EADCRM as edge-detect brake source Disabled.
\r
849 * | | |1 = EADCRM as edge-detect brake source Enabled.
\r
850 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
851 * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)
\r
852 * | | |0 = EADCRM as level-detect brake source Disabled.
\r
853 * | | |1 = EADCRM as level-detect brake source Enabled.
\r
854 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
855 * @var EPWM_T::POLCTL
\r
856 * Offset: 0xD4 EPWM Pin Polar Inverse Register
\r
857 * ---------------------------------------------------------------------------------------------------
\r
858 * |Bits |Field |Descriptions
\r
859 * | :----: | :----: | :---- |
\r
860 * |[0] |PINV0 |EPWM_CH0 PIN Polar Inverse Control
\r
861 * | | |The register controls polarity state of EPWM_CH0 output.
\r
862 * | | |0 = EPWM_CH0 output polar inverse Disabled.
\r
863 * | | |1 = EPWM_CH0 output polar inverse Enabled.
\r
864 * |[1] |PINV1 |EPWM_CH1 PIN Polar Inverse Control
\r
865 * | | |The register controls polarity state of EPWM_CH1 output.
\r
866 * | | |0 = EPWM_CH1 output polar inverse Disabled.
\r
867 * | | |1 = EPWM_CH1 output polar inverse Enabled.
\r
868 * |[2] |PINV2 |EPWM_CH2 PIN Polar Inverse Control
\r
869 * | | |The register controls polarity state of EPWM_CH2 output.
\r
870 * | | |0 = EPWM_CH2 output polar inverse Disabled.
\r
871 * | | |1 = EPWM_CH2 output polar inverse Enabled.
\r
872 * |[3] |PINV3 |EPWM_CH3 PIN Polar Inverse Control
\r
873 * | | |The register controls polarity state of EPWM_CH3 output.
\r
874 * | | |0 = EPWM_CH3 output polar inverse Disabled.
\r
875 * | | |1 = EPWM_CH3 output polar inverse Enabled.
\r
876 * |[4] |PINV4 |EPWM_CH4 PIN Polar Inverse Control
\r
877 * | | |The register controls polarity state of EPWM_CH4 output.
\r
878 * | | |0 = EPWM_CH4 output polar inverse Disabled.
\r
879 * | | |1 = EPWM_CH4 output polar inverse Enabled.
\r
880 * |[5] |PINV5 |EPWM_CH5 PIN Polar Inverse Control
\r
881 * | | |The register controls polarity state of EPWM_CH5 output.
\r
882 * | | |0 = EPWM_CH5 output polar inverse Disabled.
\r
883 * | | |1 = EPWM_CH5 output polar inverse Enabled.
\r
884 * @var EPWM_T::POEN
\r
885 * Offset: 0xD8 EPWM Output Enable Register
\r
886 * ---------------------------------------------------------------------------------------------------
\r
887 * |Bits |Field |Descriptions
\r
888 * | :----: | :----: | :---- |
\r
889 * |[0] |POEN0 |EPWM_CH0 Pin Output Enable Bits
\r
890 * | | |0 = EPWM_CH0 pin at tri-state.
\r
891 * | | |1 = EPWM_CH0 pin in output mode.
\r
892 * |[1] |POEN1 |EPWM_CH1 Pin Output Enable Bits
\r
893 * | | |0 = EPWM_CH1 pin at tri-state.
\r
894 * | | |1 = EPWM_CH1 pin in output mode.
\r
895 * |[2] |POEN2 |EPWM_CH2 Pin Output Enable Bits
\r
896 * | | |0 = EPWM_CH2 pin at tri-state.
\r
897 * | | |1 = EPWM_CH2 pin in output mode.
\r
898 * |[3] |POEN3 |EPWM_CH3 Pin Output Enable Bits
\r
899 * | | |0 = EPWM_CH3 pin at tri-state.
\r
900 * | | |1 = EPWM_CH3 pin in output mode.
\r
901 * |[4] |POEN4 |EPWM_CH4 Pin Output Enable Bits
\r
902 * | | |0 = EPWM_CH4 pin at tri-state.
\r
903 * | | |1 = EPWM_CH4 pin in output mode.
\r
904 * |[5] |POEN5 |EPWM_CH5 Pin Output Enable Bits
\r
905 * | | |0 = EPWM_CH5 pin at tri-state.
\r
906 * | | |1 = EPWM_CH5 pin in output mode.
\r
907 * @var EPWM_T::SWBRK
\r
908 * Offset: 0xDC EPWM Software Brake Control Register
\r
909 * ---------------------------------------------------------------------------------------------------
\r
910 * |Bits |Field |Descriptions
\r
911 * | :----: | :----: | :---- |
\r
912 * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
\r
913 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF0 to 1 in EPWM_INTSTS1 register.
\r
914 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
915 * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
\r
916 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF2 to 1 in EPWM_INTSTS1 register.
\r
917 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
918 * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
\r
919 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF4 to 1 in EPWM_INTSTS1 register.
\r
920 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
921 * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
\r
922 * | | |Write 1 to this bit will trigger level brake, and set BRKLIF0 to 1 in EPWM_INTSTS1 register.
\r
923 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
924 * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
\r
925 * | | |Write 1 to this bit will trigger level brake, and set BRKLIF2 to 1 in EPWM_INTSTS1 register.
\r
926 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
927 * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
\r
928 * | | |Write 1 to this bit will trigger level brake, and set BRKLIF4 to 1 in EPWM_INTSTS1 register.
\r
929 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
930 * @var EPWM_T::INTEN0
\r
931 * Offset: 0xE0 EPWM Interrupt Enable Register 0
\r
932 * ---------------------------------------------------------------------------------------------------
\r
933 * |Bits |Field |Descriptions
\r
934 * | :----: | :----: | :---- |
\r
935 * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits
\r
936 * | | |0 = Zero point interrupt Disabled.
\r
937 * | | |1 = Zero point interrupt Enabled.
\r
938 * | | |Note: Odd channels will read always 0 at complementary mode.
\r
939 * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits
\r
940 * | | |0 = Zero point interrupt Disabled.
\r
941 * | | |1 = Zero point interrupt Enabled.
\r
942 * | | |Note: Odd channels will read always 0 at complementary mode.
\r
943 * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits
\r
944 * | | |0 = Zero point interrupt Disabled.
\r
945 * | | |1 = Zero point interrupt Enabled.
\r
946 * | | |Note: Odd channels will read always 0 at complementary mode.
\r
947 * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits
\r
948 * | | |0 = Zero point interrupt Disabled.
\r
949 * | | |1 = Zero point interrupt Enabled.
\r
950 * | | |Note: Odd channels will read always 0 at complementary mode.
\r
951 * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits
\r
952 * | | |0 = Zero point interrupt Disabled.
\r
953 * | | |1 = Zero point interrupt Enabled.
\r
954 * | | |Note: Odd channels will read always 0 at complementary mode.
\r
955 * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits
\r
956 * | | |0 = Zero point interrupt Disabled.
\r
957 * | | |1 = Zero point interrupt Enabled.
\r
958 * | | |Note: Odd channels will read always 0 at complementary mode.
\r
959 * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits
\r
960 * | | |0 = Period point interrupt Disabled.
\r
961 * | | |1 = Period point interrupt Enabled.
\r
962 * | | |Note1: When up-down counter type period point means center point.
\r
963 * | | |Note2: Odd channels will read always 0 at complementary mode.
\r
964 * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits
\r
965 * | | |0 = Period point interrupt Disabled.
\r
966 * | | |1 = Period point interrupt Enabled.
\r
967 * | | |Note1: When up-down counter type period point means center point.
\r
968 * | | |Note2: Odd channels will read always 0 at complementary mode.
\r
969 * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits
\r
970 * | | |0 = Period point interrupt Disabled.
\r
971 * | | |1 = Period point interrupt Enabled.
\r
972 * | | |Note1: When up-down counter type period point means center point.
\r
973 * | | |Note2: Odd channels will read always 0 at complementary mode.
\r
974 * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits
\r
975 * | | |0 = Period point interrupt Disabled.
\r
976 * | | |1 = Period point interrupt Enabled.
\r
977 * | | |Note1: When up-down counter type period point means center point.
\r
978 * | | |Note2: Odd channels will read always 0 at complementary mode.
\r
979 * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits
\r
980 * | | |0 = Period point interrupt Disabled.
\r
981 * | | |1 = Period point interrupt Enabled.
\r
982 * | | |Note1: When up-down counter type period point means center point.
\r
983 * | | |Note2: Odd channels will read always 0 at complementary mode.
\r
984 * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits
\r
985 * | | |0 = Period point interrupt Disabled.
\r
986 * | | |1 = Period point interrupt Enabled.
\r
987 * | | |Note1: When up-down counter type period point means center point.
\r
988 * | | |Note2: Odd channels will read always 0 at complementary mode.
\r
989 * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits
\r
990 * | | |0 = Compare up count interrupt Disabled.
\r
991 * | | |1 = Compare up count interrupt Enabled.
\r
992 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
\r
993 * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits
\r
994 * | | |0 = Compare up count interrupt Disabled.
\r
995 * | | |1 = Compare up count interrupt Enabled.
\r
996 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
\r
997 * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits
\r
998 * | | |0 = Compare up count interrupt Disabled.
\r
999 * | | |1 = Compare up count interrupt Enabled.
\r
1000 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
\r
1001 * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits
\r
1002 * | | |0 = Compare up count interrupt Disabled.
\r
1003 * | | |1 = Compare up count interrupt Enabled.
\r
1004 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
\r
1005 * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits
\r
1006 * | | |0 = Compare up count interrupt Disabled.
\r
1007 * | | |1 = Compare up count interrupt Enabled.
\r
1008 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
\r
1009 * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits
\r
1010 * | | |0 = Compare up count interrupt Disabled.
\r
1011 * | | |1 = Compare up count interrupt Enabled.
\r
1012 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
\r
1013 * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits
\r
1014 * | | |0 = Compare down count interrupt Disabled.
\r
1015 * | | |1 = Compare down count interrupt Enabled.
\r
1016 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
\r
1017 * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits
\r
1018 * | | |0 = Compare down count interrupt Disabled.
\r
1019 * | | |1 = Compare down count interrupt Enabled.
\r
1020 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
\r
1021 * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits
\r
1022 * | | |0 = Compare down count interrupt Disabled.
\r
1023 * | | |1 = Compare down count interrupt Enabled.
\r
1024 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
\r
1025 * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits
\r
1026 * | | |0 = Compare down count interrupt Disabled.
\r
1027 * | | |1 = Compare down count interrupt Enabled.
\r
1028 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
\r
1029 * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits
\r
1030 * | | |0 = Compare down count interrupt Disabled.
\r
1031 * | | |1 = Compare down count interrupt Enabled.
\r
1032 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
\r
1033 * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits
\r
1034 * | | |0 = Compare down count interrupt Disabled.
\r
1035 * | | |1 = Compare down count interrupt Enabled.
\r
1036 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
\r
1037 * @var EPWM_T::INTEN1
\r
1038 * Offset: 0xE4 EPWM Interrupt Enable Register 1
\r
1039 * ---------------------------------------------------------------------------------------------------
\r
1040 * |Bits |Field |Descriptions
\r
1041 * | :----: | :----: | :---- |
\r
1042 * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
\r
1043 * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
\r
1044 * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
\r
1045 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1046 * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
\r
1047 * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
\r
1048 * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
\r
1049 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1050 * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
\r
1051 * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
\r
1052 * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
\r
1053 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1054 * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
\r
1055 * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled.
\r
1056 * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled.
\r
1057 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1058 * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
\r
1059 * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled.
\r
1060 * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled.
\r
1061 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1062 * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
\r
1063 * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled.
\r
1064 * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled.
\r
1065 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1066 * @var EPWM_T::INTSTS0
\r
1067 * Offset: 0xE8 EPWM Interrupt Flag Register 0
\r
1068 * ---------------------------------------------------------------------------------------------------
\r
1069 * |Bits |Field |Descriptions
\r
1070 * | :----: | :----: | :---- |
\r
1071 * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag
\r
1072 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
\r
1073 * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag
\r
1074 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
\r
1075 * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag
\r
1076 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
\r
1077 * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag
\r
1078 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
\r
1079 * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag
\r
1080 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
\r
1081 * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag
\r
1082 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
\r
1083 * |[8] |PIF0 |EPWM Period Point Interrupt Flag
\r
1084 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD0, software can write 1 to clear this bit to zero
\r
1085 * |[9] |PIF1 |EPWM Period Point Interrupt Flag
\r
1086 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD1, software can write 1 to clear this bit to zero
\r
1087 * |[10] |PIF2 |EPWM Period Point Interrupt Flag
\r
1088 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD2, software can write 1 to clear this bit to zero
\r
1089 * |[11] |PIF3 |EPWM Period Point Interrupt Flag
\r
1090 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD4, software can write 1 to clear this bit to zero
\r
1091 * |[12] |PIF4 |EPWM Period Point Interrupt Flag
\r
1092 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD5, software can write 1 to clear this bit to zero
\r
1093 * |[13] |PIF5 |EPWM Period Point Interrupt Flag
\r
1094 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
\r
1095 * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag
\r
1096 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it.
\r
1097 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
\r
1098 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
\r
1099 * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag
\r
1100 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it.
\r
1101 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
\r
1102 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
\r
1103 * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag
\r
1104 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it.
\r
1105 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
\r
1106 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
\r
1107 * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag
\r
1108 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it.
\r
1109 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
\r
1110 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
\r
1111 * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag
\r
1112 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it.
\r
1113 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
\r
1114 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
\r
1115 * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag
\r
1116 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it.
\r
1117 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
\r
1118 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
\r
1119 * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag
\r
1120 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it.
\r
1121 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
\r
1122 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
\r
1123 * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag
\r
1124 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it.
\r
1125 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
\r
1126 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
\r
1127 * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag
\r
1128 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it.
\r
1129 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
\r
1130 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
\r
1131 * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag
\r
1132 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it.
\r
1133 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
\r
1134 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
\r
1135 * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag
\r
1136 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it.
\r
1137 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
\r
1138 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
\r
1139 * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag
\r
1140 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it.
\r
1141 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
\r
1142 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
\r
1143 * @var EPWM_T::INTSTS1
\r
1144 * Offset: 0xEC EPWM Interrupt Flag Register 1
\r
1145 * ---------------------------------------------------------------------------------------------------
\r
1146 * |Bits |Field |Descriptions
\r
1147 * | :----: | :----: | :---- |
\r
1148 * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)
\r
1149 * | | |0 = EPWM channel0 edge-detect brake event do not happened.
\r
1150 * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1151 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1152 * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)
\r
1153 * | | |0 = EPWM channel1 edge-detect brake event do not happened.
\r
1154 * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1155 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1156 * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)
\r
1157 * | | |0 = EPWM channel2 edge-detect brake event do not happened.
\r
1158 * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1159 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1160 * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)
\r
1161 * | | |0 = EPWM channel3 edge-detect brake event do not happened.
\r
1162 * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1163 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1164 * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)
\r
1165 * | | |0 = EPWM channel4 edge-detect brake event do not happened.
\r
1166 * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1167 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1168 * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)
\r
1169 * | | |0 = EPWM channel5 edge-detect brake event do not happened.
\r
1170 * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1171 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1172 * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)
\r
1173 * | | |0 = EPWM channel0 level-detect brake event do not happened.
\r
1174 * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1175 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1176 * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)
\r
1177 * | | |0 = EPWM channel1 level-detect brake event do not happened.
\r
1178 * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1179 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1180 * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)
\r
1181 * | | |0 = EPWM channel2 level-detect brake event do not happened.
\r
1182 * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1183 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1184 * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)
\r
1185 * | | |0 = EPWM channel3 level-detect brake event do not happened.
\r
1186 * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1187 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1188 * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)
\r
1189 * | | |0 = EPWM channel4 level-detect brake event do not happened.
\r
1190 * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1191 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1192 * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)
\r
1193 * | | |0 = EPWM channel5 level-detect brake event do not happened.
\r
1194 * | | |1 = When EPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
\r
1195 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
\r
1196 * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only)
\r
1197 * | | |0 = EPWM channel0 edge-detect brake state is released.
\r
1198 * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear.
\r
1199 * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only)
\r
1200 * | | |0 = EPWM channel1 edge-detect brake state is released.
\r
1201 * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear.
\r
1202 * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only)
\r
1203 * | | |0 = EPWM channel2 edge-detect brake state is released.
\r
1204 * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear.
\r
1205 * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only)
\r
1206 * | | |0 = EPWM channel3 edge-detect brake state is released.
\r
1207 * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear.
\r
1208 * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only)
\r
1209 * | | |0 = EPWM channel4 edge-detect brake state is released.
\r
1210 * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear.
\r
1211 * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only)
\r
1212 * | | |0 = EPWM channel5 edge-detect brake state is released.
\r
1213 * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear.
\r
1214 * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only)
\r
1215 * | | |0 = EPWM channel0 level-detect brake state is released.
\r
1216 * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state.
\r
1217 * | | |Note: This bit is read only and auto cleared by hardware
\r
1218 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
\r
1219 * | | |The EPWM waveform will start output from next full EPWM period.
\r
1220 * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only)
\r
1221 * | | |0 = EPWM channel1 level-detect brake state is released.
\r
1222 * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state.
\r
1223 * | | |Note: This bit is read only and auto cleared by hardware
\r
1224 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
\r
1225 * | | |The EPWM waveform will start output from next full EPWM period.
\r
1226 * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only)
\r
1227 * | | |0 = EPWM channel2 level-detect brake state is released.
\r
1228 * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state.
\r
1229 * | | |Note: This bit is read only and auto cleared by hardware
\r
1230 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
\r
1231 * | | |The EPWM waveform will start output from next full EPWM period.
\r
1232 * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only)
\r
1233 * | | |0 = EPWM channel3 level-detect brake state is released.
\r
1234 * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state.
\r
1235 * | | |Note: This bit is read only and auto cleared by hardware
\r
1236 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
\r
1237 * | | |The EPWM waveform will start output from next full EPWM period.
\r
1238 * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only)
\r
1239 * | | |0 = EPWM channel4 level-detect brake state is released.
\r
1240 * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state.
\r
1241 * | | |Note: This bit is read only and auto cleared by hardware
\r
1242 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
\r
1243 * | | |The EPWM waveform will start output from next full EPWM period.
\r
1244 * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only)
\r
1245 * | | |0 = EPWM channel5 level-detect brake state is released.
\r
1246 * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state.
\r
1247 * | | |Note: This bit is read only and auto cleared by hardware
\r
1248 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
\r
1249 * | | |The EPWM waveform will start output from next full EPWM period.
\r
1250 * @var EPWM_T::DACTRGEN
\r
1251 * Offset: 0xF4 EPWM Trigger DAC Enable Register
\r
1252 * ---------------------------------------------------------------------------------------------------
\r
1253 * |Bits |Field |Descriptions
\r
1254 * | :----: | :----: | :---- |
\r
1255 * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits
\r
1256 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
\r
1257 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1258 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1259 * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits
\r
1260 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
\r
1261 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1262 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1263 * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits
\r
1264 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
\r
1265 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1266 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1267 * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits
\r
1268 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
\r
1269 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1270 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1271 * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits
\r
1272 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
\r
1273 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1274 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1275 * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits
\r
1276 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
\r
1277 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1278 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1279 * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits
\r
1280 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
\r
1281 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1282 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1283 * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits
\r
1284 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
\r
1285 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1286 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1287 * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits
\r
1288 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
\r
1289 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1290 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1291 * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits
\r
1292 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
\r
1293 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1294 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1295 * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits
\r
1296 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
\r
1297 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1298 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1299 * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits
\r
1300 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
\r
1301 * | | |0 = EPWM period point trigger DAC function Disabled.
\r
1302 * | | |1 = EPWM period point trigger DAC function Enabled.
\r
1303 * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits
\r
1304 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
\r
1305 * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
\r
1306 * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
\r
1307 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
\r
1308 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
\r
1309 * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits
\r
1310 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
\r
1311 * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
\r
1312 * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
\r
1313 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
\r
1314 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
\r
1315 * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits
\r
1316 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
\r
1317 * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
\r
1318 * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
\r
1319 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
\r
1320 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
\r
1321 * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits
\r
1322 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
\r
1323 * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
\r
1324 * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
\r
1325 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
\r
1326 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
\r
1327 * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits
\r
1328 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
\r
1329 * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
\r
1330 * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
\r
1331 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
\r
1332 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
\r
1333 * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits
\r
1334 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
\r
1335 * | | |0 = EPWM Compare Up point trigger DAC function Disabled.
\r
1336 * | | |1 = EPWM Compare Up point trigger DAC function Enabled.
\r
1337 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
\r
1338 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
\r
1339 * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits
\r
1340 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
\r
1341 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
\r
1342 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
\r
1343 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
\r
1344 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
\r
1345 * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits
\r
1346 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
\r
1347 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
\r
1348 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
\r
1349 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
\r
1350 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
\r
1351 * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits
\r
1352 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
\r
1353 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
\r
1354 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
\r
1355 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
\r
1356 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
\r
1357 * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits
\r
1358 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
\r
1359 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
\r
1360 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
\r
1361 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
\r
1362 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
\r
1363 * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits
\r
1364 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
\r
1365 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
\r
1366 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
\r
1367 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
\r
1368 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
\r
1369 * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits
\r
1370 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
\r
1371 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled.
\r
1372 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled.
\r
1373 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
\r
1374 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
\r
1375 * @var EPWM_T::EADCTS0
\r
1376 * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0
\r
1377 * ---------------------------------------------------------------------------------------------------
\r
1378 * |Bits |Field |Descriptions
\r
1379 * | :----: | :----: | :---- |
\r
1380 * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select
\r
1381 * | | |0000 = EPWM_CH0 zero point.
\r
1382 * | | |0001 = EPWM_CH0 period point.
\r
1383 * | | |0010 = EPWM_CH0 zero or period point.
\r
1384 * | | |0011 = EPWM_CH0 up-count CMPDAT point.
\r
1385 * | | |0100 = EPWM_CH0 down-count CMPDAT point.
\r
1386 * | | |0101 = EPWM_CH1 zero point.
\r
1387 * | | |0110 = EPWM_CH1 period point.
\r
1388 * | | |0111 = EPWM_CH1 zero or period point.
\r
1389 * | | |1000 = EPWM_CH1 up-count CMPDAT point.
\r
1390 * | | |1001 = EPWM_CH1 down-count CMPDAT point.
\r
1391 * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
\r
1392 * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
\r
1393 * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
\r
1394 * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
\r
1395 * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
\r
1396 * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
\r
1397 * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit
\r
1398 * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select
\r
1399 * | | |0000 = EPWM_CH0 zero point.
\r
1400 * | | |0001 = EPWM_CH0 period point.
\r
1401 * | | |0010 = EPWM_CH0 zero or period point.
\r
1402 * | | |0011 = EPWM_CH0 up-count CMPDAT point.
\r
1403 * | | |0100 = EPWM_CH0 down-count CMPDAT point.
\r
1404 * | | |0101 = EPWM_CH1 zero point.
\r
1405 * | | |0110 = EPWM_CH1 period point.
\r
1406 * | | |0111 = EPWM_CH1 zero or period point.
\r
1407 * | | |1000 = EPWM_CH1 up-count CMPDAT point.
\r
1408 * | | |1001 = EPWM_CH1 down-count CMPDAT point.
\r
1409 * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
\r
1410 * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
\r
1411 * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
\r
1412 * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
\r
1413 * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
\r
1414 * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
\r
1415 * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit
\r
1416 * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select
\r
1417 * | | |0000 = EPWM_CH2 zero point.
\r
1418 * | | |0001 = EPWM_CH2 period point.
\r
1419 * | | |0010 = EPWM_CH2 zero or period point.
\r
1420 * | | |0011 = EPWM_CH2 up-count CMPDAT point.
\r
1421 * | | |0100 = EPWM_CH2 down-count CMPDAT point.
\r
1422 * | | |0101 = EPWM_CH3 zero point.
\r
1423 * | | |0110 = EPWM_CH3 period point.
\r
1424 * | | |0111 = EPWM_CH3 zero or period point.
\r
1425 * | | |1000 = EPWM_CH3 up-count CMPDAT point.
\r
1426 * | | |1001 = EPWM_CH3 down-count CMPDAT point.
\r
1427 * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
\r
1428 * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
\r
1429 * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
\r
1430 * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
\r
1431 * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
\r
1432 * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
\r
1433 * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit
\r
1434 * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select
\r
1435 * | | |0000 = EPWM_CH2 zero point.
\r
1436 * | | |0001 = EPWM_CH2 period point.
\r
1437 * | | |0010 = EPWM_CH2 zero or period point.
\r
1438 * | | |0011 = EPWM_CH2 up-count CMPDAT point.
\r
1439 * | | |0100 = EPWM_CH2 down-count CMPDAT point.
\r
1440 * | | |0101 = EPWM_CH3 zero point.
\r
1441 * | | |0110 = EPWM_CH3 period point.
\r
1442 * | | |0111 = EPWM_CH3 zero or period point.
\r
1443 * | | |1000 = EPWM_CH3 up-count CMPDAT point.
\r
1444 * | | |1001 = EPWM_CH3 down-count CMPDAT point.
\r
1445 * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
\r
1446 * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
\r
1447 * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
\r
1448 * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
\r
1449 * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
\r
1450 * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
\r
1451 * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit
\r
1452 * @var EPWM_T::EADCTS1
\r
1453 * Offset: 0xFC EPWM Trigger EADC Source Select Register 1
\r
1454 * ---------------------------------------------------------------------------------------------------
\r
1455 * |Bits |Field |Descriptions
\r
1456 * | :----: | :----: | :---- |
\r
1457 * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select
\r
1458 * | | |0000 = EPWM_CH4 zero point.
\r
1459 * | | |0001 = EPWM_CH4 period point.
\r
1460 * | | |0010 = EPWM_CH4 zero or period point.
\r
1461 * | | |0011 = EPWM_CH4 up-count CMPDAT point.
\r
1462 * | | |0100 = EPWM_CH4 down-count CMPDAT point.
\r
1463 * | | |0101 = EPWM_CH5 zero point.
\r
1464 * | | |0110 = EPWM_CH5 period point.
\r
1465 * | | |0111 = EPWM_CH5 zero or period point.
\r
1466 * | | |1000 = EPWM_CH5 up-count CMPDAT point.
\r
1467 * | | |1001 = EPWM_CH5 down-count CMPDAT point.
\r
1468 * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
\r
1469 * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
\r
1470 * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
\r
1471 * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
\r
1472 * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
\r
1473 * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
\r
1474 * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit
\r
1475 * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select
\r
1476 * | | |0000 = EPWM_CH4 zero point.
\r
1477 * | | |0001 = EPWM_CH4 period point.
\r
1478 * | | |0010 = EPWM_CH4 zero or period point.
\r
1479 * | | |0011 = EPWM_CH4 up-count CMPDAT point.
\r
1480 * | | |0100 = EPWM_CH4 down-count CMPDAT point.
\r
1481 * | | |0101 = EPWM_CH5 zero point.
\r
1482 * | | |0110 = EPWM_CH5 period point.
\r
1483 * | | |0111 = EPWM_CH5 zero or period point.
\r
1484 * | | |1000 = EPWM_CH5 up-count CMPDAT point.
\r
1485 * | | |1001 = EPWM_CH5 down-count CMPDAT point.
\r
1486 * | | |1010 = EPWM_CH0 up-count free CMPDAT point.
\r
1487 * | | |1011 = EPWM_CH0 down-count free CMPDAT point.
\r
1488 * | | |1100 = EPWM_CH2 up-count free CMPDAT point.
\r
1489 * | | |1101 = EPWM_CH2 down-count free CMPDAT point.
\r
1490 * | | |1110 = EPWM_CH4 up-count free CMPDAT point.
\r
1491 * | | |1111 = EPWM_CH4 down-count free CMPDAT point.
\r
1492 * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit
\r
1493 * @var EPWM_T::FTCMPDAT[3]
\r
1494 * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5
\r
1495 * ---------------------------------------------------------------------------------------------------
\r
1496 * |Bits |Field |Descriptions
\r
1497 * | :----: | :----: | :---- |
\r
1498 * |[15:0] |FTCMP |EPWM Free Trigger Compare Register
\r
1499 * | | |FTCMP use to compare with even CNTR to trigger EADC
\r
1500 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
\r
1501 * @var EPWM_T::SSCTL
\r
1502 * Offset: 0x110 EPWM Synchronous Start Control Register
\r
1503 * ---------------------------------------------------------------------------------------------------
\r
1504 * |Bits |Field |Descriptions
\r
1505 * | :----: | :----: | :---- |
\r
1506 * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits
\r
1507 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
\r
1508 * | | |0 = EPWM synchronous start function Disabled.
\r
1509 * | | |1 = EPWM synchronous start function Enabled.
\r
1510 * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits
\r
1511 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
\r
1512 * | | |0 = EPWM synchronous start function Disabled.
\r
1513 * | | |1 = EPWM synchronous start function Enabled.
\r
1514 * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits
\r
1515 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
\r
1516 * | | |0 = EPWM synchronous start function Disabled.
\r
1517 * | | |1 = EPWM synchronous start function Enabled.
\r
1518 * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits
\r
1519 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
\r
1520 * | | |0 = EPWM synchronous start function Disabled.
\r
1521 * | | |1 = EPWM synchronous start function Enabled.
\r
1522 * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits
\r
1523 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
\r
1524 * | | |0 = EPWM synchronous start function Disabled.
\r
1525 * | | |1 = EPWM synchronous start function Enabled.
\r
1526 * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits
\r
1527 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
\r
1528 * | | |0 = EPWM synchronous start function Disabled.
\r
1529 * | | |1 = EPWM synchronous start function Enabled.
\r
1530 * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits
\r
1531 * | | |00 = Synchronous start source come from EPWM0.
\r
1532 * | | |01 = Synchronous start source come from EPWM1.
\r
1533 * | | |10 = Synchronous start source come from BPWM0.
\r
1534 * | | |11 = Synchronous start source come from BPWM1.
\r
1535 * @var EPWM_T::SSTRG
\r
1536 * Offset: 0x114 EPWM Synchronous Start Trigger Register
\r
1537 * ---------------------------------------------------------------------------------------------------
\r
1538 * |Bits |Field |Descriptions
\r
1539 * | :----: | :----: | :---- |
\r
1540 * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only)
\r
1541 * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.
\r
1542 * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled.
\r
1543 * @var EPWM_T::LEBCTL
\r
1544 * Offset: 0x118 EPWM Leading Edge Blanking Control Register
\r
1545 * ---------------------------------------------------------------------------------------------------
\r
1546 * |Bits |Field |Descriptions
\r
1547 * | :----: | :----: | :---- |
\r
1548 * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit
\r
1549 * | | |0 = EPWM Leading Edge Blanking Disabled.
\r
1550 * | | |1 = EPWM Leading Edge Blanking Enabled.
\r
1551 * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit
\r
1552 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled.
\r
1553 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled.
\r
1554 * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit
\r
1555 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled.
\r
1556 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled.
\r
1557 * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit
\r
1558 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled.
\r
1559 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled.
\r
1560 * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type
\r
1561 * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting.
\r
1562 * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting.
\r
1563 * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting.
\r
1564 * | | |3 = Reserved.
\r
1565 * @var EPWM_T::LEBCNT
\r
1566 * Offset: 0x11C EPWM Leading Edge Blanking Counter Register
\r
1567 * ---------------------------------------------------------------------------------------------------
\r
1568 * |Bits |Field |Descriptions
\r
1569 * | :----: | :----: | :---- |
\r
1570 * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter
\r
1571 * | | |This counter value decides leading edge blanking window size.
\r
1572 * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK.
\r
1573 * @var EPWM_T::STATUS
\r
1574 * Offset: 0x120 EPWM Status Register
\r
1575 * ---------------------------------------------------------------------------------------------------
\r
1576 * |Bits |Field |Descriptions
\r
1577 * | :----: | :----: | :---- |
\r
1578 * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag
\r
1579 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
\r
1580 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
\r
1581 * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag
\r
1582 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
\r
1583 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
\r
1584 * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag
\r
1585 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
\r
1586 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
\r
1587 * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag
\r
1588 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
\r
1589 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
\r
1590 * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag
\r
1591 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
\r
1592 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
\r
1593 * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag
\r
1594 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
\r
1595 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
\r
1596 * |[8] |SYNCINF0 |Input Synchronization Latched Flag
\r
1597 * | | |0 = Indicates no SYNC_IN event has occurred.
\r
1598 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
\r
1599 * |[9] |SYNCINF2 |Input Synchronization Latched Flag
\r
1600 * | | |0 = Indicates no SYNC_IN event has occurred.
\r
1601 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
\r
1602 * |[10] |SYNCINF4 |Input Synchronization Latched Flag
\r
1603 * | | |0 = Indicates no SYNC_IN event has occurred.
\r
1604 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
\r
1605 * |[16] |EADCTRGF0 |EADC Start of Conversion Flag
\r
1606 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
\r
1607 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
\r
1608 * |[17] |EADCTRGF1 |EADC Start of Conversion Flag
\r
1609 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
\r
1610 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
\r
1611 * |[18] |EADCTRGF2 |EADC Start of Conversion Flag
\r
1612 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
\r
1613 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
\r
1614 * |[19] |EADCTRGF3 |EADC Start of Conversion Flag
\r
1615 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
\r
1616 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
\r
1617 * |[20] |EADCTRGF4 |EADC Start of Conversion Flag
\r
1618 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
\r
1619 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
\r
1620 * |[21] |EADCTRGF5 |EADC Start of Conversion Flag
\r
1621 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
\r
1622 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
\r
1623 * |[24] |DACTRGF |DAC Start of Conversion Flag
\r
1624 * | | |0 = Indicates no DAC start of conversion trigger event has occurred.
\r
1625 * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
\r
1626 * @var EPWM_T::IFA[6]
\r
1627 * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5
\r
1628 * ---------------------------------------------------------------------------------------------------
\r
1629 * |Bits |Field |Descriptions
\r
1630 * | :----: | :----: | :---- |
\r
1631 * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter
\r
1632 * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.
\r
1633 * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period.
\r
1634 * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select
\r
1635 * | | |00 = CNT equal to Zero in channel n.
\r
1636 * | | |01 = CNT equal to PERIOD in channel n.
\r
1637 * | | |10 = CNT equal to CMPU in channel n.
\r
1638 * | | |11 = CNT equal to CMPD in channel n.
\r
1639 * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits
\r
1640 * | | |0 = EPWM_CHn interrupt flag accumulator disable.
\r
1641 * | | |1 = EPWM_CHn interrupt flag accumulator enable.
\r
1642 * @var EPWM_T::AINTSTS
\r
1643 * Offset: 0x150 EPWM Accumulator Interrupt Flag Register
\r
1644 * ---------------------------------------------------------------------------------------------------
\r
1645 * |Bits |Field |Descriptions
\r
1646 * | :----: | :----: | :---- |
\r
1647 * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
\r
1648 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
\r
1649 * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
\r
1650 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
\r
1651 * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
\r
1652 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
\r
1653 * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
\r
1654 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
\r
1655 * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
\r
1656 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
\r
1657 * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
\r
1658 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
\r
1659 * @var EPWM_T::AINTEN
\r
1660 * Offset: 0x154 EPWM Accumulator Interrupt Enable Register
\r
1661 * ---------------------------------------------------------------------------------------------------
\r
1662 * |Bits |Field |Descriptions
\r
1663 * | :----: | :----: | :---- |
\r
1664 * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
\r
1665 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
\r
1666 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
\r
1667 * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
\r
1668 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
\r
1669 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
\r
1670 * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
\r
1671 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
\r
1672 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
\r
1673 * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
\r
1674 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
\r
1675 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
\r
1676 * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
\r
1677 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
\r
1678 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
\r
1679 * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
\r
1680 * | | |0 = Interrupt Flag accumulator interrupt Disabled.
\r
1681 * | | |1 = Interrupt Flag accumulator interrupt Enabled.
\r
1682 * @var EPWM_T::APDMACTL
\r
1683 * Offset: 0x158 EPWM Accumulator PDMA Control Register
\r
1684 * ---------------------------------------------------------------------------------------------------
\r
1685 * |Bits |Field |Descriptions
\r
1686 * | :----: | :----: | :---- |
\r
1687 * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits
\r
1688 * | | |0 = Channel n PDMA function Disabled.
\r
1689 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
\r
1690 * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits
\r
1691 * | | |0 = Channel n PDMA function Disabled.
\r
1692 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
\r
1693 * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits
\r
1694 * | | |0 = Channel n PDMA function Disabled.
\r
1695 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
\r
1696 * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits
\r
1697 * | | |0 = Channel n PDMA function Disabled.
\r
1698 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
\r
1699 * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits
\r
1700 * | | |0 = Channel n PDMA function Disabled.
\r
1701 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
\r
1702 * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits
\r
1703 * | | |0 = Channel n PDMA function Disabled.
\r
1704 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
\r
1705 * @var EPWM_T::CAPINEN
\r
1706 * Offset: 0x200 EPWM Capture Input Enable Register
\r
1707 * ---------------------------------------------------------------------------------------------------
\r
1708 * |Bits |Field |Descriptions
\r
1709 * | :----: | :----: | :---- |
\r
1710 * |[0] |CAPINEN0 |Capture Input Enable Bits
\r
1711 * | | |0 = EPWM Channel capture input path Disabled
\r
1712 * | | |The input of EPWM channel capture function is always regarded as 0.
\r
1713 * | | |1 = EPWM Channel capture input path Enabled
\r
1714 * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
\r
1715 * |[1] |CAPINEN1 |Capture Input Enable Bits
\r
1716 * | | |0 = EPWM Channel capture input path Disabled
\r
1717 * | | |The input of EPWM channel capture function is always regarded as 0.
\r
1718 * | | |1 = EPWM Channel capture input path Enabled
\r
1719 * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
\r
1720 * |[2] |CAPINEN2 |Capture Input Enable Bits
\r
1721 * | | |0 = EPWM Channel capture input path Disabled
\r
1722 * | | |The input of EPWM channel capture function is always regarded as 0.
\r
1723 * | | |1 = EPWM Channel capture input path Enabled
\r
1724 * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
\r
1725 * |[3] |CAPINEN3 |Capture Input Enable Bits
\r
1726 * | | |0 = EPWM Channel capture input path Disabled
\r
1727 * | | |The input of EPWM channel capture function is always regarded as 0.
\r
1728 * | | |1 = EPWM Channel capture input path Enabled
\r
1729 * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
\r
1730 * |[4] |CAPINEN4 |Capture Input Enable Bits
\r
1731 * | | |0 = EPWM Channel capture input path Disabled
\r
1732 * | | |The input of EPWM channel capture function is always regarded as 0.
\r
1733 * | | |1 = EPWM Channel capture input path Enabled
\r
1734 * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
\r
1735 * |[5] |CAPINEN5 |Capture Input Enable Bits
\r
1736 * | | |0 = EPWM Channel capture input path Disabled
\r
1737 * | | |The input of EPWM channel capture function is always regarded as 0.
\r
1738 * | | |1 = EPWM Channel capture input path Enabled
\r
1739 * | | |The input of EPWM channel capture function comes from correlative multifunction pin.
\r
1740 * @var EPWM_T::CAPCTL
\r
1741 * Offset: 0x204 EPWM Capture Control Register
\r
1742 * ---------------------------------------------------------------------------------------------------
\r
1743 * |Bits |Field |Descriptions
\r
1744 * | :----: | :----: | :---- |
\r
1745 * |[0] |CAPEN0 |Capture Function Enable Bits
\r
1746 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
\r
1747 * | | |1 = Capture function Enabled
\r
1748 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
\r
1749 * |[1] |CAPEN1 |Capture Function Enable Bits
\r
1750 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
\r
1751 * | | |1 = Capture function Enabled
\r
1752 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
\r
1753 * |[2] |CAPEN2 |Capture Function Enable Bits
\r
1754 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
\r
1755 * | | |1 = Capture function Enabled
\r
1756 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
\r
1757 * |[3] |CAPEN3 |Capture Function Enable Bits
\r
1758 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
\r
1759 * | | |1 = Capture function Enabled
\r
1760 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
\r
1761 * |[4] |CAPEN4 |Capture Function Enable Bits
\r
1762 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
\r
1763 * | | |1 = Capture function Enabled
\r
1764 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
\r
1765 * |[5] |CAPEN5 |Capture Function Enable Bits
\r
1766 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
\r
1767 * | | |1 = Capture function Enabled
\r
1768 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
\r
1769 * |[8] |CAPINV0 |Capture Inverter Enable Bits
\r
1770 * | | |0 = Capture source inverter Disabled.
\r
1771 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
\r
1772 * |[9] |CAPINV1 |Capture Inverter Enable Bits
\r
1773 * | | |0 = Capture source inverter Disabled.
\r
1774 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
\r
1775 * |[10] |CAPINV2 |Capture Inverter Enable Bits
\r
1776 * | | |0 = Capture source inverter Disabled.
\r
1777 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
\r
1778 * |[11] |CAPINV3 |Capture Inverter Enable Bits
\r
1779 * | | |0 = Capture source inverter Disabled.
\r
1780 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
\r
1781 * |[12] |CAPINV4 |Capture Inverter Enable Bits
\r
1782 * | | |0 = Capture source inverter Disabled.
\r
1783 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
\r
1784 * |[13] |CAPINV5 |Capture Inverter Enable Bits
\r
1785 * | | |0 = Capture source inverter Disabled.
\r
1786 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
\r
1787 * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits
\r
1788 * | | |0 = Rising capture reload counter Disabled.
\r
1789 * | | |1 = Rising capture reload counter Enabled.
\r
1790 * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits
\r
1791 * | | |0 = Rising capture reload counter Disabled.
\r
1792 * | | |1 = Rising capture reload counter Enabled.
\r
1793 * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits
\r
1794 * | | |0 = Rising capture reload counter Disabled.
\r
1795 * | | |1 = Rising capture reload counter Enabled.
\r
1796 * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits
\r
1797 * | | |0 = Rising capture reload counter Disabled.
\r
1798 * | | |1 = Rising capture reload counter Enabled.
\r
1799 * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits
\r
1800 * | | |0 = Rising capture reload counter Disabled.
\r
1801 * | | |1 = Rising capture reload counter Enabled.
\r
1802 * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits
\r
1803 * | | |0 = Rising capture reload counter Disabled.
\r
1804 * | | |1 = Rising capture reload counter Enabled.
\r
1805 * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits
\r
1806 * | | |0 = Falling capture reload counter Disabled.
\r
1807 * | | |1 = Falling capture reload counter Enabled.
\r
1808 * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits
\r
1809 * | | |0 = Falling capture reload counter Disabled.
\r
1810 * | | |1 = Falling capture reload counter Enabled.
\r
1811 * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits
\r
1812 * | | |0 = Falling capture reload counter Disabled.
\r
1813 * | | |1 = Falling capture reload counter Enabled.
\r
1814 * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits
\r
1815 * | | |0 = Falling capture reload counter Disabled.
\r
1816 * | | |1 = Falling capture reload counter Enabled.
\r
1817 * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits
\r
1818 * | | |0 = Falling capture reload counter Disabled.
\r
1819 * | | |1 = Falling capture reload counter Enabled.
\r
1820 * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits
\r
1821 * | | |0 = Falling capture reload counter Disabled.
\r
1822 * | | |1 = Falling capture reload counter Enabled.
\r
1823 * @var EPWM_T::CAPSTS
\r
1824 * Offset: 0x208 EPWM Capture Status Register
\r
1825 * ---------------------------------------------------------------------------------------------------
\r
1826 * |Bits |Field |Descriptions
\r
1827 * | :----: | :----: | :---- |
\r
1828 * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
\r
1829 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
\r
1830 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
\r
1831 * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
\r
1832 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
\r
1833 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
\r
1834 * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
\r
1835 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
\r
1836 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
\r
1837 * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
\r
1838 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
\r
1839 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
\r
1840 * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
\r
1841 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
\r
1842 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
\r
1843 * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
\r
1844 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
\r
1845 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
\r
1846 * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
\r
1847 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
\r
1848 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
\r
1849 * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
\r
1850 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
\r
1851 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
\r
1852 * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
\r
1853 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
\r
1854 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
\r
1855 * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
\r
1856 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
\r
1857 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
\r
1858 * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
\r
1859 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
\r
1860 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
\r
1861 * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
\r
1862 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
\r
1863 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
\r
1864 * @var EPWM_T::PDMACTL
\r
1865 * Offset: 0x23C EPWM PDMA Control Register
\r
1866 * ---------------------------------------------------------------------------------------------------
\r
1867 * |Bits |Field |Descriptions
\r
1868 * | :----: | :----: | :---- |
\r
1869 * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable
\r
1870 * | | |0 = Channel 0/1 PDMA function Disabled.
\r
1871 * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
\r
1872 * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer
\r
1873 * | | |00 = Reserved.
\r
1874 * | | |01 = EPWM_RCAPDAT0/1 register.
\r
1875 * | | |10 = EPWM_FCAPDAT0/1 register.
\r
1876 * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 registers.
\r
1877 * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
\r
1878 * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to = 0x3.
\r
1879 * | | |0 = EPWM_FCAPDAT0/1 register is the first captured data to memory.
\r
1880 * | | |1 = EPWM_RCAPDAT0/1 register is the first captured data to memory.
\r
1881 * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer
\r
1882 * | | |0 = Channel0.
\r
1883 * | | |1 = Channel1.
\r
1884 * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable
\r
1885 * | | |0 = Channel 2/3 PDMA function Disabled.
\r
1886 * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
\r
1887 * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer
\r
1888 * | | |00 = Reserved.
\r
1889 * | | |01 = EPWM_RCAPDAT2/3 register.
\r
1890 * | | |10 = EPWM_FCAPDAT2/3 register.
\r
1891 * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 registers.
\r
1892 * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
\r
1893 * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to =0x3.
\r
1894 * | | |0 = EPWM_FCAPDAT2/3 register is the first captured data to memory.
\r
1895 * | | |1 = EPWM_RCAPDAT2/3 register is the first captured data to memory.
\r
1896 * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer
\r
1897 * | | |0 = Channel2.
\r
1898 * | | |1 = Channel3.
\r
1899 * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable
\r
1900 * | | |0 = Channel 4/5 PDMA function Disabled.
\r
1901 * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
\r
1902 * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer
\r
1903 * | | |00 = Reserved.
\r
1904 * | | |01 = EPWM_RCAPDAT4/5 register.
\r
1905 * | | |10 = EPWM_FCAPDAT4/5 register.
\r
1906 * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 registers.
\r
1907 * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
\r
1908 * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits =are set to 0x3.
\r
1909 * | | |0 = EPWM_FCAPDAT4/5 register is the first captured data to memory.
\r
1910 * | | |1 = EPWM_RCAPDAT4/5 register is the first captured data to memory.
\r
1911 * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer
\r
1912 * | | |0 = Channel4.
\r
1913 * | | |1 = Channel5.
\r
1914 * @var EPWM_T::PDMACAP[3]
\r
1915 * Offset: 0x240 EPWM Capture Channel 01 PDMA Register
\r
1916 * ---------------------------------------------------------------------------------------------------
\r
1917 * |Bits |Field |Descriptions
\r
1918 * | :----: | :----: | :---- |
\r
1919 * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only)
\r
1920 * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA.
\r
1921 * @var EPWM_T::CAPIEN
\r
1922 * Offset: 0x250 EPWM Capture Interrupt Enable Register
\r
1923 * ---------------------------------------------------------------------------------------------------
\r
1924 * |Bits |Field |Descriptions
\r
1925 * | :----: | :----: | :---- |
\r
1926 * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits
\r
1927 * | | |0 = Capture rising edge latch interrupt Disabled.
\r
1928 * | | |1 = Capture rising edge latch interrupt Enabled.
\r
1929 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN0 bit must be disabled.
\r
1930 * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits
\r
1931 * | | |0 = Capture rising edge latch interrupt Disabled.
\r
1932 * | | |1 = Capture rising edge latch interrupt Enabled.
\r
1933 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN1 bit must be disabled.
\r
1934 * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits
\r
1935 * | | |0 = Capture rising edge latch interrupt Disabled.
\r
1936 * | | |1 = Capture rising edge latch interrupt Enabled.
\r
1937 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN2 bit must be disabled.
\r
1938 * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits
\r
1939 * | | |0 = Capture rising edge latch interrupt Disabled.
\r
1940 * | | |1 = Capture rising edge latch interrupt Enabled.
\r
1941 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN3 bit must be disabled.
\r
1942 * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits
\r
1943 * | | |0 = Capture rising edge latch interrupt Disabled.
\r
1944 * | | |1 = Capture rising edge latch interrupt Enabled.
\r
1945 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN4 bit must be disabled.
\r
1946 * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits
\r
1947 * | | |0 = Capture rising edge latch interrupt Disabled.
\r
1948 * | | |1 = Capture rising edge latch interrupt Enabled.
\r
1949 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN5 bit must be disabled.
\r
1950 * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits
\r
1951 * | | |0 = Capture falling edge latch interrupt Disabled.
\r
1952 * | | |1 = Capture falling edge latch interrupt Enabled.
\r
1953 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN0 bit must be disabled.
\r
1954 * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits
\r
1955 * | | |0 = Capture falling edge latch interrupt Disabled.
\r
1956 * | | |1 = Capture falling edge latch interrupt Enabled.
\r
1957 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN1 bit must be disabled.
\r
1958 * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits
\r
1959 * | | |0 = Capture falling edge latch interrupt Disabled.
\r
1960 * | | |1 = Capture falling edge latch interrupt Enabled.
\r
1961 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN2 bit must be disabled.
\r
1962 * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits
\r
1963 * | | |0 = Capture falling edge latch interrupt Disabled.
\r
1964 * | | |1 = Capture falling edge latch interrupt Enabled.
\r
1965 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN3 bit must be disabled.
\r
1966 * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits
\r
1967 * | | |0 = Capture falling edge latch interrupt Disabled.
\r
1968 * | | |1 = Capture falling edge latch interrupt Enabled.
\r
1969 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN4 bit must be disabled.
\r
1970 * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits
\r
1971 * | | |0 = Capture falling edge latch interrupt Disabled.
\r
1972 * | | |1 = Capture falling edge latch interrupt Enabled.
\r
1973 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN5 bit must be disabled.
\r
1974 * @var EPWM_T::CAPIF
\r
1975 * Offset: 0x254 EPWM Capture Interrupt Flag Register
\r
1976 * ---------------------------------------------------------------------------------------------------
\r
1977 * |Bits |Field |Descriptions
\r
1978 * | :----: | :----: | :---- |
\r
1979 * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag
\r
1980 * | | |This bit is writing 1 to clear.
\r
1981 * | | |0 = No capture rising latch condition happened.
\r
1982 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
\r
1983 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF0 bit will cleared by hardware after PDMA transfer data.
\r
1984 * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag
\r
1985 * | | |This bit is writing 1 to clear.
\r
1986 * | | |0 = No capture rising latch condition happened.
\r
1987 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
\r
1988 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF1 bit will cleared by hardware after PDMA transfer data.
\r
1989 * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag
\r
1990 * | | |This bit is writing 1 to clear.
\r
1991 * | | |0 = No capture rising latch condition happened.
\r
1992 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
\r
1993 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF2 bit will cleared by hardware after PDMA transfer data.
\r
1994 * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag
\r
1995 * | | |This bit is writing 1 to clear.
\r
1996 * | | |0 = No capture rising latch condition happened.
\r
1997 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
\r
1998 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF3 bit will cleared by hardware after PDMA transfer data.
\r
1999 * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag
\r
2000 * | | |This bit is writing 1 to clear.
\r
2001 * | | |0 = No capture rising latch condition happened.
\r
2002 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
\r
2003 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF4 bit will cleared by hardware after PDMA transfer data.
\r
2004 * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag
\r
2005 * | | |This bit is writing 1 to clear.
\r
2006 * | | |0 = No capture rising latch condition happened.
\r
2007 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
\r
2008 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF5 bit will cleared by hardware after PDMA transfer data.
\r
2009 * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag
\r
2010 * | | |This bit is writing 1 to clear.
\r
2011 * | | |0 = No capture falling latch condition happened.
\r
2012 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
\r
2013 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF0 bit will cleared by hardware after PDMA transfer data.
\r
2014 * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag
\r
2015 * | | |This bit is writing 1 to clear.
\r
2016 * | | |0 = No capture falling latch condition happened.
\r
2017 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
\r
2018 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF1 bit will cleared by hardware after PDMA transfer data.
\r
2019 * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag
\r
2020 * | | |This bit is writing 1 to clear.
\r
2021 * | | |0 = No capture falling latch condition happened.
\r
2022 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
\r
2023 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF2 bit will cleared by hardware after PDMA transfer data.
\r
2024 * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag
\r
2025 * | | |This bit is writing 1 to clear.
\r
2026 * | | |0 = No capture falling latch condition happened.
\r
2027 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
\r
2028 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF3 bit will cleared by hardware after PDMA transfer data.
\r
2029 * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag
\r
2030 * | | |This bit is writing 1 to clear.
\r
2031 * | | |0 = No capture falling latch condition happened.
\r
2032 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
\r
2033 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF4 bit will cleared by hardware after PDMA transfer data.
\r
2034 * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag
\r
2035 * | | |This bit is writing 1 to clear.
\r
2036 * | | |0 = No capture falling latch condition happened.
\r
2037 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
\r
2038 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
\r
2039 * @var EPWM_T::PBUF[6]
\r
2040 * Offset: 0x304 EPWM PERIOD0~5 Buffer
\r
2041 * ---------------------------------------------------------------------------------------------------
\r
2042 * |Bits |Field |Descriptions
\r
2043 * | :----: | :----: | :---- |
\r
2044 * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only)
\r
2045 * | | |Used as PERIOD active register.
\r
2046 * @var EPWM_T::CMPBUF[6]
\r
2047 * Offset: 0x31C EPWM CMPDAT0~5 Buffer
\r
2048 * ---------------------------------------------------------------------------------------------------
\r
2049 * |Bits |Field |Descriptions
\r
2050 * | :----: | :----: | :---- |
\r
2051 * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only)
\r
2052 * | | |Used as CMP active register.
\r
2053 * @var EPWM_T::CPSCBUF[3]
\r
2054 * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer
\r
2055 * ---------------------------------------------------------------------------------------------------
\r
2056 * |Bits |Field |Descriptions
\r
2057 * | :----: | :----: | :---- |
\r
2058 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer
\r
2059 * | | |Use as EPWM counter clock prescale active register.
\r
2060 * @var EPWM_T::FTCBUF[3]
\r
2061 * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer
\r
2062 * ---------------------------------------------------------------------------------------------------
\r
2063 * |Bits |Field |Descriptions
\r
2064 * | :----: | :----: | :---- |
\r
2065 * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only)
\r
2066 * | | |Used as FTCMPDAT active register.
\r
2067 * @var EPWM_T::FTCI
\r
2068 * Offset: 0x34C EPWM FTCMPDAT Indicator Register
\r
2069 * ---------------------------------------------------------------------------------------------------
\r
2070 * |Bits |Field |Descriptions
\r
2071 * | :----: | :----: | :---- |
\r
2072 * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator
\r
2073 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
\r
2074 * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator
\r
2075 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
\r
2076 * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator
\r
2077 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
\r
2078 * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator
\r
2079 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
\r
2080 * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator
\r
2081 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
\r
2082 * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator
\r
2083 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
\r
2085 __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */
\r
2086 __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */
\r
2087 __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */
\r
2088 __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */
\r
2089 __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */
\r
2090 __IO uint32_t CLKPSC[3]; /*!< [0x0014~0x001c] EPWM Clock Prescale Register 0_1,2_3,4_5 */
\r
2091 __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */
\r
2092 __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */
\r
2093 __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */
\r
2094 __I uint32_t RESERVE0[1];
\r
2095 __IO uint32_t PERIOD[6]; /*!< [0x0030~0x0044] EPWM Period Register 0~5 */
\r
2096 __I uint32_t RESERVE1[2];
\r
2097 __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] EPWM Comparator Register 0~5 */
\r
2098 __I uint32_t RESERVE2[2];
\r
2099 __IO uint32_t DTCTL[3]; /*!< [0x0070~0x0078] EPWM Dead-Time Control Register 0_1,2_3,4_5 */
\r
2100 __I uint32_t RESERVE3[1];
\r
2101 __IO uint32_t PHS[3]; /*!< [0x0080~0x0088] EPWM Counter Phase Register 0_1,2_3,4_5 */
\r
2102 __I uint32_t RESERVE4[1];
\r
2103 __I uint32_t CNT[6]; /*!< [0x0090~0x00A4 EPWM Counter Register 0~5 */
\r
2104 __I uint32_t RESERVE5[2];
\r
2105 __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */
\r
2106 __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */
\r
2107 __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */
\r
2108 __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */
\r
2109 __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */
\r
2110 __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */
\r
2111 __IO uint32_t BRKCTL[3]; /*!< [0x00c8~0x00d0] EPWM Brake Edge Detect Control Register 0_1,2_3,4_5 */
\r
2112 __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */
\r
2113 __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */
\r
2114 __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */
\r
2115 __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */
\r
2116 __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */
\r
2117 __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */
\r
2118 __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */
\r
2119 __I uint32_t RESERVE6[1];
\r
2120 __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */
\r
2121 __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */
\r
2122 __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */
\r
2123 __IO uint32_t FTCMPDAT[3]; /*!< [0x0100~0x108] EPWM Free Trigger Compare Register 0_1,2_3,4_5 */
\r
2124 __I uint32_t RESERVE7[1];
\r
2125 __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */
\r
2126 __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */
\r
2127 __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */
\r
2128 __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */
\r
2129 __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */
\r
2130 __I uint32_t RESERVE8[3];
\r
2131 __IO uint32_t IFA[6]; /*!< [0x0130~0x144] EPWM Interrupt Flag Accumulator Register 0~5 */
\r
2132 __I uint32_t RESERVE9[2];
\r
2133 __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */
\r
2134 __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */
\r
2135 __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */
\r
2136 __I uint32_t RESERVE10[41];
\r
2137 __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */
\r
2138 __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */
\r
2139 __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */
\r
2140 ECAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] EPWM Rising and Falling Capture Data Register 0~5 */
\r
2141 __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */
\r
2142 __I uint32_t PDMACAP[3]; /*!< [0x0240~0x248] EPWM Capture Channel 0_1,2_3,4_5 PDMA Register */
\r
2143 __I uint32_t RESERVE11[1];
\r
2144 __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */
\r
2145 __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */
\r
2146 __I uint32_t RESERVE12[43];
\r
2147 __I uint32_t PBUF[6]; /*!< [0x0304~0x0318 EPWM PERIOD0~5 Buffer */
\r
2148 __I uint32_t CMPBUF[6]; /*!< [0x031C~0x0330 EPWM CMPDAT0~5 Buffer */
\r
2149 __I uint32_t CPSCBUF[3]; /*!< [0x0334~0x33c] EPWM CLKPSC0_1,2_3,4_5 Buffer */
\r
2150 __I uint32_t FTCBUF[3]; /*!< [0x0340~0x348] EPWM FTCMPDAT0_1,2_3,4_5 Buffer */
\r
2151 __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */
\r
2156 @addtogroup EPWM_CONST EPWM Bit Field Definition
\r
2157 Constant Definitions for EPWM Controller
\r
2160 #define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */
\r
2161 #define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */
\r
2163 #define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */
\r
2164 #define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */
\r
2166 #define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */
\r
2167 #define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */
\r
2169 #define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */
\r
2170 #define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */
\r
2172 #define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */
\r
2173 #define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */
\r
2175 #define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */
\r
2176 #define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */
\r
2178 #define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */
\r
2179 #define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */
\r
2181 #define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */
\r
2182 #define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */
\r
2184 #define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */
\r
2185 #define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */
\r
2187 #define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */
\r
2188 #define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */
\r
2190 #define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */
\r
2191 #define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */
\r
2193 #define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */
\r
2194 #define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */
\r
2196 #define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */
\r
2197 #define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */
\r
2199 #define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */
\r
2200 #define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */
\r
2202 #define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */
\r
2203 #define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */
\r
2205 #define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */
\r
2206 #define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */
\r
2208 #define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */
\r
2209 #define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */
\r
2211 #define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */
\r
2212 #define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */
\r
2214 #define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */
\r
2215 #define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */
\r
2217 #define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */
\r
2218 #define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */
\r
2220 #define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */
\r
2221 #define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */
\r
2223 #define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */
\r
2224 #define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */
\r
2226 #define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */
\r
2227 #define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */
\r
2229 #define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */
\r
2230 #define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */
\r
2232 #define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */
\r
2233 #define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */
\r
2235 #define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */
\r
2236 #define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */
\r
2238 #define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */
\r
2239 #define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */
\r
2241 #define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */
\r
2242 #define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */
\r
2244 #define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */
\r
2245 #define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */
\r
2247 #define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */
\r
2248 #define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */
\r
2250 #define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */
\r
2251 #define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */
\r
2253 #define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */
\r
2254 #define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */
\r
2256 #define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */
\r
2257 #define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */
\r
2259 #define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */
\r
2260 #define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */
\r
2262 #define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */
\r
2263 #define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */
\r
2265 #define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */
\r
2266 #define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */
\r
2268 #define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */
\r
2269 #define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */
\r
2271 #define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */
\r
2272 #define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */
\r
2274 #define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */
\r
2275 #define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */
\r
2277 #define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */
\r
2278 #define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */
\r
2280 #define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */
\r
2281 #define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */
\r
2283 #define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */
\r
2284 #define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */
\r
2286 #define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */
\r
2287 #define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */
\r
2289 #define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */
\r
2290 #define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */
\r
2292 #define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */
\r
2293 #define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */
\r
2295 #define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */
\r
2296 #define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */
\r
2298 #define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */
\r
2299 #define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */
\r
2301 #define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */
\r
2302 #define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */
\r
2304 #define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */
\r
2305 #define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */
\r
2307 #define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */
\r
2308 #define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */
\r
2310 #define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */
\r
2311 #define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */
\r
2313 #define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */
\r
2314 #define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */
\r
2316 #define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */
\r
2317 #define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */
\r
2319 #define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */
\r
2320 #define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */
\r
2322 #define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */
\r
2323 #define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */
\r
2325 #define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */
\r
2326 #define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */
\r
2328 #define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */
\r
2329 #define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */
\r
2331 #define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */
\r
2332 #define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */
\r
2334 #define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */
\r
2335 #define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */
\r
2337 #define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */
\r
2338 #define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */
\r
2340 #define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */
\r
2341 #define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */
\r
2343 #define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */
\r
2344 #define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */
\r
2346 #define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */
\r
2347 #define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */
\r
2349 #define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */
\r
2350 #define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */
\r
2352 #define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */
\r
2353 #define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */
\r
2355 #define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */
\r
2356 #define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */
\r
2358 #define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */
\r
2359 #define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */
\r
2361 #define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */
\r
2362 #define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */
\r
2364 #define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */
\r
2365 #define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */
\r
2367 #define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */
\r
2368 #define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */
\r
2370 #define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */
\r
2371 #define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */
\r
2373 #define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */
\r
2374 #define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */
\r
2376 #define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */
\r
2377 #define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */
\r
2379 #define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */
\r
2380 #define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */
\r
2382 #define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */
\r
2383 #define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */
\r
2385 #define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */
\r
2386 #define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */
\r
2388 #define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */
\r
2389 #define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */
\r
2391 #define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */
\r
2392 #define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */
\r
2394 #define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */
\r
2395 #define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */
\r
2397 #define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */
\r
2398 #define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */
\r
2400 #define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */
\r
2401 #define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */
\r
2403 #define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */
\r
2404 #define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */
\r
2406 #define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */
\r
2407 #define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */
\r
2409 #define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */
\r
2410 #define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */
\r
2412 #define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */
\r
2413 #define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */
\r
2415 #define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */
\r
2416 #define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */
\r
2418 #define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */
\r
2419 #define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */
\r
2421 #define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */
\r
2422 #define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */
\r
2424 #define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */
\r
2425 #define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */
\r
2427 #define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */
\r
2428 #define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */
\r
2430 #define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */
\r
2431 #define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */
\r
2433 #define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */
\r
2434 #define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */
\r
2436 #define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */
\r
2437 #define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */
\r
2439 #define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */
\r
2440 #define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */
\r
2442 #define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */
\r
2443 #define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */
\r
2445 #define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */
\r
2446 #define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */
\r
2448 #define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */
\r
2449 #define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */
\r
2451 #define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */
\r
2452 #define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */
\r
2454 #define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */
\r
2455 #define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */
\r
2457 #define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */
\r
2458 #define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */
\r
2460 #define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */
\r
2461 #define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */
\r
2463 #define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */
\r
2464 #define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */
\r
2466 #define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */
\r
2467 #define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */
\r
2469 #define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */
\r
2470 #define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */
\r
2472 #define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */
\r
2473 #define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */
\r
2475 #define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */
\r
2476 #define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */
\r
2478 #define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */
\r
2479 #define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */
\r
2481 #define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */
\r
2482 #define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */
\r
2484 #define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */
\r
2485 #define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */
\r
2487 #define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */
\r
2488 #define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */
\r
2490 #define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */
\r
2491 #define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */
\r
2493 #define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */
\r
2494 #define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */
\r
2496 #define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */
\r
2497 #define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */
\r
2499 #define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */
\r
2500 #define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */
\r
2502 #define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */
\r
2503 #define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */
\r
2505 #define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */
\r
2506 #define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */
\r
2508 #define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */
\r
2509 #define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */
\r
2511 #define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */
\r
2512 #define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */
\r
2514 #define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */
\r
2515 #define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */
\r
2517 #define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */
\r
2518 #define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */
\r
2520 #define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */
\r
2521 #define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */
\r
2523 #define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */
\r
2524 #define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */
\r
2526 #define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */
\r
2527 #define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */
\r
2529 #define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */
\r
2530 #define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */
\r
2532 #define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */
\r
2533 #define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */
\r
2535 #define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */
\r
2536 #define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */
\r
2538 #define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */
\r
2539 #define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */
\r
2541 #define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */
\r
2542 #define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */
\r
2544 #define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */
\r
2545 #define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */
\r
2547 #define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */
\r
2548 #define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */
\r
2550 #define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */
\r
2551 #define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */
\r
2553 #define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */
\r
2554 #define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */
\r
2556 #define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */
\r
2557 #define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */
\r
2559 #define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */
\r
2560 #define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */
\r
2562 #define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */
\r
2563 #define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */
\r
2565 #define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */
\r
2566 #define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */
\r
2568 #define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */
\r
2569 #define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */
\r
2571 #define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */
\r
2572 #define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */
\r
2574 #define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */
\r
2575 #define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */
\r
2577 #define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */
\r
2578 #define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */
\r
2580 #define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */
\r
2581 #define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */
\r
2583 #define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */
\r
2584 #define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */
\r
2586 #define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */
\r
2587 #define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */
\r
2589 #define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */
\r
2590 #define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */
\r
2592 #define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */
\r
2593 #define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */
\r
2595 #define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */
\r
2596 #define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */
\r
2598 #define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */
\r
2599 #define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */
\r
2601 #define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */
\r
2602 #define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */
\r
2604 #define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */
\r
2605 #define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */
\r
2607 #define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */
\r
2608 #define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */
\r
2610 #define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */
\r
2611 #define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */
\r
2613 #define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */
\r
2614 #define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */
\r
2616 #define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */
\r
2617 #define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */
\r
2619 #define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */
\r
2620 #define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */
\r
2622 #define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */
\r
2623 #define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */
\r
2625 #define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */
\r
2626 #define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */
\r
2628 #define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */
\r
2629 #define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */
\r
2631 #define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */
\r
2632 #define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */
\r
2634 #define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */
\r
2635 #define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */
\r
2637 #define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */
\r
2638 #define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */
\r
2640 #define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */
\r
2641 #define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */
\r
2643 #define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */
\r
2644 #define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */
\r
2646 #define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */
\r
2647 #define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */
\r
2649 #define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */
\r
2650 #define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */
\r
2652 #define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */
\r
2653 #define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */
\r
2655 #define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */
\r
2656 #define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */
\r
2658 #define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */
\r
2659 #define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */
\r
2661 #define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */
\r
2662 #define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */
\r
2664 #define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */
\r
2665 #define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */
\r
2667 #define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */
\r
2668 #define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */
\r
2670 #define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */
\r
2671 #define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */
\r
2673 #define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */
\r
2674 #define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */
\r
2676 #define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */
\r
2677 #define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */
\r
2679 #define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */
\r
2680 #define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */
\r
2682 #define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */
\r
2683 #define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */
\r
2685 #define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */
\r
2686 #define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */
\r
2688 #define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */
\r
2689 #define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */
\r
2691 #define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */
\r
2692 #define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */
\r
2694 #define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */
\r
2695 #define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */
\r
2697 #define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */
\r
2698 #define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */
\r
2700 #define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */
\r
2701 #define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */
\r
2703 #define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */
\r
2704 #define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */
\r
2706 #define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */
\r
2707 #define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */
\r
2709 #define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */
\r
2710 #define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */
\r
2712 #define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */
\r
2713 #define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */
\r
2715 #define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */
\r
2716 #define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */
\r
2718 #define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */
\r
2719 #define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */
\r
2721 #define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */
\r
2722 #define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */
\r
2724 #define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */
\r
2725 #define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */
\r
2727 #define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */
\r
2728 #define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */
\r
2730 #define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */
\r
2731 #define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */
\r
2733 #define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */
\r
2734 #define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */
\r
2736 #define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */
\r
2737 #define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */
\r
2739 #define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */
\r
2740 #define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */
\r
2742 #define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */
\r
2743 #define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */
\r
2745 #define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */
\r
2746 #define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */
\r
2748 #define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */
\r
2749 #define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */
\r
2751 #define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */
\r
2752 #define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */
\r
2754 #define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */
\r
2755 #define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */
\r
2757 #define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */
\r
2758 #define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */
\r
2760 #define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */
\r
2761 #define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */
\r
2763 #define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */
\r
2764 #define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */
\r
2766 #define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */
\r
2767 #define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */
\r
2769 #define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */
\r
2770 #define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */
\r
2772 #define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */
\r
2773 #define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */
\r
2775 #define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */
\r
2776 #define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */
\r
2778 #define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */
\r
2779 #define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */
\r
2781 #define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */
\r
2782 #define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */
\r
2784 #define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */
\r
2785 #define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */
\r
2787 #define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */
\r
2788 #define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */
\r
2790 #define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */
\r
2791 #define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */
\r
2793 #define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */
\r
2794 #define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */
\r
2796 #define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */
\r
2797 #define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */
\r
2799 #define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */
\r
2800 #define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */
\r
2802 #define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */
\r
2803 #define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */
\r
2805 #define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */
\r
2806 #define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */
\r
2808 #define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */
\r
2809 #define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */
\r
2811 #define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */
\r
2812 #define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */
\r
2814 #define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */
\r
2815 #define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */
\r
2817 #define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */
\r
2818 #define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */
\r
2820 #define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */
\r
2821 #define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */
\r
2823 #define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */
\r
2824 #define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */
\r
2826 #define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */
\r
2827 #define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */
\r
2829 #define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */
\r
2830 #define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */
\r
2832 #define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */
\r
2833 #define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */
\r
2835 #define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */
\r
2836 #define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */
\r
2838 #define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */
\r
2839 #define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */
\r
2841 #define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */
\r
2842 #define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */
\r
2844 #define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */
\r
2845 #define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */
\r
2847 #define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */
\r
2848 #define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */
\r
2850 #define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */
\r
2851 #define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */
\r
2853 #define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */
\r
2854 #define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */
\r
2856 #define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */
\r
2857 #define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */
\r
2859 #define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */
\r
2860 #define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */
\r
2862 #define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */
\r
2863 #define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */
\r
2865 #define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */
\r
2866 #define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */
\r
2868 #define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */
\r
2869 #define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */
\r
2871 #define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */
\r
2872 #define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */
\r
2874 #define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */
\r
2875 #define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */
\r
2877 #define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */
\r
2878 #define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */
\r
2880 #define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */
\r
2881 #define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */
\r
2883 #define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */
\r
2884 #define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */
\r
2886 #define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */
\r
2887 #define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */
\r
2889 #define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */
\r
2890 #define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */
\r
2892 #define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */
\r
2893 #define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */
\r
2895 #define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */
\r
2896 #define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */
\r
2898 #define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */
\r
2899 #define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */
\r
2901 #define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */
\r
2902 #define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */
\r
2904 #define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */
\r
2905 #define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */
\r
2907 #define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */
\r
2908 #define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */
\r
2910 #define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */
\r
2911 #define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */
\r
2913 #define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */
\r
2914 #define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */
\r
2916 #define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */
\r
2917 #define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */
\r
2919 #define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */
\r
2920 #define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */
\r
2922 #define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */
\r
2923 #define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */
\r
2925 #define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */
\r
2926 #define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */
\r
2928 #define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */
\r
2929 #define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */
\r
2931 #define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */
\r
2932 #define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */
\r
2934 #define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */
\r
2935 #define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */
\r
2937 #define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */
\r
2938 #define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */
\r
2940 #define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */
\r
2941 #define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */
\r
2943 #define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */
\r
2944 #define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */
\r
2946 #define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */
\r
2947 #define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */
\r
2949 #define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */
\r
2950 #define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */
\r
2952 #define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */
\r
2953 #define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */
\r
2955 #define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */
\r
2956 #define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */
\r
2958 #define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */
\r
2959 #define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */
\r
2961 #define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */
\r
2962 #define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */
\r
2964 #define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */
\r
2965 #define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */
\r
2967 #define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */
\r
2968 #define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */
\r
2970 #define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */
\r
2971 #define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */
\r
2973 #define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */
\r
2974 #define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */
\r
2976 #define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */
\r
2977 #define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */
\r
2979 #define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */
\r
2980 #define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */
\r
2982 #define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */
\r
2983 #define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */
\r
2985 #define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */
\r
2986 #define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */
\r
2988 #define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */
\r
2989 #define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */
\r
2991 #define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */
\r
2992 #define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */
\r
2994 #define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */
\r
2995 #define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */
\r
2997 #define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */
\r
2998 #define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */
\r
3000 #define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */
\r
3001 #define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */
\r
3003 #define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */
\r
3004 #define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */
\r
3006 #define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */
\r
3007 #define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */
\r
3009 #define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */
\r
3010 #define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */
\r
3012 #define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */
\r
3013 #define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */
\r
3015 #define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */
\r
3016 #define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */
\r
3018 #define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */
\r
3019 #define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */
\r
3021 #define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */
\r
3022 #define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */
\r
3024 #define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */
\r
3025 #define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */
\r
3027 #define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */
\r
3028 #define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */
\r
3030 #define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */
\r
3031 #define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */
\r
3033 #define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */
\r
3034 #define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */
\r
3036 #define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */
\r
3037 #define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */
\r
3039 #define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */
\r
3040 #define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */
\r
3042 #define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */
\r
3043 #define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */
\r
3045 #define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */
\r
3046 #define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */
\r
3048 #define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */
\r
3049 #define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */
\r
3051 #define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */
\r
3052 #define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */
\r
3054 #define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */
\r
3055 #define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */
\r
3057 #define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */
\r
3058 #define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */
\r
3060 #define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */
\r
3061 #define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */
\r
3063 #define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */
\r
3064 #define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */
\r
3066 #define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */
\r
3067 #define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */
\r
3069 #define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */
\r
3070 #define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */
\r
3072 #define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */
\r
3073 #define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */
\r
3075 #define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */
\r
3076 #define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */
\r
3078 #define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */
\r
3079 #define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */
\r
3081 #define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */
\r
3082 #define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */
\r
3084 #define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */
\r
3085 #define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */
\r
3087 #define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */
\r
3088 #define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */
\r
3090 #define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */
\r
3091 #define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */
\r
3093 #define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */
\r
3094 #define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */
\r
3096 #define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */
\r
3097 #define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */
\r
3099 #define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */
\r
3100 #define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */
\r
3102 #define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */
\r
3103 #define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */
\r
3105 #define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */
\r
3106 #define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */
\r
3108 #define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */
\r
3109 #define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */
\r
3111 #define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */
\r
3112 #define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */
\r
3114 #define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */
\r
3115 #define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */
\r
3117 #define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */
\r
3118 #define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */
\r
3120 #define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */
\r
3121 #define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */
\r
3123 #define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */
\r
3124 #define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */
\r
3126 #define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */
\r
3127 #define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */
\r
3129 #define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */
\r
3130 #define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */
\r
3132 #define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */
\r
3133 #define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */
\r
3135 #define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */
\r
3136 #define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */
\r
3138 #define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */
\r
3139 #define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */
\r
3141 #define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */
\r
3142 #define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */
\r
3144 #define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */
\r
3145 #define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */
\r
3147 #define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */
\r
3148 #define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */
\r
3150 #define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */
\r
3151 #define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */
\r
3153 #define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */
\r
3154 #define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */
\r
3156 #define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */
\r
3157 #define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */
\r
3159 #define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */
\r
3160 #define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */
\r
3162 #define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */
\r
3163 #define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */
\r
3165 #define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */
\r
3166 #define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */
\r
3168 #define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */
\r
3169 #define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */
\r
3171 #define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */
\r
3172 #define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */
\r
3174 #define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */
\r
3175 #define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */
\r
3177 #define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */
\r
3178 #define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */
\r
3180 #define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */
\r
3181 #define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */
\r
3183 #define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */
\r
3184 #define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */
\r
3186 #define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */
\r
3187 #define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */
\r
3189 #define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */
\r
3190 #define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */
\r
3192 #define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */
\r
3193 #define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */
\r
3195 #define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */
\r
3196 #define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */
\r
3198 #define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */
\r
3199 #define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */
\r
3201 #define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */
\r
3202 #define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */
\r
3204 #define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */
\r
3205 #define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */
\r
3207 #define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */
\r
3208 #define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */
\r
3210 #define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */
\r
3211 #define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */
\r
3213 #define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */
\r
3214 #define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */
\r
3216 #define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */
\r
3217 #define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */
\r
3219 #define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */
\r
3220 #define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */
\r
3222 #define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */
\r
3223 #define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */
\r
3225 #define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */
\r
3226 #define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */
\r
3228 #define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */
\r
3229 #define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */
\r
3231 #define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */
\r
3232 #define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */
\r
3234 #define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */
\r
3235 #define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */
\r
3237 #define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */
\r
3238 #define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */
\r
3240 #define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */
\r
3241 #define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */
\r
3243 #define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */
\r
3244 #define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */
\r
3246 #define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */
\r
3247 #define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */
\r
3249 #define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */
\r
3250 #define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */
\r
3252 #define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */
\r
3253 #define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */
\r
3255 #define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */
\r
3256 #define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */
\r
3258 #define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */
\r
3259 #define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */
\r
3261 #define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */
\r
3262 #define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */
\r
3264 #define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */
\r
3265 #define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */
\r
3267 #define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */
\r
3268 #define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */
\r
3270 #define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */
\r
3271 #define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */
\r
3273 #define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */
\r
3274 #define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */
\r
3276 #define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */
\r
3277 #define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */
\r
3279 #define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */
\r
3280 #define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */
\r
3282 #define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */
\r
3283 #define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */
\r
3285 #define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */
\r
3286 #define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */
\r
3288 #define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */
\r
3289 #define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */
\r
3291 #define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */
\r
3292 #define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */
\r
3294 #define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */
\r
3295 #define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */
\r
3297 #define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */
\r
3298 #define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */
\r
3300 #define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */
\r
3301 #define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */
\r
3303 #define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */
\r
3304 #define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */
\r
3306 #define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */
\r
3307 #define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */
\r
3309 #define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */
\r
3310 #define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */
\r
3312 #define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */
\r
3313 #define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */
\r
3315 #define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */
\r
3316 #define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */
\r
3318 #define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */
\r
3319 #define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */
\r
3321 #define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */
\r
3322 #define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */
\r
3324 #define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */
\r
3325 #define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */
\r
3327 #define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */
\r
3328 #define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */
\r
3330 #define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */
\r
3331 #define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */
\r
3333 #define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */
\r
3334 #define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */
\r
3336 #define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */
\r
3337 #define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */
\r
3339 #define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */
\r
3340 #define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */
\r
3342 #define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */
\r
3343 #define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */
\r
3345 #define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */
\r
3346 #define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */
\r
3348 #define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */
\r
3349 #define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */
\r
3351 #define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */
\r
3352 #define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */
\r
3354 #define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */
\r
3355 #define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */
\r
3357 #define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */
\r
3358 #define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */
\r
3360 #define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */
\r
3361 #define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */
\r
3363 #define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */
\r
3364 #define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */
\r
3366 #define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */
\r
3367 #define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */
\r
3369 #define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */
\r
3370 #define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */
\r
3372 #define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */
\r
3373 #define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */
\r
3375 #define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */
\r
3376 #define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */
\r
3378 #define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */
\r
3379 #define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */
\r
3381 #define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */
\r
3382 #define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */
\r
3384 #define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */
\r
3385 #define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */
\r
3387 #define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */
\r
3388 #define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */
\r
3390 #define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */
\r
3391 #define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */
\r
3393 #define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */
\r
3394 #define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */
\r
3396 #define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */
\r
3397 #define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */
\r
3399 #define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */
\r
3400 #define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */
\r
3402 #define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */
\r
3403 #define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */
\r
3405 #define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */
\r
3406 #define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */
\r
3408 #define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */
\r
3409 #define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */
\r
3411 #define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */
\r
3412 #define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */
\r
3414 #define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */
\r
3415 #define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */
\r
3417 #define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */
\r
3418 #define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */
\r
3420 #define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */
\r
3421 #define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */
\r
3423 #define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */
\r
3424 #define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */
\r
3426 #define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */
\r
3427 #define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */
\r
3429 #define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */
\r
3430 #define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */
\r
3432 #define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */
\r
3433 #define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */
\r
3435 #define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */
\r
3436 #define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */
\r
3438 #define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */
\r
3439 #define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */
\r
3441 #define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */
\r
3442 #define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */
\r
3444 #define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */
\r
3445 #define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */
\r
3447 #define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */
\r
3448 #define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */
\r
3450 #define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */
\r
3451 #define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */
\r
3453 #define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */
\r
3454 #define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */
\r
3456 #define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */
\r
3457 #define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */
\r
3459 #define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */
\r
3460 #define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */
\r
3462 #define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */
\r
3463 #define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */
\r
3465 #define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */
\r
3466 #define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */
\r
3468 #define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */
\r
3469 #define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */
\r
3471 #define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */
\r
3472 #define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */
\r
3474 #define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */
\r
3475 #define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */
\r
3477 #define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */
\r
3478 #define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */
\r
3480 #define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */
\r
3481 #define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */
\r
3483 #define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */
\r
3484 #define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */
\r
3486 #define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */
\r
3487 #define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */
\r
3489 #define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */
\r
3490 #define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */
\r
3492 #define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */
\r
3493 #define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */
\r
3495 #define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */
\r
3496 #define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */
\r
3498 #define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */
\r
3499 #define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */
\r
3501 #define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */
\r
3502 #define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */
\r
3504 #define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */
\r
3505 #define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */
\r
3507 #define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */
\r
3508 #define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */
\r
3510 #define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */
\r
3511 #define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */
\r
3513 #define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */
\r
3514 #define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */
\r
3516 #define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */
\r
3517 #define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */
\r
3519 #define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */
\r
3520 #define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */
\r
3522 #define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */
\r
3523 #define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */
\r
3525 #define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */
\r
3526 #define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */
\r
3528 #define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */
\r
3529 #define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */
\r
3531 #define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */
\r
3532 #define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */
\r
3534 #define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */
\r
3535 #define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */
\r
3537 #define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */
\r
3538 #define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */
\r
3540 #define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */
\r
3541 #define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */
\r
3543 #define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */
\r
3544 #define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */
\r
3546 #define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */
\r
3547 #define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */
\r
3549 #define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */
\r
3550 #define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */
\r
3552 #define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */
\r
3553 #define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */
\r
3555 #define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */
\r
3556 #define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */
\r
3558 #define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */
\r
3559 #define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */
\r
3561 #define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */
\r
3562 #define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */
\r
3564 #define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */
\r
3565 #define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */
\r
3567 #define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */
\r
3568 #define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */
\r
3570 #define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */
\r
3571 #define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */
\r
3573 #define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */
\r
3574 #define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */
\r
3576 #define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */
\r
3577 #define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */
\r
3579 #define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */
\r
3580 #define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */
\r
3582 #define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */
\r
3583 #define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */
\r
3585 #define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */
\r
3586 #define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */
\r
3588 #define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */
\r
3589 #define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */
\r
3591 #define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */
\r
3592 #define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */
\r
3594 #define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */
\r
3595 #define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */
\r
3597 #define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */
\r
3598 #define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */
\r
3600 #define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */
\r
3601 #define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */
\r
3603 #define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */
\r
3604 #define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */
\r
3606 #define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */
\r
3607 #define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */
\r
3609 #define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */
\r
3610 #define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */
\r
3612 #define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */
\r
3613 #define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */
\r
3615 #define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */
\r
3616 #define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */
\r
3618 #define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */
\r
3619 #define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */
\r
3621 #define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */
\r
3622 #define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */
\r
3624 #define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */
\r
3625 #define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */
\r
3627 #define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */
\r
3628 #define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */
\r
3630 #define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */
\r
3631 #define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */
\r
3633 #define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */
\r
3634 #define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */
\r
3636 #define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */
\r
3637 #define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */
\r
3639 #define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */
\r
3640 #define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */
\r
3642 #define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */
\r
3643 #define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */
\r
3645 #define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */
\r
3646 #define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */
\r
3648 #define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */
\r
3649 #define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */
\r
3651 #define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */
\r
3652 #define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */
\r
3654 #define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */
\r
3655 #define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */
\r
3657 #define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */
\r
3658 #define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */
\r
3660 #define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */
\r
3661 #define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */
\r
3663 #define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */
\r
3664 #define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */
\r
3666 #define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */
\r
3667 #define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */
\r
3669 #define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */
\r
3670 #define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */
\r
3672 #define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */
\r
3673 #define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */
\r
3675 #define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */
\r
3676 #define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */
\r
3678 #define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */
\r
3679 #define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */
\r
3681 #define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */
\r
3682 #define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */
\r
3684 #define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */
\r
3685 #define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */
\r
3687 #define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */
\r
3688 #define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */
\r
3690 #define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */
\r
3691 #define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */
\r
3693 #define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */
\r
3694 #define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */
\r
3696 #define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */
\r
3697 #define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */
\r
3699 #define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */
\r
3700 #define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */
\r
3702 #define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */
\r
3703 #define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */
\r
3705 #define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */
\r
3706 #define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */
\r
3708 #define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */
\r
3709 #define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */
\r
3711 #define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */
\r
3712 #define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */
\r
3714 #define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */
\r
3715 #define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */
\r
3717 #define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */
\r
3718 #define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */
\r
3720 #define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */
\r
3721 #define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */
\r
3723 #define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */
\r
3724 #define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */
\r
3726 /**@}*/ /* EPWM_CONST */
\r
3727 /**@}*/ /* end of EPWM register group */
\r
3728 /**@}*/ /* end of REGISTER group */
\r
3732 #endif /* __EPWM_REG_H__ */
\r
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