1 /**************************************************************************//**
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4 * @brief FMC register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __FMC_REG_H__
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9 #define __FMC_REG_H__
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11 /** @addtogroup REGISTER Control Register
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18 /*---------------------- Flash Memory Controller -------------------------*/
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20 @addtogroup FMC Flash Memory Controller(FMC)
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21 Memory Mapped Structure for FMC Controller
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29 * @var FMC_T::ISPCTL
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30 * Offset: 0x00 ISP Control Register
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31 * ---------------------------------------------------------------------------------------------------
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32 * |Bits |Field |Descriptions
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33 * | :----: | :----: | :---- |
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34 * |[0] |ISPEN |ISP Enable Bit (Write Protect)
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35 * | | |ISP function enable bit. Set this bit to enable ISP function.
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36 * | | |0 = ISP function Disabled.
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37 * | | |1 = ISP function Enabled.
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38 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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39 * |[1] |BS |Boot Select (Write Protect)
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40 * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively
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41 * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from
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42 * | | |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
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43 * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
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44 * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
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45 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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46 * |[3] |APUEN |APROM Update Enable Bit (Write Protect)
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47 * | | |0 = APROM cannot be updated when the chip runs in APROM.
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48 * | | |1 = APROM can be updated when the chip runs in APROM.
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49 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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50 * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
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51 * | | |0 = CONFIG cannot be updated.
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52 * | | |1 = CONFIG can be updated.
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53 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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54 * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
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55 * | | |LDROM update enable bit.
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56 * | | |0 = LDROM cannot be updated.
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57 * | | |1 = LDROM can be updated.
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58 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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59 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
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60 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
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61 * | | |This bit needs to be cleared by writing 1 to it.
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62 * | | |(1) APROM writes to itself if APUEN is set to 0.
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63 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
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64 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
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65 * | | |(4) Page Erase command at LOCK mode with ICE connection
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66 * | | |(5) Erase or Program command at brown-out detected
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67 * | | |(6) Destination address is illegal, such as over an available range.
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68 * | | |(7) Invalid ISP commands
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69 * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1
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70 * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1
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71 * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1
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72 * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0
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73 * | | |(12) Read any content of boot loader with ICE connection
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74 * | | |(13) The address of block erase and bank erase is not in APROM
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75 * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command
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76 * | | |(15) The wrong setting of page erase ISP CMD in XOM
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77 * | | |(16) Violate XOM setting one time protection
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78 * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page
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79 * | | |(18) Mass erase when MERASE (CFG0[13]) is disable
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80 * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP
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81 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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82 * |[16] |BL |Boot Loader Booting (Write Protect)
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83 * | | |This bit is initiated with the inverses value of MBS (CONFIG0[5])
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84 * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded
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85 * | | |This bit is used to check chip boot from Boot Loader or not
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86 * | | |User should keep original value of this bit when updating FMC_ISPCTL register.
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87 * | | |0 = Booting from APROM or LDROM.
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88 * | | |1 = Booting from Boot Loader.
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89 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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90 * |[24] |INTEN |Interrupt Enable (Write Protect)
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91 * | | |0 = ISP INT Disabled.
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92 * | | |1 = ISP INT Enabled.
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93 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.
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94 * @var FMC_T::ISPADDR
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95 * Offset: 0x04 ISP Address Register
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96 * ---------------------------------------------------------------------------------------------------
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97 * |Bits |Field |Descriptions
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98 * | :----: | :----: | :---- |
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99 * |[31:0] |ISPADDR |ISP Address
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100 * | | |The NuMicro M2351 series is equipped with embedded flash
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101 * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation
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102 * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
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103 * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation.
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104 * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)
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105 * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).
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106 * @var FMC_T::ISPDAT
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107 * Offset: 0x08 ISP Data Register
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108 * ---------------------------------------------------------------------------------------------------
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109 * |Bits |Field |Descriptions
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110 * | :----: | :----: | :---- |
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111 * |[31:0] |ISPDAT |ISP Data
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112 * | | |Write data to this register before ISP program operation.
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113 * | | |Read data from this register after ISP read operation.
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114 * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff
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115 * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment
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116 * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result
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117 * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect
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118 * | | |For XOM page erase function, , ISPDAT = 0x0055_aa03.
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119 * @var FMC_T::ISPCMD
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120 * Offset: 0x0C ISP Command Register
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121 * ---------------------------------------------------------------------------------------------------
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122 * |Bits |Field |Descriptions
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123 * | :----: | :----: | :---- |
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124 * |[6:0] |CMD |ISP Command
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125 * | | |ISP command table is shown below:
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126 * | | |0x00= FLASH Read.
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127 * | | |0x04= Read Unique ID.
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128 * | | |0x08= Read Flash All-One Result.
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129 * | | |0x0B= Read Company ID.
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130 * | | |0x0C= Read Device ID.
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131 * | | |0x0D= Read Checksum.
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132 * | | |0x21= FLASH 32-bit Program.
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133 * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.
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134 * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.
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135 * | | |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1..
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136 * | | |0x27= FLASH Multi-Word Program.
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137 * | | |0x28= Run Flash All-One Verification.
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138 * | | |0x2D= Run Checksum Calculation.
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139 * | | |0x2E= Vector Remap.
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140 * | | |0x40= FLASH 64-bit Read.
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141 * | | |0x61= FLASH 64-bit Program.
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142 * | | |The other commands are invalid.
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143 * @var FMC_T::ISPTRG
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144 * Offset: 0x10 ISP Trigger Control Register
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145 * ---------------------------------------------------------------------------------------------------
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146 * |Bits |Field |Descriptions
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147 * | :----: | :----: | :---- |
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148 * |[0] |ISPGO |ISP Start Trigger (Write Protect)
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149 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished
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150 * | | |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0
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151 * | | |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY.
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152 * | | |0 = ISP operation is finished.
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153 * | | |1 = ISP is progressed.
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154 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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155 * @var FMC_T::ISPSTS
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156 * Offset: 0x40 ISP Status Register
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157 * ---------------------------------------------------------------------------------------------------
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158 * |Bits |Field |Descriptions
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159 * | :----: | :----: | :---- |
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160 * |[0] |ISPBUSY |ISP Busy Flag (Read Only)
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161 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
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162 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
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163 * | | |0 = ISP operation is finished.
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164 * | | |1 = ISP is progressed.
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165 * |[2] |CBS |Boot Selection of CONFIG (Read Only)
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166 * | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
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167 * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
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168 * | | |0 = LDROM with IAP mode.
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169 * | | |1 = APROM with IAP mode.
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170 * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
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171 * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
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172 * | | |0 = Booting from Boot Loader.
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173 * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting)
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174 * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)
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175 * | | |This bit is set if flash access cycle auto-tuning function is disabled
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176 * | | |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
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177 * | | |0 = Flash access cycle auto-tuning is Enabled.
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178 * | | |1 = Flash access cycle auto-tuning is Disabled.
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179 * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only)
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180 * | | |This bit is set if data is mismatched at ISP programming verification
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181 * | | |This bit is clear by performing ISP flash erase or ISP read CID operation
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182 * | | |0 = Flash Program is success.
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183 * | | |1 = Flash Program is fail. Program data is different with data in the flash memory
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184 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
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185 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set.
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186 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
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187 * | | |(1) APROM writes to itself if APUEN is set to 0.
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188 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
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189 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
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190 * | | |(4) Page Erase command at LOCK mode with ICE connection
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191 * | | |(5) Erase or Program command at brown-out detected
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192 * | | |(6) Destination address is illegal, such as over an available range.
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193 * | | |(7) Invalid ISP commands
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194 * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1
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195 * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1
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196 * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1
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197 * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.
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198 * | | |(12) Read any content of boot loader with ICE connection
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199 * | | |(13) The address of block erase and bank erase is not in APROM
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200 * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command
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201 * | | |(15) The wrong setting of page erase ISP CMD in XOM
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202 * | | |(16) Violate XOM setting one time protection
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203 * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page
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204 * | | |(18) Mass erase when MERASE (CFG0[13]) is disable
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205 * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP
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206 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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207 * |[7] |ALLONE |Flash All-one Verification Flag
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208 * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1
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209 * | | |0 = All of flash bits are 1 after Run Flash All-One Verification complete.
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210 * | | |1 = Flash bits are not all 1 after Run Flash All-One Verification complete.
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211 * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
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212 * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
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213 * |[24] |INTFLAG |Interrupt Flag
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214 * | | |0 = ISP is not finish.
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215 * | | |1 = ISP done or ISPFF set.
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216 * @var FMC_T::CYCCTL
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217 * Offset: 0x4C Flash Access Cycle Control Register
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218 * ---------------------------------------------------------------------------------------------------
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219 * |Bits |Field |Descriptions
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220 * | :----: | :----: | :---- |
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221 * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
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222 * | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).
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223 * | | |When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle >0.
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224 * | | |0000 = CPU access with zero wait cycle ; Flash access cycle is 1. The HCLK working frequency range is <27MHz; Cache is disabled by hardware.
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225 * | | |0001 = CPU access with one wait cycle if cache miss; Flash access cycle is 1. The HCLK working frequency range range is<27MHz.
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226 * | | |0010 = CPU access with two wait cycles if cache miss; Flash access cycle is 2. The optimized HCLK working frequency range is 25~52 MHz.
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227 * | | |0011 = CPU access with three wait cycles if cache miss; Flash access cycle is 3. The optimized HCLK working frequency range is 49~79MHz.
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228 * | | |Others = Reserved.
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229 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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230 * |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect)
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231 * | | |Set this bit to disable flash access cycle auto-tuning function
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232 * | | |0 = Flash access cycle auto-tuning is enabled.
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233 * | | |1 = Flash access cycle auto-tuning is disabled.
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234 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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235 * @var FMC_T::KPKEY0
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236 * Offset: 0x50 KPROM KEY0 Data Register
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237 * ---------------------------------------------------------------------------------------------------
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238 * |Bits |Field |Descriptions
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239 * | :----: | :----: | :---- |
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240 * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only)
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241 * | | |Write KPKEY0 data to this register before KEY Comparison operation.
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242 * @var FMC_T::KPKEY1
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243 * Offset: 0x54 KPROM KEY1 Data Register
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244 * ---------------------------------------------------------------------------------------------------
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245 * |Bits |Field |Descriptions
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246 * | :----: | :----: | :---- |
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247 * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only)
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248 * | | |Write KPKEY1 data to this register before KEY Comparison operation.
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249 * @var FMC_T::KPKEY2
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250 * Offset: 0x58 KPROM KEY2 Data Register
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251 * ---------------------------------------------------------------------------------------------------
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252 * |Bits |Field |Descriptions
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253 * | :----: | :----: | :---- |
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254 * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only)
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255 * | | |Write KPKEY2 data to this register before KEY Comparison operation.
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256 * @var FMC_T::KPKEYTRG
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257 * Offset: 0x5C KPROM KEY Comparison Trigger Control Register
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258 * ---------------------------------------------------------------------------------------------------
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259 * |Bits |Field |Descriptions
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260 * | :----: | :----: | :---- |
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261 * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection)
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262 * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished
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263 * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.
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264 * | | |0 = KEY comparison operation is finished.
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265 * | | |1 = KEY comparison is progressed.
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266 * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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267 * |[1] |TCEN |Timeout Counting Enable (Write Protection)
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268 * | | |0 = Timeout counting is disabled.
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269 * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish.
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270 * | | |10 minutes is at least for timeout, and average is about 20 minutes.
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271 * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
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272 * @var FMC_T::KPKEYSTS
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273 * Offset: 0x60 KPROM KEY Comparison Status Register
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274 * ---------------------------------------------------------------------------------------------------
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275 * |Bits |Field |Descriptions
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276 * | :----: | :----: | :---- |
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277 * |[0] |KEYBUSY |KEY Comparison Busy (Read Only)
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278 * | | |0 = KEY comparison is finished.
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279 * | | |1 = KEY comparison is busy.
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280 * |[1] |KEYLOCK |KEY LOCK Flag
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281 * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection
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282 * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0
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283 * | | |This bit also can be set to 1 while
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284 * | | |l CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
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285 * | | |l KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or
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286 * | | |l KEYENROM is programmed a non-0x5a value or
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287 * | | |l Timeout event or
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288 * | | |l FORBID(FMC_KPKEYSTS[3]) is 1
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289 * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection.
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290 * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection.
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291 * | | |CONFIG write protect is depended on CFGFLAG
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292 * |[2] |KEYMATCH |KEY Match Flag (Read Only)
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293 * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched
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294 * | | |This bit is also cleared to 0 while
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295 * | | |l CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or
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296 * | | |l Timeout event or
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297 * | | |l KPROM is erased or
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298 * | | |l KEYENROM is programmed to a non-0x5a value.
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299 * | | |l Chip is in power down mode.
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300 * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting.
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301 * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting.
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302 * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only)
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303 * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]).
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304 * | | |0 = KEY comparison is not forbidden.
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305 * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger.
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306 * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only)
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307 * | | |This bit is set while the KEYENROM [7:0] is not 0x5a at power-on or reset
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308 * | | |This bit is cleared to 0 by hardware while KPROM is erased
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309 * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0x5a value.
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310 * | | |0 = Security Key protection is disabled.
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311 * | | |1 = Security Key protection is enabled.
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312 * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only)
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313 * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset
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314 * | | |This bit is cleared to 0 by hardware while KPROM is erased
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315 * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.
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316 * | | |0 = CONFIG write-protection is disabled.
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317 * | | |1 = CONFIG write-protection is enabled.
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318 * |[8] |SBKPBUSY |Secure Boot Key Programming BUSY (Read Only)
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319 * | | |This bit is set to 1 while secure boot key program function is running
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320 * | | |This bit is cleared to 0 while secure boot key key program function had been done.
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321 * | | |0 = Secure boot key program function is done.
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322 * | | |1 = Secure boot key program function is busy.
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323 * |[9] |SBKPFLAG |Secure Boot Key Programming Flag (Read Only)
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324 * | | |This bit is set to 1 while secure boot key program function fails
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325 * | | |This bit is cleared to 0 while secure boot key had been programmed into flash memory.
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326 * | | |0 = Secure boot key program function is successful.
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327 * | | |1 = Secure boot key program function fails.
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328 * @var FMC_T::KPKEYCNT
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329 * Offset: 0x64 KPROM KEY-Unmatched Counting Register
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330 * ---------------------------------------------------------------------------------------------------
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331 * |Bits |Field |Descriptions
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332 * | :----: | :----: | :---- |
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333 * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only)
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334 * | | |KPKECNT is increased when entry keys is wrong in Security Key protection
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335 * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on.
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336 * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only)
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337 * | | |KPKEMAX is the maximum error key entry number at each power-on
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338 * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated
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339 * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting
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340 * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.
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341 * @var FMC_T::KPCNT
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342 * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register
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343 * ---------------------------------------------------------------------------------------------------
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344 * |Bits |Field |Descriptions
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345 * | :----: | :----: | :---- |
\r
346 * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only)
\r
347 * | | |KPCNT is the power-on counting for error key entry in Security Key protection
\r
348 * | | |KPCNT is cleared to 0 if key comparison is matched.
\r
349 * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only)
\r
350 * | | |KPMAX is the power-on maximum number for error key entry
\r
351 * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated
\r
352 * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting
\r
353 * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX
\r
354 * @var FMC_T::MPDAT0
\r
355 * Offset: 0x80 ISP Data0 Register
\r
356 * ---------------------------------------------------------------------------------------------------
\r
357 * |Bits |Field |Descriptions
\r
358 * | :----: | :----: | :---- |
\r
359 * |[31:0] |ISPDAT0 |ISP Data 0
\r
360 * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
\r
361 * @var FMC_T::MPDAT1
\r
362 * Offset: 0x84 ISP Data1 Register
\r
363 * ---------------------------------------------------------------------------------------------------
\r
364 * |Bits |Field |Descriptions
\r
365 * | :----: | :----: | :---- |
\r
366 * |[31:0] |ISPDAT1 |ISP Data 1
\r
367 * | | |This register is the second 32-bit data for 64-bit/multi-word programming.
\r
368 * @var FMC_T::MPDAT2
\r
369 * Offset: 0x88 ISP Data2 Register
\r
370 * ---------------------------------------------------------------------------------------------------
\r
371 * |Bits |Field |Descriptions
\r
372 * | :----: | :----: | :---- |
\r
373 * |[31:0] |ISPDAT2 |ISP Data 2
\r
374 * | | |This register is the third 32-bit data for multi-word programming.
\r
375 * @var FMC_T::MPDAT3
\r
376 * Offset: 0x8C ISP Data3 Register
\r
377 * ---------------------------------------------------------------------------------------------------
\r
378 * |Bits |Field |Descriptions
\r
379 * | :----: | :----: | :---- |
\r
380 * |[31:0] |ISPDAT3 |ISP Data 3
\r
381 * | | |This register is the fourth 32-bit data for multi-word programming.
\r
382 * @var FMC_T::MPSTS
\r
383 * Offset: 0xC0 ISP Multi-Program Status Register
\r
384 * ---------------------------------------------------------------------------------------------------
\r
385 * |Bits |Field |Descriptions
\r
386 * | :----: | :----: | :---- |
\r
387 * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only)
\r
388 * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
\r
389 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
\r
390 * | | |0 = ISP Multi-Word program operation is finished.
\r
391 * | | |1 = ISP Multi-Word program operation is progressed.
\r
392 * |[1] |PPGO |ISP Multi-program Status (Read Only)
\r
393 * | | |0 = ISP multi-word program operation is not active.
\r
394 * | | |1 = ISP multi-word program operation is in progress.
\r
395 * |[2] |ISPFF |ISP Fail Flag (Read Only)
\r
396 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
\r
397 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
\r
398 * | | |(1) APROM writes to itself if APUEN is set to 0.
\r
399 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
\r
400 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
\r
401 * | | |(4) Page Erase command at LOCK mode with ICE connection
\r
402 * | | |(5) Erase or Program command at brown-out detected
\r
403 * | | |(6) Destination address is illegal, such as over an available range.
\r
404 * | | |(7) Invalid ISP commands
\r
405 * |[4] |D0 |ISP DATA 0 Flag (Read Only)
\r
406 * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
\r
407 * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
\r
408 * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
\r
409 * |[5] |D1 |ISP DATA 1 Flag (Read Only)
\r
410 * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
\r
411 * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
\r
412 * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
\r
413 * |[6] |D2 |ISP DATA 2 Flag (Read Only)
\r
414 * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
\r
415 * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
\r
416 * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
\r
417 * |[7] |D3 |ISP DATA 3 Flag (Read Only)
\r
418 * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
\r
419 * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
\r
420 * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
\r
421 * @var FMC_T::MPADDR
\r
422 * Offset: 0xC4 ISP Multi-Program Address Register
\r
423 * ---------------------------------------------------------------------------------------------------
\r
424 * |Bits |Field |Descriptions
\r
425 * | :----: | :----: | :---- |
\r
426 * |[31:0] |MPADDR |ISP Multi-word Program Address
\r
427 * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
\r
428 * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
\r
429 * @var FMC_T::XOMR0STS
\r
430 * Offset: 0xD0 XOM Region 0 Status Register
\r
431 * ---------------------------------------------------------------------------------------------------
\r
432 * |Bits |Field |Descriptions
\r
433 * | :----: | :----: | :---- |
\r
434 * |[7:0] |SIZE |XOM Region 0 Size (Page-aligned)
\r
435 * | | |SIZE is the page number of XOM Region 0.
\r
436 * |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned)
\r
437 * | | |BASE is the base address of XOM Region 0.
\r
438 * @var FMC_T::XOMR1STS
\r
439 * Offset: 0xD4 XOM Region 1 Status Register
\r
440 * ---------------------------------------------------------------------------------------------------
\r
441 * |Bits |Field |Descriptions
\r
442 * | :----: | :----: | :---- |
\r
443 * |[7:0] |SIZE |XOM Region 1 Size (Page-aligned)
\r
444 * | | |SIZE is the page number of XOM Region 1.
\r
445 * |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned)
\r
446 * | | |BASE is the base address of XOM Region 1.
\r
447 * @var FMC_T::XOMR2STS
\r
448 * Offset: 0xD8 XOM Region 2 Status Register
\r
449 * ---------------------------------------------------------------------------------------------------
\r
450 * |Bits |Field |Descriptions
\r
451 * | :----: | :----: | :---- |
\r
452 * |[7:0] |SIZE |XOM Region 2 Size (Page-aligned)
\r
453 * | | |SIZE is the page number of XOM Region 2.
\r
454 * |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned)
\r
455 * | | |BASE is the base address of XOM Region 2.
\r
456 * @var FMC_T::XOMR3STS
\r
457 * Offset: 0xDC XOM Region 3 Status Register
\r
458 * ---------------------------------------------------------------------------------------------------
\r
459 * |Bits |Field |Descriptions
\r
460 * | :----: | :----: | :---- |
\r
461 * |[7:0] |SIZE |XOM Region 3 Size (Page-aligned)
\r
462 * | | |SIZE is the page number of XOM Region 3.
\r
463 * |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned)
\r
464 * | | |BASE is the base address of XOM Region 3.
\r
465 * @var FMC_T::XOMSTS
\r
466 * Offset: 0xE0 XOM Status Register
\r
467 * ---------------------------------------------------------------------------------------------------
\r
468 * |Bits |Field |Descriptions
\r
469 * | :----: | :----: | :---- |
\r
470 * |[0] |XOMR0ON |XOM Region 0 On
\r
471 * | | |XOM Region 0 active status.
\r
472 * | | |0 = No active.
\r
473 * | | |1 = XOM region 0 is active.
\r
474 * |[1] |XOMR1ON |XOM Region 1 On
\r
475 * | | |XOM Region 1 active status.
\r
476 * | | |0 = No active.
\r
477 * | | |1 = XOM region 1 is active.
\r
478 * |[2] |XOMR2ON |XOM Region 2 On
\r
479 * | | |XOM Region 2 active status.
\r
480 * | | |0 = No active.
\r
481 * | | |1 = XOM region 2 is active.
\r
482 * |[3] |XOMR3ON |XOM Region 3 On
\r
483 * | | |XOM Region 3 active status.
\r
484 * | | |0 = No active.
\r
485 * | | |1 = XOM region 3 is active.
\r
486 * |[4] |XOMPEF |XOM Page Erase Function Fail
\r
487 * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
\r
488 * | | |0 = Success.
\r
491 __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */
\r
492 __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */
\r
493 __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */
\r
494 __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */
\r
495 __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */
\r
496 __I uint32_t RESERVE0[11];
\r
497 __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */
\r
498 __I uint32_t RESERVE1[2];
\r
499 __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */
\r
500 __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */
\r
501 __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */
\r
502 __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */
\r
503 __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */
\r
504 __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */
\r
505 __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */
\r
506 __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */
\r
507 __I uint32_t RESERVE2[5];
\r
508 __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */
\r
509 __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */
\r
510 __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */
\r
511 __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */
\r
512 __I uint32_t RESERVE3[12];
\r
513 __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */
\r
514 __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */
\r
515 __I uint32_t RESERVE4[2];
\r
516 __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */
\r
517 __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */
\r
518 __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */
\r
519 __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */
\r
520 __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */
\r
525 @addtogroup FMC_CONST FMC Bit Field Definition
\r
526 Constant Definitions for FMC Controller
\r
529 #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
\r
530 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
\r
532 #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
\r
533 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
\r
535 #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
\r
536 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
\r
538 #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
\r
539 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
\r
541 #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
\r
542 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
\r
544 #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
\r
545 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
\r
547 #define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
\r
548 #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
\r
550 #define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */
\r
551 #define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */
\r
553 #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
\r
554 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
\r
556 #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
\r
557 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
\r
559 #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
\r
560 #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
\r
562 #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
\r
563 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
\r
565 #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
\r
566 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
\r
568 #define FMC_ISPSTS_CBS_Pos (2) /*!< FMC_T::ISPSTS: CBS Position */
\r
569 #define FMC_ISPSTS_CBS_Msk (0x1ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
\r
571 #define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
\r
572 #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
\r
574 #define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */
\r
575 #define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */
\r
577 #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
\r
578 #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
\r
580 #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
\r
581 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
\r
583 #define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */
\r
584 #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */
\r
586 #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
\r
587 #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
\r
589 #define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */
\r
590 #define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */
\r
592 #define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */
\r
593 #define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */
\r
595 #define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */
\r
596 #define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */
\r
598 #define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */
\r
599 #define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */
\r
601 #define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */
\r
602 #define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */
\r
604 #define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */
\r
605 #define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */
\r
607 #define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */
\r
608 #define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */
\r
610 #define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */
\r
611 #define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */
\r
613 #define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */
\r
614 #define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */
\r
616 #define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */
\r
617 #define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */
\r
619 #define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */
\r
620 #define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */
\r
622 #define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */
\r
623 #define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */
\r
625 #define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */
\r
626 #define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */
\r
628 #define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */
\r
629 #define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */
\r
631 #define FMC_KPKEYSTS_SBKPBUSY_Pos (8) /*!< FMC_T::KPKEYSTS: SBKPBUSY Position */
\r
632 #define FMC_KPKEYSTS_SBKPBUSY_Msk (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos) /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask */
\r
634 #define FMC_KPKEYSTS_SBKPFLAG_Pos (9) /*!< FMC_T::KPKEYSTS: SBKPFLAG Position */
\r
635 #define FMC_KPKEYSTS_SBKPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask */
\r
637 #define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */
\r
638 #define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */
\r
640 #define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */
\r
641 #define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */
\r
643 #define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */
\r
644 #define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */
\r
646 #define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */
\r
647 #define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */
\r
649 #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
\r
650 #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
\r
652 #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
\r
653 #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
\r
655 #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
\r
656 #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
\r
658 #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
\r
659 #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
\r
661 #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
\r
662 #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
\r
664 #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
\r
665 #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
\r
667 #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
\r
668 #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
\r
670 #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
\r
671 #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
\r
673 #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
\r
674 #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
\r
676 #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
\r
677 #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
\r
679 #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
\r
680 #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
\r
682 #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
\r
683 #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
\r
685 #define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */
\r
686 #define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */
\r
688 #define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */
\r
689 #define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */
\r
691 #define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */
\r
692 #define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */
\r
694 #define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */
\r
695 #define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */
\r
697 #define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */
\r
698 #define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */
\r
700 #define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */
\r
701 #define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOMR2STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */
\r
703 #define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */
\r
704 #define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */
\r
706 #define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */
\r
707 #define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */
\r
709 #define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */
\r
710 #define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */
\r
712 #define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */
\r
713 #define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */
\r
715 #define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */
\r
716 #define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */
\r
718 #define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */
\r
719 #define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */
\r
721 #define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */
\r
722 #define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */
\r
724 /**@}*/ /* FMC_CONST */
\r
725 /**@}*/ /* end of FMC register group */
\r
726 /**@}*/ /* end of REGISTER group */
\r
728 #endif /* __FMC_REG_H__ */
\r
projects / freertos / blob