1 /**************************************************************************//**
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4 * @brief PDMA register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __PDMA_REG_H__
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9 #define __PDMA_REG_H__
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11 /** @addtogroup REGISTER Control Register
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17 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
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19 @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
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20 Memory Mapped Structure for PDMA Controller
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29 * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70 Descriptor Table Control Register of PDMA Channel 0~7
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30 * ---------------------------------------------------------------------------------------------------
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31 * |Bits |Field |Descriptions
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32 * | :----: | :----: | :---- |
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33 * |[1:0] |OPMODE |PDMA Operation Mode Selection
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34 * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
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35 * | | |01 = Basic mode: The descriptor table only has one task
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36 * | | |When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted.
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37 * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute.
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38 * | | |11 = Reserved.
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39 * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
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40 * |[2] |TXTYPE |Transfer Type
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41 * | | |0 = Burst transfer type.
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42 * | | |1 = Single transfer type.
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43 * |[6:4] |BURSIZE |Burst Size
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44 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
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45 * | | |000 = 128 Transfers.
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46 * | | |001 = 64 Transfers.
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47 * | | |010 = 32 Transfers.
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48 * | | |011 = 16 Transfers.
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49 * | | |100 = 8 Transfers.
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50 * | | |101 = 4 Transfers.
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51 * | | |110 = 2 Transfers.
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52 * | | |111 = 1 Transfers.
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53 * | | |Note: This field is only useful in burst transfer type.
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54 * |[7] |TBINTDIS |Table Interrupt Disable Bit
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55 * | | |This field can be used to decide whether to enable table interrupt or not
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56 * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
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57 * | | |0 = Table interrupt Enabled.
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58 * | | |1 = Table interrupt Disabled.
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59 * | | |Note: If this bit set to 1, the TEMPTYF will not be set.
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60 * |[9:8] |SAINC |Source Address Increment
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61 * | | |This field is used to set the source address increment size.
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62 * | | |11 = No increment (fixed address).
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63 * | | |Others = Increment and size is depended on TXWIDTH selection.
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64 * |[11:10] |DAINC |Destination Address Increment
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65 * | | |This field is used to set the destination address increment size.
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66 * | | |11 = No increment (fixed address).
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67 * | | |Others = Increment and size is depended on TXWIDTH selection.
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68 * |[13:12] |TXWIDTH |Transfer Width Selection
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69 * | | |This field is used for transfer width.
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70 * | | |00 = One byte (8 bit) is transferred for every operation.
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71 * | | |01 = One half-word (16 bit) is transferred for every operation.
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72 * | | |10 = One word (32-bit) is transferred for every operation.
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73 * | | |11 = Reserved.
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74 * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
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75 * | | |For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment
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76 * | | |The source address is aligned when TXWIDTH is byte or half-word transfer.
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77 * |[14] |TXACK |Transfer Acknowledge Selection
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78 * | | |0 = transfer ack when transfer done.
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79 * | | |1 = transfer ack when PDMA get transfer data.
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80 * |[15] |STRIDEEN |Stride Mode Enable Bit
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81 * | | |0 = Stride transfer mode Disabled.
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82 * | | |1 = Stride transfer mode Enabled.
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83 * |[31:16] |TXCNT |Transfer Count
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84 * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
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85 * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
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87 * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74 Source Address Register of PDMA Channel 0~7
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88 * ---------------------------------------------------------------------------------------------------
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89 * |Bits |Field |Descriptions
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90 * | :----: | :----: | :---- |
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91 * |[31:0] |SA |PDMA Transfer Source Address Register
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92 * | | |This field indicates a 32-bit source address of PDMA controller.
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93 * | | |Note: The PDMA transfer source address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.
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95 * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78 Destination Address Register of PDMA Channel 0~7
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96 * ---------------------------------------------------------------------------------------------------
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97 * |Bits |Field |Descriptions
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98 * | :----: | :----: | :---- |
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99 * |[31:0] |DA |PDMA Transfer Destination Address Register
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100 * | | |This field indicates a 32-bit destination address of PDMA controller.
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101 * | | |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.
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102 * @var DSCT_T::NEXT
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103 * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7
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104 * ---------------------------------------------------------------------------------------------------
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105 * |Bits |Field |Descriptions
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106 * | :----: | :----: | :---- |
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107 * |[15:0] |FIRST |PDMA First Descriptor Table Offset
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108 * | | |This field indicates the offset of the first descriptor table address in system memory.
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109 * | | |Write Operation:
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110 * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
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111 * | | |Read Operation:
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112 * | | |When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.
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113 * | | |Note1: The first descriptor table address must be word boundary.
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114 * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
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115 * |[31:16] |NEXT |PDMA Next Descriptor Table Offset
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116 * | | |This field indicates the offset of next descriptor table address in system memory.
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117 * | | |Note: write operation is useless in this field.
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120 __IO uint32_t CTL; /*!< [0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7 */
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121 __IO uint32_t SA; /*!< [0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7 */
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122 __IO uint32_t DA; /*!< [0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7 */
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123 __IO uint32_t NEXT; /*!< [0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C]Next Scatter-Gather Descriptor Table Offset */
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130 * @var STRIDE_T::STCR
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131 * Offset: 0x500/0x508/0x510/0x518/0x520/0x528 Stride Transfer Count Register of PDMA Channel 0~5
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132 * ---------------------------------------------------------------------------------------------------
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133 * |Bits |Field |Descriptions
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134 * | :----: | :----: | :---- |
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135 * |[15:0] |STC |PDMA Stride Transfer Count
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136 * | | |The 16-bit register defines the stride transfer count of each row.
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137 * @var STRIDE_T::ASOCR
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138 * Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C Address Stride Offset Register of PDMA Channel 0~5
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139 * ---------------------------------------------------------------------------------------------------
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140 * |Bits |Field |Descriptions
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141 * | :----: | :----: | :---- |
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142 * |[15:0] |SASOL |VDMA Source Address Stride Offset Length
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143 * | | |The 16-bit register defines the source address stride transfer offset count of each row.
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144 * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length
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145 * | | |The 16-bit register defines the destination address stride transfer offset count of each row.
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147 __IO uint32_t STCR; /*!< [0x0500/0x508/0x510/0x518/0x520/0x528] Stride Transfer Count Register of PDMA Channel 0~7 */
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148 __IO uint32_t ASOCR; /*!< [0x0504/0x50C/0x514/0x51C/0x524/0x52C] Address Stride Offset Register of PDMA Channel 0 */
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156 * @var PDMA_T::CURSCAT
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157 * Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x98/0x9C Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7
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158 * ---------------------------------------------------------------------------------------------------
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159 * |Bits |Field |Descriptions
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160 * | :----: | :----: | :---- |
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161 * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
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162 * | | |This field indicates a 32-bit current external description address of PDMA controller.
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163 * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
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164 * @var PDMA_T::CHCTL
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165 * Offset: 0x400 PDMA Channel Control Register
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166 * ---------------------------------------------------------------------------------------------------
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167 * |Bits |Field |Descriptions
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168 * | :----: | :----: | :---- |
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169 * |[15:0] |CHENn |PDMA Channel Enable Bit
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170 * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
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171 * | | |0 = PDMA channel [n] Disabled.
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172 * | | |1 = PDMA channel [n] Enabled.
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173 * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
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174 * @var PDMA_T::PAUSE
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175 * Offset: 0x404 PDMA Transfer Pause Control Register
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176 * ---------------------------------------------------------------------------------------------------
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177 * |Bits |Field |Descriptions
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178 * | :----: | :----: | :---- |
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179 * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only)
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180 * | | |User can set PAUSEn bit field to pause the PDMA transfer
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181 * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag
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182 * | | |If re-enable the paused channel again, the remaining transfers will be processed.
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183 * | | |0 = No effect.
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184 * | | |1 = Pause PDMA channel n transfer.
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185 * @var PDMA_T::SWREQ
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186 * Offset: 0x408 PDMA Software Request Register
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187 * ---------------------------------------------------------------------------------------------------
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188 * |Bits |Field |Descriptions
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189 * | :----: | :----: | :---- |
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190 * |[15:0] |SWREQn |PDMA Software Request Register (Write Only)
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191 * | | |Set this bit to 1 to generate a software request to PDMA [n].
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192 * | | |0 = No effect.
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193 * | | |1 = Generate a software request.
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194 * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active
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195 * | | |Active flag may be triggered by software request or peripheral request.
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196 * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
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197 * @var PDMA_T::TRGSTS
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198 * Offset: 0x40C PDMA Channel Request Status Register
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199 * ---------------------------------------------------------------------------------------------------
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200 * |Bits |Field |Descriptions
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201 * | :----: | :----: | :---- |
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202 * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only)
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203 * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral
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204 * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
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205 * | | |0 = PDMA Channel n has no request.
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206 * | | |1 = PDMA Channel n has a request.
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207 * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
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208 * @var PDMA_T::PRISET
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209 * Offset: 0x410 PDMA Fixed Priority Setting Register
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210 * ---------------------------------------------------------------------------------------------------
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211 * |Bits |Field |Descriptions
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212 * | :----: | :----: | :---- |
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213 * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register
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214 * | | |Set this bit to 1 to enable fixed priority level.
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215 * | | |Write Operation:
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216 * | | |0 = No effect.
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217 * | | |1 = Set PDMA channel [n] to fixed priority channel.
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218 * | | |Read Operation:
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219 * | | |0 = Corresponding PDMA channel is round-robin priority.
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220 * | | |1 = Corresponding PDMA channel is fixed priority.
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221 * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
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222 * @var PDMA_T::PRICLR
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223 * Offset: 0x414 PDMA Fixed Priority Clear Register
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224 * ---------------------------------------------------------------------------------------------------
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225 * |Bits |Field |Descriptions
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226 * | :----: | :----: | :---- |
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227 * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
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228 * | | |Set this bit to 1 to clear fixed priority level.
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229 * | | |0 = No effect.
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230 * | | |1 = Clear PDMA channel [n] fixed priority setting.
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231 * | | |Note: User can read PDMA_PRISET register to know the channel priority.
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232 * @var PDMA_T::INTEN
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233 * Offset: 0x418 PDMA Interrupt Enable Register
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234 * ---------------------------------------------------------------------------------------------------
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235 * |Bits |Field |Descriptions
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236 * | :----: | :----: | :---- |
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237 * |[15:0] |INTENn |PDMA Interrupt Enable Register
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238 * | | |This field is used for enabling PDMA channel[n] interrupt.
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239 * | | |0 = PDMA channel n interrupt Disabled.
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240 * | | |1 = PDMA channel n interrupt Enabled.
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241 * @var PDMA_T::INTSTS
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242 * Offset: 0x41C PDMA Interrupt Status Register
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243 * ---------------------------------------------------------------------------------------------------
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244 * |Bits |Field |Descriptions
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245 * | :----: | :----: | :---- |
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246 * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only)
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247 * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
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248 * | | |0 = No AHB bus ERROR response received.
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249 * | | |1 = AHB bus ERROR response received.
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250 * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
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251 * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
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252 * | | |0 = Not finished yet.
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253 * | | |1 = PDMA channel has finished transmission.
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254 * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only)
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255 * | | |0 = PDMA channel source address and destination address both follow transfer width setting.
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256 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
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257 * |[8] |REQTOF0 |Request Time-out Flag for Channel 0
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258 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
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259 * | | |0 = No request time-out.
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260 * | | |1 = Peripheral request time-out.
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261 * |[9] |REQTOF1 |Request Time-out Flag for Channel 1
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262 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
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263 * | | |0 = No request time-out.
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264 * | | |1 = Peripheral request time-out.
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265 * @var PDMA_T::ABTSTS
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266 * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
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267 * ---------------------------------------------------------------------------------------------------
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268 * |Bits |Field |Descriptions
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269 * | :----: | :----: | :---- |
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270 * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
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271 * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
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272 * | | |0 = No AHB bus ERROR response received when channel n transfer.
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273 * | | |1 = AHB bus ERROR response received when channel n transfer.
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274 * @var PDMA_T::TDSTS
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275 * Offset: 0x424 PDMA Channel Transfer Done Flag Register
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276 * ---------------------------------------------------------------------------------------------------
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277 * |Bits |Field |Descriptions
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278 * | :----: | :----: | :---- |
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279 * |[15:0] |TDIFn |Transfer Done Flag Register
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280 * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
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281 * | | |0 = PDMA channel transfer has not finished.
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282 * | | |1 = PDMA channel has finished transmission.
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283 * @var PDMA_T::ALIGN
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284 * Offset: 0x428 PDMA Transfer Alignment Status Register
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285 * ---------------------------------------------------------------------------------------------------
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286 * |Bits |Field |Descriptions
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287 * | :----: | :----: | :---- |
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288 * |[15:0] |ALIGNn |Transfer Alignment Flag Register
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289 * | | |0 = PDMA channel source address and destination address both follow transfer width setting.
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290 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting.
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291 * @var PDMA_T::TACTSTS
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292 * Offset: 0x42C PDMA Transfer Active Flag Register
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293 * ---------------------------------------------------------------------------------------------------
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294 * |Bits |Field |Descriptions
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295 * | :----: | :----: | :---- |
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296 * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only)
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297 * | | |This bit indicates which PDMA channel is in active.
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298 * | | |0 = PDMA channel is not finished.
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299 * | | |1 = PDMA channel is active.
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300 * @var PDMA_T::TOUTPSC
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301 * Offset: 0x430 PDMA Time-out Prescaler Register
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302 * ---------------------------------------------------------------------------------------------------
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303 * |Bits |Field |Descriptions
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304 * | :----: | :----: | :---- |
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305 * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits
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306 * | | |000 = PDMA channel 0 time-out clock source is HCLK/2^8.
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307 * | | |001 = PDMA channel 0 time-out clock source is HCLK/2^9.
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308 * | | |010 = PDMA channel 0 time-out clock source is HCLK/2^10.
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309 * | | |011 = PDMA channel 0 time-out clock source is HCLK/2^11.
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310 * | | |100 = PDMA channel 0 time-out clock source is HCLK/2^12.
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311 * | | |101 = PDMA channel 0 time-out clock source is HCLK/2^13.
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312 * | | |110 = PDMA channel 0 time-out clock source is HCLK/2^14.
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313 * | | |111 = PDMA channel 0 time-out clock source is HCLK/2^15.
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314 * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits
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315 * | | |000 = PDMA channel 1 time-out clock source is HCLK/2^8.
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316 * | | |001 = PDMA channel 1 time-out clock source is HCLK/2^9.
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317 * | | |010 = PDMA channel 1 time-out clock source is HCLK/2^10.
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318 * | | |011 = PDMA channel 1 time-out clock source is HCLK/2^11.
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319 * | | |100 = PDMA channel 1 time-out clock source is HCLK/2^12.
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320 * | | |101 = PDMA channel 1 time-out clock source is HCLK/2^13.
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321 * | | |110 = PDMA channel 1 time-out clock source is HCLK/2^14.
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322 * | | |111 = PDMA channel 1 time-out clock source is HCLK/2^15.
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323 * @var PDMA_T::TOUTEN
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324 * Offset: 0x434 PDMA Time-out Enable Register
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325 * ---------------------------------------------------------------------------------------------------
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326 * |Bits |Field |Descriptions
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327 * | :----: | :----: | :---- |
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328 * |[0] |TOUTEN0 |PDMA Channel 0 Time-out Enable Bit
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329 * | | |0 = PDMA Channel 0 time-out function Disable.
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330 * | | |1 = PDMA Channel 0 time-out function Enable.
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331 * |[1] |TOUTEN1 |PDMA Channel 1 Time-out Enable Bit
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332 * | | |0 = PDMA Channel 1 time-out function Disable.
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333 * | | |1 = PDMA Channel 1 time-out function Enable.
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334 * @var PDMA_T::TOUTIEN
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335 * Offset: 0x438 PDMA Time-out Interrupt Enable Register
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336 * ---------------------------------------------------------------------------------------------------
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337 * |Bits |Field |Descriptions
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338 * | :----: | :----: | :---- |
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339 * |[0] |TOUTIEN0 |PDMA Channel 0 Time-out Interrupt Enable Bit
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340 * | | |0 = PDMA Channel 0 time-out interrupt Disable.
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341 * | | |1 = PDMA Channel 0 time-out interrupt Enable.
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342 * |[1] |TOUTIEN1 |PDMA Channel 1 Time-out Interrupt Enable Bit
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343 * | | |0 = PDMA Channel 1 time-out interrupt Disable.
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344 * | | |1 = PDMA Channel 1 time-out interrupt Enable.
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345 * @var PDMA_T::SCATBA
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346 * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
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347 * ---------------------------------------------------------------------------------------------------
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348 * |Bits |Field |Descriptions
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349 * | :----: | :----: | :---- |
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350 * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register
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351 * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address
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352 * | | |The next link address equation is
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353 * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
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354 * | | |Note: Only useful in Scatter-Gather mode.
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355 * @var PDMA_T::TOC0_1
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356 * Offset: 0x440 PDMA Channel 0 and Channel 1 Time-out Counter Register
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357 * ---------------------------------------------------------------------------------------------------
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358 * |Bits |Field |Descriptions
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359 * | :----: | :----: | :---- |
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360 * |[15:0] |TOC0 |Time-out Counter for Channel 0
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361 * | | |This controls the period of time-out function for channel 0
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362 * | | |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.
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363 * | | |Time-out period = (Period of time-out clock) * (16-bit TOCn),n = 0,1.
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364 * |[31:16] |TOC1 |Time-out Counter for Channel 1
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365 * | | |This controls the period of time-out function for channel 1
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366 * | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock
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367 * | | |The example of time-out period can refer TOC0 bit description.
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368 * @var PDMA_T::CHRST
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369 * Offset: 0x460 PDMA Channel Reset Control Register
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370 * ---------------------------------------------------------------------------------------------------
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371 * |Bits |Field |Descriptions
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372 * | :----: | :----: | :---- |
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373 * |[15:0] |CHnRST |Channel N Reset
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374 * | | |0 = corresponding channel n not reset.
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375 * | | |1 = corresponding channel n is reset.
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376 * @var PDMA_T::REQSEL0_3
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377 * Offset: 0x480 PDMA Channel 0 to Channel 3 Request Source Select Register
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378 * ---------------------------------------------------------------------------------------------------
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379 * |Bits |Field |Descriptions
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380 * | :----: | :----: | :---- |
\r
381 * |[6:0] |REQSRC0 |Channel 0 Request Source Selection
\r
382 * | | |This filed defines which peripheral is connected to PDMA channel 0
\r
383 * | | |User can configure the peripheral by setting REQSRC0.
\r
384 * | | |0 = Disable PDMA.
\r
385 * | | |1 = Reserved.
\r
386 * | | |2 = Channel connects to USB_TX.
\r
387 * | | |3 = Channel connects to USB_RX.
\r
388 * | | |4 = Channel connects to UART0_TX.
\r
389 * | | |5 = Channel connects to UART0_RX.
\r
390 * | | |6 = Channel connects to UART1_TX.
\r
391 * | | |7 = Channel connects to UART1_RX.
\r
392 * | | |8 = Channel connects to UART2_TX.
\r
393 * | | |9 = Channel connects to UART2_RX.
\r
394 * | | |10 = Channel connects to UART3_TX.
\r
395 * | | |11 = Channel connects to UART3_RX.
\r
396 * | | |12 = Channel connects to UART4_TX.
\r
397 * | | |13 = Channel connects to UART4_RX.
\r
398 * | | |14 = Channel connects to UART5_TX.
\r
399 * | | |15 = Channel connects to UART5_RX.
\r
400 * | | |16 = Channel connects to USCI0_TX.
\r
401 * | | |17 = Channel connects to USCI0_RX.
\r
402 * | | |18 = Channel connects to USCI1_TX.
\r
403 * | | |19 = Channel connects to USCI1_RX.
\r
404 * | | |20 = Channel connects to QSPI0_TX.
\r
405 * | | |21 = Channel connects to QSPI0_RX.
\r
406 * | | |22 = Channel connects to SPI0_TX.
\r
407 * | | |23 = Channel connects to SPI0_RX.
\r
408 * | | |24 = Channel connects to SPI1_TX.
\r
409 * | | |25 = Channel connects to SPI1_RX.
\r
410 * | | |26 = Channel connects to SPI2_TX.
\r
411 * | | |27 = Channel connects to SPI2_RX.
\r
412 * | | |28 = Channel connects to SPI3_TX.
\r
413 * | | |29 = Channel connects to SPI3_RX.
\r
414 * | | |32 = Channel connects to EPWM0_P1_RX.
\r
415 * | | |33 = Channel connects to EPWM0_P2_RX.
\r
416 * | | |34 = Channel connects to EPWM0_P3_RX.
\r
417 * | | |35 = Channel connects to EPWM1_P1_RX.
\r
418 * | | |36 = Channel connects to EPWM1_P2_RX.
\r
419 * | | |37 = Channel connects to EPWM1_P3_RX.
\r
420 * | | |38 = Channel connects to I2C0_TX.
\r
421 * | | |39 = Channel connects to I2C0_RX.
\r
422 * | | |40 = Channel connects to I2C1_TX.
\r
423 * | | |41 = Channel connects to I2C1_RX.
\r
424 * | | |42 = Channel connects to I2C2_TX.
\r
425 * | | |43 = Channel connects to I2C2_RX.
\r
426 * | | |44 = Channel connects to I2S0_TX.
\r
427 * | | |45 = Channel connects to I2S0_RX.
\r
428 * | | |46 = Channel connects to TMR0.
\r
429 * | | |47 = Channel connects to TMR1.
\r
430 * | | |48 = Channel connects to TMR2.
\r
431 * | | |49 = Channel connects to TMR3.
\r
432 * | | |50 = Channel connects to ADC_RX.
\r
433 * | | |51 = Channel connects to DAC0_TX.
\r
434 * | | |52 = Channel connects to DAC1_TX.
\r
435 * | | |53 = Channel connects to EPWM0_CH0_TX.
\r
436 * | | |54 = Channel connects to EPWM0_CH1_TX.
\r
437 * | | |55 = Channel connects to EPWM0_CH2_TX.
\r
438 * | | |56 = Channel connects to EPWM0_CH3_TX.
\r
439 * | | |57 = Channel connects to EPWM0_CH4_TX.
\r
440 * | | |58 = Channel connects to EPWM0_CH5_TX.
\r
441 * | | |59 = Channel connects to EPWM1_CH0_TX.
\r
442 * | | |60 = Channel connects to EPWM1_CH1_TX.
\r
443 * | | |61 = Channel connects to EPWM1_CH2_TX.
\r
444 * | | |62 = Channel connects to EPWM1_CH3_TX.
\r
445 * | | |63 = Channel connects to EPWM1_CH4_TX.
\r
446 * | | |64 = Channel connects to EPWM1_CH5_TX.
\r
447 * | | |Others = Reserved.
\r
448 * | | |Note 1: A request source cannot assign to two channels at the same time.
\r
449 * | | |Note 2: This field is useless when transfer between memory and memory.
\r
450 * |[14:8] |REQSRC1 |Channel 1 Request Source Selection
\r
451 * | | |This filed defines which peripheral is connected to PDMA channel 1
\r
452 * | | |User can configure the peripheral setting by REQSRC1.
\r
453 * | | |Note: The channel configuration is the same as REQSRC0 field
\r
454 * | | |Please refer to the explanation of REQSRC0.
\r
455 * |[22:16] |REQSRC2 |Channel 2 Request Source Selection
\r
456 * | | |This filed defines which peripheral is connected to PDMA channel 2
\r
457 * | | |User can configure the peripheral setting by REQSRC2.
\r
458 * | | |Note: The channel configuration is the same as REQSRC0 field
\r
459 * | | |Please refer to the explanation of REQSRC0.
\r
460 * |[30:24] |REQSRC3 |Channel 3 Request Source Selection
\r
461 * | | |This filed defines which peripheral is connected to PDMA channel 3
\r
462 * | | |User can configure the peripheral setting by REQSRC3.
\r
463 * | | |Note: The channel configuration is the same as REQSRC0 field
\r
464 * | | |Please refer to the explanation of REQSRC0.
\r
465 * @var PDMA_T::REQSEL4_7
\r
466 * Offset: 0x484 PDMA Request Source Select Register 1
\r
467 * ---------------------------------------------------------------------------------------------------
\r
468 * |Bits |Field |Descriptions
\r
469 * | :----: | :----: | :---- |
\r
470 * |[6:0] |REQSRC4 |Channel 4 Request Source Selection
\r
471 * | | |This filed defines which peripheral is connected to PDMA channel 4
\r
472 * | | |User can configure the peripheral setting by REQSRC4.
\r
473 * | | |Note: The channel configuration is the same as REQSRC0 field
\r
474 * | | |Please refer to the explanation of REQSRC0.
\r
475 * |[14:8] |REQSRC5 |Channel 5 Request Source Selection
\r
476 * | | |This filed defines which peripheral is connected to PDMA channel 5
\r
477 * | | |User can configure the peripheral setting by REQSRC5.
\r
478 * | | |Note: The channel configuration is the same as REQSRC0 field
\r
479 * | | |Please refer to the explanation of REQSRC0.
\r
480 * |[22:16] |REQSRC6 |Channel 6 Request Source Selection
\r
481 * | | |This filed defines which peripheral is connected to PDMA channel 6
\r
482 * | | |User can configure the peripheral setting by REQSRC6.
\r
483 * | | |Note: The channel configuration is the same as REQSRC0 field
\r
484 * | | |Please refer to the explanation of REQSRC0.
\r
485 * |[30:24] |REQSRC7 |Channel 7 Request Source Selection
\r
486 * | | |This filed defines which peripheral is connected to PDMA channel 7
\r
487 * | | |User can configure the peripheral setting by REQSRC7.
\r
488 * | | |Note: The channel configuration is the same as REQSRC0 field
\r
489 * | | |Please refer to the explanation of REQSRC0.
\r
492 DSCT_T DSCT[8]; /*!< [0x0000 ~ 0x007C] DMA Embedded Description Table 0~7 */
\r
493 __I uint32_t CURSCAT[8]; /*!< [0x0080~0x009C] Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 */
\r
494 __I uint32_t RESERVE0[216];
\r
495 __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */
\r
496 __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */
\r
497 __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */
\r
498 __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */
\r
499 __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */
\r
500 __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */
\r
501 __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */
\r
502 __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */
\r
503 __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */
\r
504 __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */
\r
505 __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */
\r
506 __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */
\r
507 __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */
\r
508 __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */
\r
509 __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */
\r
510 __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */
\r
511 __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Channel 0 and Channel 1 Time-out Counter Register */
\r
512 __I uint32_t RESERVE1[7];
\r
513 __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */
\r
514 __I uint32_t RESERVE2[7];
\r
515 __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Channel 0 to Channel 3 Request Source Select Register */
\r
516 __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Channel 4 to Channel 7 Request Source Select Register */
\r
517 __I uint32_t RESERVE4[30];
\r
518 STRIDE_T STRIDE[6]; /*!< [0x0500 ~ 0x052C] Stride function control register of PDMA Channel 0 ~ 5 */
\r
526 @addtogroup PDMA_CONST PDMA Bit Field Definition
\r
527 Constant Definitions for PDMA Controller
\r
530 #define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */
\r
531 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */
\r
533 #define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */
\r
534 #define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */
\r
536 #define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */
\r
537 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */
\r
539 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */
\r
540 #define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */
\r
542 #define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */
\r
543 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */
\r
545 #define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */
\r
546 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */
\r
548 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */
\r
549 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */
\r
551 #define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */
\r
552 #define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */
\r
554 #define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */
\r
555 #define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */
\r
557 #define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */
\r
558 #define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */
\r
560 #define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */
\r
561 #define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */
\r
563 #define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */
\r
564 #define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */
\r
566 #define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */
\r
567 #define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */
\r
569 #define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */
\r
570 #define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */
\r
572 #define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
\r
573 #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
\r
575 #define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
\r
576 #define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
\r
578 #define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */
\r
579 #define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */
\r
581 #define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
\r
582 #define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
\r
584 #define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
\r
585 #define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
\r
587 #define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
\r
588 #define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
\r
590 #define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
\r
591 #define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
\r
593 #define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
\r
594 #define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
\r
596 #define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
\r
597 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
\r
599 #define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
\r
600 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
\r
602 #define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */
\r
603 #define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */
\r
605 #define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */
\r
606 #define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */
\r
608 #define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */
\r
609 #define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */
\r
611 #define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */
\r
612 #define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */
\r
614 #define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */
\r
615 #define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */
\r
617 #define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */
\r
618 #define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */
\r
620 #define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */
\r
621 #define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */
\r
623 #define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */
\r
624 #define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */
\r
626 #define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */
\r
627 #define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */
\r
629 #define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */
\r
630 #define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */
\r
632 #define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */
\r
633 #define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */
\r
635 #define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */
\r
636 #define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */
\r
638 #define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */
\r
639 #define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */
\r
641 #define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */
\r
642 #define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */
\r
644 #define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */
\r
645 #define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */
\r
647 #define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */
\r
648 #define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */
\r
650 #define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */
\r
651 #define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */
\r
653 #define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */
\r
654 #define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */
\r
656 #define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */
\r
657 #define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */
\r
659 #define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */
\r
660 #define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */
\r
662 #define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */
\r
663 #define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */
\r
665 #define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */
\r
666 #define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */
\r
668 #define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */
\r
669 #define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */
\r
671 #define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */
\r
672 #define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */
\r
674 #define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */
\r
675 #define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */
\r
677 #define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */
\r
678 #define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */
\r
680 #define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */
\r
681 #define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */
\r
683 #define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */
\r
684 #define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */
\r
686 #define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */
\r
687 #define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */
\r
689 #define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */
\r
690 #define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */
\r
692 #define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */
\r
693 #define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */
\r
695 #define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */
\r
696 #define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */
\r
698 #define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */
\r
699 #define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */
\r
701 #define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */
\r
702 #define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */
\r
704 #define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */
\r
705 #define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */
\r
707 #define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */
\r
708 #define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */
\r
710 #define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
\r
711 #define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
\r
713 #define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */
\r
714 #define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */
\r
716 #define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */
\r
717 #define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */
\r
719 #define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
\r
720 #define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
\r
722 #define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
\r
723 #define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
\r
725 #define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
\r
726 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
\r
728 #define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
\r
729 #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
\r
731 #define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
\r
732 #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
\r
734 #define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */
\r
735 #define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */
\r
737 #define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
\r
738 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
\r
740 #define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
\r
741 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
\r
743 #define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
\r
744 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
\r
746 #define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
\r
747 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
\r
749 #define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
\r
750 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
\r
752 #define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
\r
753 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
\r
755 #define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
\r
756 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
\r
758 #define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
\r
759 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
\r
761 #define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */
\r
762 #define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */
\r
764 #define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */
\r
765 #define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */
\r
767 #define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */
\r
768 #define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */
\r
770 /**@}*/ /* PDMA_CONST */
\r
771 /**@}*/ /* end of PDMA register group */
\r
772 /**@}*/ /* end of REGISTER group */
\r
775 #endif /* __PDMA_REG_H__ */
\r
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