1 /**************************************************************************//**
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4 * @brief QEI register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __QEI_REG_H__
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9 #define __QEI_REG_H__
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11 /** @addtogroup REGISTER Control Register
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17 /*---------------------- Quadrature Encoder Interface -------------------------*/
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19 @addtogroup QEI Quadrature Encoder Interface(QEI)
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20 Memory Mapped Structure for QEI Controller
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29 * Offset: 0x00 QEI Counter Register
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30 * ---------------------------------------------------------------------------------------------------
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31 * |Bits |Field |Descriptions
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32 * | :----: | :----: | :---- |
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33 * |[31:0] |CNT |Quadrature Encoder Interface Counter
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34 * | | |A 32-bit up/down counter
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35 * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero
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36 * | | |This register performs an integrator which count value is proportional to the encoder position
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37 * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:
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38 * | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0.
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39 * | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode.
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40 * | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTL[27])=1.
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41 * @var QEI_T::CNTHOLD
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42 * Offset: 0x04 QEI Counter Hold Register
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43 * ---------------------------------------------------------------------------------------------------
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44 * |Bits |Field |Descriptions
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45 * | :----: | :----: | :---- |
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46 * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold
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47 * | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
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48 * @var QEI_T::CNTLATCH
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49 * Offset: 0x08 QEI Counter Index Latch Register
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50 * ---------------------------------------------------------------------------------------------------
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51 * |Bits |Field |Descriptions
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52 * | :----: | :----: | :---- |
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53 * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch
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54 * | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
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55 * @var QEI_T::CNTCMP
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56 * Offset: 0x0C QEI Counter Compare Register
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57 * ---------------------------------------------------------------------------------------------------
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58 * |Bits |Field |Descriptions
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59 * | :----: | :----: | :---- |
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60 * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare
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61 * | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set
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62 * | | |This register is software writable.
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63 * @var QEI_T::CNTMAX
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64 * Offset: 0x14 QEI Pre-set Maximum Count Register
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65 * ---------------------------------------------------------------------------------------------------
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66 * |Bits |Field |Descriptions
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67 * | :----: | :----: | :---- |
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68 * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count
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69 * | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode
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71 * Offset: 0x18 QEI Controller Control Register
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72 * ---------------------------------------------------------------------------------------------------
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73 * |Bits |Field |Descriptions
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74 * | :----: | :----: | :---- |
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75 * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
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76 * | | |To determine the sampling frequency of the Noise Filter clock .
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77 * | | |000 = QEI_CLK.
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78 * | | |001 = QEI_CLK/2.
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79 * | | |010 = QEI_CLK/4.
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80 * | | |011 = QEI_CLK/16.
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81 * | | |100 = QEI_CLK/32.
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82 * | | |101 = QEI_CLK/64.
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83 * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit
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84 * | | |0 = The noise filter of QEI controller Enabled.
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85 * | | |1 = The noise filter of QEI controller Disabled.
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86 * |[4] |CHAEN |QEA Input to QEI Controller Enable Bit
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87 * | | |0 = QEA input to QEI Controller Disabled.
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88 * | | |1 = QEA input to QEI Controller Enabled.
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89 * |[5] |CHBEN |QEB Input to QEI Controller Enable Bit
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90 * | | |0 = QEB input to QEI Controller Disabled.
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91 * | | |1 = QEB input to QEI Controller Enabled.
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92 * |[6] |IDXEN |IDX Input to QEI Controller Enable Bit
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93 * | | |0 = IDX input to QEI Controller Disabled.
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94 * | | |1 = IDX input to QEI Controller Enabled.
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95 * |[9:8] |MODE |QEI Counting Mode Selection
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96 * | | |There are four quadrature encoder pulse counter operation modes.
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97 * | | |00 = X4 Free-counting Mode.
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98 * | | |01 = X2 Free-counting Mode.
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99 * | | |10 = X4 Compare-counting Mode.
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100 * | | |11 = X2 Compare-counting Mode.
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101 * |[12] |CHAINV |Inverse QEA Input Polarity
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102 * | | |0 = Not inverse QEA input polarity.
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103 * | | |1 = QEA input polarity is inverse to QEI controller.
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104 * |[13] |CHBINV |Inverse QEB Input Polarity
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105 * | | |0 = Not inverse QEB input polarity.
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106 * | | |1 = QEB input polarity is inverse to QEI controller.
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107 * |[14] |IDXINV |Inverse IDX Input Polarity
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108 * | | |0 = Not inverse IDX input polarity.
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109 * | | |1 = IDX input polarity is inverse to QEI controller.
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110 * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit
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111 * | | |0 = OVUNF can trigger QEI controller interrupt Disabled.
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112 * | | |1 = OVUNF can trigger QEI controller interrupt Enabled.
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113 * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit
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114 * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
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115 * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
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116 * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit
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117 * | | |0 = CMPF can trigger QEI controller interrupt Disabled.
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118 * | | |1 = CMPF can trigger QEI controller interrupt Enabled.
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119 * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit
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120 * | | |0 = The IDXF can trigger QEI interrupt Disabled.
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121 * | | |1 = The IDXF can trigger QEI interrupt Enabled.
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122 * |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0
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123 * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
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124 * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
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125 * |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1
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126 * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
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127 * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
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128 * |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2
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129 * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
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130 * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
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131 * |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3
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132 * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
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133 * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
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134 * |[24] |HOLDCNT |Hold QEI_CNT Control
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135 * | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into QEI_CNTHOLD
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136 * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
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137 * | | |0 = No operation.
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138 * | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD.
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139 * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
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140 * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit
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141 * | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.
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142 * | | |0 = The index signal latch QEI counter function Disabled.
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143 * | | |1 = The index signal latch QEI counter function Enabled.
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144 * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit
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145 * | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF = 0).
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146 * | | |0 = Reload function Disabled.
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147 * | | |1 = QEI_CNT re-initialized by Index signal Enabled.
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148 * |[28] |CMPEN |the Compare Function Enable Bit
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149 * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
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150 * | | |0 = Compare function Disabled.
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151 * | | |1 = Compare function Enabled.
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152 * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit
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153 * | | |0 = QEI controller function Disabled.
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154 * | | |1 = QEI controller function Enabled.
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155 * @var QEI_T::STATUS
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156 * Offset: 0x2C QEI Controller Status Register
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157 * ---------------------------------------------------------------------------------------------------
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158 * |Bits |Field |Descriptions
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159 * | :----: | :----: | :---- |
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160 * |[0] |IDXF |IDX Detected Flag
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161 * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
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162 * | | |0 = No rising edge detected on signal CHX.
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163 * | | |1 = A rising edge occurs on signal CHX.
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164 * | | |Note: This bit is only cleared by writing 1 to it.
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165 * |[1] |CMPF |Compare-match Flag
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166 * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).
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167 * | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).
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168 * | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).
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169 * | | |Note: This bit is only cleared by writing 1 to it.
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170 * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag
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171 * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode
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172 * | | |Similarly, the flag is set wile QEI counter underflow from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).
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173 * | | |0 = No overflow or underflow occurs in QEI counter.
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174 * | | |1 = QEI counter occurs counting overflow or underflow.
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175 * | | |Note: This bit is only cleared by writing 1 to it.
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176 * |[3] |DIRCHGF |Direction Change Flag
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177 * | | |Flag is set by hardware while QEI counter counting direction is changed
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178 * | | |Software can clear this bit by writing 1 to it.
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179 * | | |0 = No change in QEI counter counting direction.
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180 * | | |1 = QEI counter counting direction is changed.
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181 * | | |Note: This bit is only cleared by writing 1 to it.
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182 * |[8] |DIRF |QEI Counter Counting Direction Indication
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183 * | | |0 = QEI Counter is in down-counting.
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184 * | | |1 = QEI Counter is in up-counting.
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185 * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
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187 __IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */
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188 __IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */
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189 __IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */
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190 __IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */
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191 __I uint32_t RESERVE0[1];
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192 __IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */
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193 __IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */
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194 __I uint32_t RESERVE1[4];
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195 __IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */
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200 @addtogroup QEI_CONST QEI Bit Field Definition
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201 Constant Definitions for QEI Controller
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204 #define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */
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205 #define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */
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207 #define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */
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208 #define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */
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210 #define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */
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211 #define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */
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213 #define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */
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214 #define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */
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216 #define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */
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217 #define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */
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219 #define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */
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220 #define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */
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222 #define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */
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223 #define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */
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225 #define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */
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226 #define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */
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228 #define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */
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229 #define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */
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231 #define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */
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232 #define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */
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234 #define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */
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235 #define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */
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237 #define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */
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238 #define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */
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240 #define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */
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241 #define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */
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243 #define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */
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244 #define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */
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246 #define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */
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247 #define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */
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249 #define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */
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250 #define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */
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252 #define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */
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253 #define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */
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255 #define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */
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256 #define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */
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258 #define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */
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259 #define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */
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261 #define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */
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262 #define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */
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264 #define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */
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265 #define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */
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267 #define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */
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268 #define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */
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270 #define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */
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271 #define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */
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273 #define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */
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274 #define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */
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276 #define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */
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277 #define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */
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279 #define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */
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280 #define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */
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282 #define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */
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283 #define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */
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285 #define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */
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286 #define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */
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288 #define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */
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289 #define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */
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291 #define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */
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292 #define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */
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294 #define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */
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295 #define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */
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297 #define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */
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298 #define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */
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300 /**@}*/ /* QEI_CONST */
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301 /**@}*/ /* end of QEI register group */
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302 /**@}*/ /* end of REGISTER group */
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305 #endif /* __QEI_REG_H__ */
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