1 /**************************************************************************//**
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4 * @brief RTC register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __RTC_REG_H__
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9 #define __RTC_REG_H__
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11 /** @addtogroup REGISTER Control Register
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17 /*---------------------- Real Time Clock Controller -------------------------*/
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19 @addtogroup RTC Real Time Clock Controller(RTC)
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20 Memory Mapped Structure for RTC Controller
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29 * Offset: 0x00 RTC Initiation Register
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30 * ---------------------------------------------------------------------------------------------------
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31 * |Bits |Field |Descriptions
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32 * | :----: | :----: | :---- |
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33 * |[0] |INIT_ACTIVE|RTC Active Status (Read Only)
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34 * | | |0 = RTC is at reset state.
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35 * | | |1 = RTC is at normal active state.
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36 * |[31:1] |INIT |RTC Initiation
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37 * | | |When RTC block is powered on, RTC is at reset state
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38 * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state
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39 * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
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40 * | | |The INIT is a write-only field and read value will be always 0.
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42 * Offset: 0x04 RTC Access Enable Register
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43 * ---------------------------------------------------------------------------------------------------
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44 * |Bits |Field |Descriptions
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45 * | :----: | :----: | :---- |
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46 * |[15:0] |RWEN |RTC Register Access Enable Password (Write Only)
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47 * | | |Writing 0xA965 to this field will enable RTC accessible period keeps 1024 RTC clocks.
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48 * | | |Note: Writing other value will clear RWENF and disable RTC register access function immediately.
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49 * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
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50 * | | |0 = RTC register read/write Disabled.
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51 * | | |1 = RTC register read/write Enabled.
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52 * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clocks expired.
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53 * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
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54 * |[24] |RTCBUSY |RTC Write Busy Flag
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55 * | | |This bit indicates RTC registers are busy or not. RTC register R/W is invalid during RTCBUSY.
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56 * | | |0: RTC registers are readable and writable.
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57 * | | |1: RTC registers can't R/W, RTC under Busy Status.
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58 * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles or PCLKRTC switch on first few cycles.
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59 * | | |Note: The bit reflect RWENF (RWENF = 0 when RTCBUSY).
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60 * @var RTC_T::FREQADJ
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61 * Offset: 0x08 RTC Frequency Compensation Register
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62 * ---------------------------------------------------------------------------------------------------
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63 * |Bits |Field |Descriptions
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64 * | :----: | :----: | :---- |
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65 * |[21:0] |FREQADJ |Frequency Compensation Register
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66 * | | |User must to get actual LXT frequency for RTC application.
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67 * | | |FCR = 0x200000 * (32768 / LXT frequency).
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68 * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0.
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69 * | | |If set RTCSEL (CLK_CLKSEL3[8]) to 1, RTC clock source is from LIRC.
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70 * | | |User can set FREQADJ to execute LIRC compensation for RTC counter more accurate and the formula as below,
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71 * | | |FCR = 0x80000 * (32768 / LIRC frequency).
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73 * Offset: 0x0C RTC Time Loading Register
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74 * ---------------------------------------------------------------------------------------------------
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75 * |Bits |Field |Descriptions
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76 * | :----: | :----: | :---- |
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77 * |[3:0] |SEC |1-Sec Time Digit (0~9)
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78 * |[6:4] |TENSEC |10-Sec Time Digit (0~5)
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79 * |[11:8] |MIN |1-Min Time Digit (0~9)
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80 * |[14:12] |TENMIN |10-Min Time Digit (0~5)
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81 * |[19:16] |HR |1-Hour Time Digit (0~9)
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82 * |[21:20] |TENHR |10-Hour Time Digit (0~2)
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83 * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
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84 * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)
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86 * Offset: 0x10 RTC Calendar Loading Register
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87 * ---------------------------------------------------------------------------------------------------
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88 * |Bits |Field |Descriptions
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89 * | :----: | :----: | :---- |
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90 * |[3:0] |DAY |1-Day Calendar Digit (0~9)
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91 * |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
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92 * |[11:8] |MON |1-Month Calendar Digit (0~9)
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93 * |[12] |TENMON |10-Month Calendar Digit (0~1)
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94 * |[19:16] |YEAR |1-Year Calendar Digit (0~9)
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95 * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
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96 * @var RTC_T::CLKFMT
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97 * Offset: 0x14 RTC Time Scale Selection Register
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98 * ---------------------------------------------------------------------------------------------------
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99 * |Bits |Field |Descriptions
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100 * | :----: | :----: | :---- |
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101 * |[0] |24HEN |24-hour / 12-hour Time Scale Selection
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102 * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
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103 * | | |0 = 12-hour time scale with AM and PM indication selected.
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104 * | | |1 = 24-hour time scale selected.
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105 * |[8] |HZCNTEN |Sub-second Counter Enable Bit
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106 * | | |0 = HZCNT disabled in RTC_TIME and RTC_TALM.
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107 * | | |1 = HZCNT enabled in RTC_TIME and RTC_TALM .
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108 * @var RTC_T::WEEKDAY
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109 * Offset: 0x18 RTC Day of the Week Register
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110 * ---------------------------------------------------------------------------------------------------
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111 * |Bits |Field |Descriptions
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112 * | :----: | :----: | :---- |
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113 * |[2:0] |WEEKDAY |Day of the Week Register
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114 * | | |000 = Sunday.
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115 * | | |001 = Monday.
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116 * | | |010 = Tuesday.
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117 * | | |011 = Wednesday.
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118 * | | |100 = Thursday.
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119 * | | |101 = Friday.
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120 * | | |110 = Saturday.
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121 * | | |111 = Reserved.
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123 * Offset: 0x1C RTC Time Alarm Register
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124 * ---------------------------------------------------------------------------------------------------
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125 * |Bits |Field |Descriptions
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126 * | :----: | :----: | :---- |
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127 * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
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128 * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
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129 * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
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130 * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
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131 * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
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132 * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
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133 * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
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134 * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)
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136 * Offset: 0x20 RTC Calendar Alarm Register
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137 * ---------------------------------------------------------------------------------------------------
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138 * |Bits |Field |Descriptions
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139 * | :----: | :----: | :---- |
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140 * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
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141 * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
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142 * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
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143 * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
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144 * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
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145 * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
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146 * @var RTC_T::LEAPYEAR
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147 * Offset: 0x24 RTC Leap Year Indicator Register
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148 * ---------------------------------------------------------------------------------------------------
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149 * |Bits |Field |Descriptions
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150 * | :----: | :----: | :---- |
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151 * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
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152 * | | |0 = This year is not a leap year.
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153 * | | |1 = This year is leap year.
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154 * @var RTC_T::INTEN
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155 * Offset: 0x28 RTC Interrupt Enable Register
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156 * ---------------------------------------------------------------------------------------------------
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157 * |Bits |Field |Descriptions
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158 * | :----: | :----: | :---- |
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159 * |[0] |ALMIEN |Alarm Interrupt Enable Bit
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160 * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
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161 * | | |0 = RTC Alarm interrupt Disabled.
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162 * | | |1 = RTC Alarm interrupt Enabled.
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163 * |[1] |TICKIEN |Time Tick Interrupt Enable Bit
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164 * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
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165 * | | |0 = RTC Time Tick interrupt Disabled.
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166 * | | |1 = RTC Time Tick interrupt Enabled.
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167 * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit
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168 * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
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169 * | | |0 = Tamper 0 interrupt Disabled.
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170 * | | |1 = Tamper 0 interrupt Enabled.
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171 * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit
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172 * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.
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173 * | | |0 = Tamper 1 or Pair 0 interrupt Disabled.
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174 * | | |1 = Tamper 1 or Pair 0 interrupt Enabled.
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175 * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit
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176 * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.
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177 * | | |0 = Tamper 2 interrupt Disabled.
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178 * | | |1 = Tamper 2 interrupt Enabled.
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179 * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit
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180 * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.
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181 * | | |0 = Tamper 3 or Pair 1 interrupt Disabled.
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182 * | | |1 = Tamper 3 or Pair 1 interrupt Enabled.
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183 * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit
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184 * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.
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185 * | | |0 = Tamper 4 interrupt Disabled.
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186 * | | |1 = Tamper 4 interrupt Enabled.
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187 * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit
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188 * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.
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189 * | | |0 = Tamper 5 or Pair 2 interrupt Disabled.
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190 * | | |1 = Tamper 5 or Pair 2 interrupt Enabled.
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191 * |[24] |CLKFIEN |LXT Clock Frequency Monitor Fail Interrupt Enable Bit
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192 * | | |0 = LXT Frequency Fail interrupt Disabled.
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193 * | | |1 = LXT Frequency Fail interrupt Enabled.
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194 * |[25] |CLKSPIEN |LXT Clock Frequency Monitor Stop Interrupt Enable Bit
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195 * | | |0 = LXT Frequency Stop interrupt Disabled.
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196 * | | |1 = LXT Frequency Stop interrupt Enabled.
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197 * @var RTC_T::INTSTS
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198 * Offset: 0x2C RTC Interrupt Status Register
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199 * ---------------------------------------------------------------------------------------------------
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200 * |Bits |Field |Descriptions
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201 * | :----: | :----: | :---- |
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202 * |[0] |ALMIF |RTC Alarm Interrupt Flag
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203 * | | |0 = Alarm condition is not matched.
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204 * | | |1 = Alarm condition is matched.
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205 * | | |Note: Write 1 to clear this bit.
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206 * |[1] |TICKIF |RTC Time Tick Interrupt Flag
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207 * | | |0 = Tick condition does not occur.
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208 * | | |1 = Tick condition occur.
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209 * | | |Note: Write 1 to clear this bit.
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210 * |[8] |TAMP0IF |Tamper 0 Interrupt Flag
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211 * | | |0 = No Tamper 0 interrupt flag is generated.
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212 * | | |1 = Tamper 0 interrupt flag is generated.
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213 * | | |Note1: Write 1 to clear this bit.
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214 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
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215 * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag
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216 * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated.
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217 * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated.
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218 * | | |Note1: Write 1 to clear this bit.
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219 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
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220 * |[10] |TAMP2IF |Tamper 2 Interrupt Flag
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221 * | | |0 = No Tamper 2 interrupt flag is generated.
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222 * | | |1 = Tamper 2 interrupt flag is generated.
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223 * | | |Note1: Write 1 to clear this bit.
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224 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
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225 * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag
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226 * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated.
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227 * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated.
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228 * | | |Note1: Write 1 to clear this bit.
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229 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
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230 * |[12] |TAMP4IF |Tamper 4 Interrupt Flag
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231 * | | |0 = No Tamper 4 interrupt flag is generated.
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232 * | | |1 = Tamper 4 interrupt flag is generated.
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233 * | | |Note1: Write 1 to clear this bit.
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234 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
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235 * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag
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236 * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated.
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237 * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated.
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238 * | | |Note1: Write 1 to clear this bit.
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239 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
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240 * |[24] |CLKFIF |LXT Clock Frequency Monitor Fail Interrupt Flag
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241 * | | |0 = LXT frequency is normal.
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242 * | | |1 = LXT frequency is abnormal.
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243 * | | |Note1: Write 1 to clear the bit to 0.
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244 * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear.
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245 * |[25] |CLKSPIF |LXT Clock Frequency Monitor Stop Interrupt Flag
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246 * | | |0 = LXT frequency is normal.
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247 * | | |1 = LXT frequency is almost stop ..
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248 * | | |Note1: Write 1 to clear the bit to 0.
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249 * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear.
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251 * Offset: 0x30 RTC Time Tick Register
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252 * ---------------------------------------------------------------------------------------------------
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253 * |Bits |Field |Descriptions
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254 * | :----: | :----: | :---- |
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255 * |[2:0] |TICK |Time Tick Register
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256 * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
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257 * | | |000 = Time tick is 1 second.
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258 * | | |001 = Time tick is 1/2 second.
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259 * | | |010 = Time tick is 1/4 second.
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260 * | | |011 = Time tick is 1/8 second.
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261 * | | |100 = Time tick is 1/16 second.
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262 * | | |101 = Time tick is 1/32 second.
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263 * | | |110 = Time tick is 1/64 second.
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264 * | | |111 = Time tick is 1/128 second.
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265 * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
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266 * @var RTC_T::TAMSK
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267 * Offset: 0x34 RTC Time Alarm Mask Register
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268 * ---------------------------------------------------------------------------------------------------
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269 * |Bits |Field |Descriptions
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270 * | :----: | :----: | :---- |
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271 * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
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272 * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
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273 * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
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274 * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
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275 * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
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276 * | | |Note: MHR function is only for 24-hour time scale mode.
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277 * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
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278 * | | |Note: MTENHR function is only for 24-hour time scale mode.
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279 * @var RTC_T::CAMSK
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280 * Offset: 0x38 RTC Calendar Alarm Mask Register
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281 * ---------------------------------------------------------------------------------------------------
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282 * |Bits |Field |Descriptions
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283 * | :----: | :----: | :---- |
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284 * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
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285 * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
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286 * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
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287 * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
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288 * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
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289 * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
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290 * @var RTC_T::SPRCTL
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291 * Offset: 0x3C RTC Spare Functional Control Register
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292 * ---------------------------------------------------------------------------------------------------
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293 * |Bits |Field |Descriptions
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294 * | :----: | :----: | :---- |
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295 * |[2] |SPRRWEN |Spare Register Enable Bit
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296 * | | |0 = Spare register is Disabled.
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297 * | | |1 = Spare register is Enabled.
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298 * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
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299 * |[5] |SPRCSTS |SPR Clear Flag
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300 * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.
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301 * | | |0 = Spare register content is not cleared.
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302 * | | |1 = Spare register content is cleared.
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303 * | | |Writes 1 to clear this bit.
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304 * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] or RTC_INTSTS[25:24] are not equal zero.
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305 * |[16] |LXTFCLR |LXT Clock Monitor Fail/Stop to Clear Spare Enable Bit
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306 * | | |0 = LXT monitor Fail/Stop to clear Spare register content is Disabled..
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307 * | | |1 = LXT monitor Fail/Stop to clear Spare register content is Enabled.
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308 * @var RTC_T::SPR[20]
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309 * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
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310 * ---------------------------------------------------------------------------------------------------
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311 * |Bits |Field |Descriptions
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312 * | :----: | :----: | :---- |
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313 * |[31:0] |SPARE |Spare Register
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314 * | | |This field is used to store back-up information defined by user.
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315 * | | |This field will be cleared by hardware automatically once a tamper pin event is detected.
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316 * | | |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
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317 * @var RTC_T::LXTCTL
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318 * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
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319 * ---------------------------------------------------------------------------------------------------
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320 * |Bits |Field |Descriptions
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321 * | :----: | :----: | :---- |
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322 * |[0] |LIRC32KEN |LIRC 32K Source Enable Bit
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323 * | | |0 = LIRC32K Disabled.
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324 * | | |1 = LIRC32K.Enabled.
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325 * |[3:1] |GAIN |Oscillator Gain Option
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326 * | | |User can select oscillator gain according to crystal external loading and operating temperature range
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327 * | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
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328 * | | |000 = L0 mode.
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329 * | | |001 = L1 mode.
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330 * | | |010 = L2 mode.
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331 * | | |011 = L3 mode.
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332 * | | |100 = L4 mode.
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333 * | | |101 = L5 mode.
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334 * | | |110 = L6 mode.
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335 * | | |111 = L7 mode (Default).
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336 * |[7] |C32KS |Clock 32K Source Selection:
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337 * | | |0 = Internal 32K clock is from 32K crystal .
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338 * | | |1 = Internal 32K clock is from LIRC32K.
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339 * @var RTC_T::GPIOCTL0
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340 * Offset: 0x104 RTC GPIO Control 0 Register
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341 * ---------------------------------------------------------------------------------------------------
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342 * |Bits |Field |Descriptions
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343 * | :----: | :----: | :---- |
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344 * |[1:0] |OPMODE0 |IO Operation Mode
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345 * | | |00 = PF.0 is input only mode, without pull-up resistor.
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346 * | | |01 = PF.0 is output push pull mode.
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347 * | | |10 = PF.0 is open drain mode.
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348 * | | |11 = PF.0 is quasi-bidirectional mode with internal pull up.
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349 * |[2] |DOUT0 |IO Output Data
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350 * | | |0 = PF.0 output low.
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351 * | | |1 = PF.0 output high.
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352 * |[3] |CTLSEL0 |IO Pin State Backup Selection
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353 * | | |When low speed 32 kHz oscillator is disabled, PF.0 pin (X32KO pin) can be used as GPIO function
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354 * | | |User can program CTLSEL0 to decide PF.0 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.
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355 * | | |0 = PF.0 pin I/O function is controlled by GPIO module.
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356 * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off.
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357 * | | |1 = PF.0 pin I/O function is controlled by VBAT power domain.
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358 * | | |PF.0 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.
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359 * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
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360 * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bit
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361 * | | |Determine PF.0 I/O pull-up or pull-down.
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362 * | | |00 = PF.0 pull-up and pull-up disable.
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363 * | | |01 = PF.0 pull-down enable.
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364 * | | |10 = PF.0 pull-up enable.
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365 * | | |11 = PF.0 pull-up and pull-up disable.
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367 * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
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368 * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode.
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369 * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode.
\r
370 * |[9:8] |OPMODE1 |IO Operation Mode
\r
371 * | | |00 = PF.1 is input only mode, without pull-up resistor.
\r
372 * | | |01 = PF.1 is output push pull mode.
\r
373 * | | |10 = PF.1 is open drain mode.
\r
374 * | | |11 = PF.1 is quasi-bidirectional mode with internal pull up.
\r
375 * |[10] |DOUT1 |IO Output Data
\r
376 * | | |0 = PF.1 output low.
\r
377 * | | |1 = PF.1 output high.
\r
378 * |[11] |CTLSEL1 |IO Pin State Backup Selection
\r
379 * | | |When low speed 32 kHz oscillator is disabled, PF.1 pin (X32KI pin) can be used as GPIO function
\r
380 * | | |User can program CTLSEL1 to decide PF.1 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.
\r
381 * | | |0 = PF.1 pin I/O function is controlled by GPIO module.
\r
382 * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off.
\r
383 * | | |1 = PF.1 pin I/O function is controlled by VBAT power domain.
\r
384 * | | |PF.1 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.
\r
385 * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
\r
386 * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bit
\r
387 * | | |Determine PF.1 I/O pull-up or pull-down.
\r
388 * | | |00 = PF.1 pull-up and pull-up disable.
\r
389 * | | |01 = PF.1 pull-down enable.
\r
390 * | | |10 = PF.1 pull-up enable.
\r
391 * | | |11 = PF.1 pull-up and pull-up disable.
\r
393 * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
\r
394 * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode.
\r
395 * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode.
\r
396 * |[17:16] |OPMODE2 |IO Operation Mode
\r
397 * | | |00 = PF.2 is input only mode, without pull-up resistor.
\r
398 * | | |01 = PF.2 is output push pull mode.
\r
399 * | | |10 = PF.2 is open drain mode.
\r
400 * | | |11 = PF.2 is quasi-bidirectional mode with internal pull up.
\r
401 * |[18] |DOUT2 |IO Output Data
\r
402 * | | |0 = PF.2 output low.
\r
403 * | | |1 = PF.2 output high.
\r
404 * |[19] |CTLSEL2 |IO Pin State Backup Selection
\r
405 * | | |When TAMP0EN is disabled, PF.2 pin (TAMPER0 pin) can be used as GPIO function
\r
406 * | | |User can program CTLSEL2 to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.
\r
407 * | | |0 = PF.2 pin I/O function is controlled by GPIO module.
\r
408 * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off.
\r
409 * | | |1 = PF.2 pin I/O function is controlled by VBAT power domain.
\r
410 * | | |PF.2 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.
\r
411 * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
\r
412 * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bit
\r
413 * | | |Determine PF.2 I/O pull-up or pull-down.
\r
414 * | | |00 = PF.2 pull-up and pull-up disable.
\r
415 * | | |01 = PF.2 pull-down enable.
\r
416 * | | |10 = PF.2 pull-up enable.
\r
417 * | | |11 = PF.2 pull-up and pull-up disable.
\r
419 * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
\r
420 * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode.
\r
421 * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode.
\r
422 * |[25:24] |OPMODE3 |IO Operation Mode
\r
423 * | | |00 = PF.7 is input only mode, without pull-up resistor.
\r
424 * | | |01 = PF.7 is output push pull mode.
\r
425 * | | |10 = PF.7 is open drain mode.
\r
426 * | | |11 = PF.7 is quasi-bidirectional mode with with internal pull up.
\r
427 * |[26] |DOUT3 |IO Output Data
\r
428 * | | |0 = PF.7 output low.
\r
429 * | | |1 = PF.7 output high.
\r
430 * |[27] |CTLSEL3 |IO Pin State Backup Selection
\r
431 * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function
\r
432 * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.
\r
433 * | | |0 = PF.7 pin I/O function is controlled by GPIO module.
\r
434 * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off.
\r
435 * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain.
\r
436 * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1.
\r
437 * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
\r
438 * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable Bit
\r
439 * | | |Determine PF.7 I/O pull-up or pull-down.
\r
440 * | | |00 = PF.7 pull-up and pull-down disable.
\r
441 * | | |01 = PF.7 pull-down enable.
\r
442 * | | |10 = PF.7 pull-up enable.
\r
443 * | | |11 = PF.7 pull-up and pull-down disable.
\r
445 * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
\r
446 * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode.
\r
447 * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode.
\r
448 * @var RTC_T::GPIOCTL1
\r
449 * Offset: 0x108 RTC GPIO Control 1 Register
\r
450 * ---------------------------------------------------------------------------------------------------
\r
451 * |Bits |Field |Descriptions
\r
452 * | :----: | :----: | :---- |
\r
453 * |[1:0] |OPMODE4 |IO Operation Mode
\r
454 * | | |00 = PF.8 is input only mode, without pull-up resistor.
\r
455 * | | |01 = PF.8 is output push pull mode.
\r
456 * | | |10 = PF.8 is open drain mode.
\r
457 * | | |11 = PF.8 is quasi-bidirectional mode with with internal pull up.
\r
458 * |[2] |DOUT4 |IO Output Data
\r
459 * | | |0 = PF.8 output low.
\r
460 * | | |1 = PF.8 output high.
\r
461 * |[3] |CTLSEL4 |IO Pin State Backup Selection
\r
462 * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function
\r
463 * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.
\r
464 * | | |0 = PF.8 pin I/O function is controlled by GPIO module.
\r
465 * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off.
\r
466 * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain.
\r
467 * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1.
\r
468 * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
\r
469 * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable Bit
\r
470 * | | |Determine PF.8 I/O pull-up or pull-down.
\r
471 * | | |00 = PF.8 pull-up and pull-down disable.
\r
472 * | | |01 = PF.8 pull-down enable.
\r
473 * | | |10 = PF.8 pull-up enable.
\r
474 * | | |11 = PF.8 pull-up and pull-down disable.
\r
476 * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
\r
477 * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode.
\r
478 * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode.
\r
479 * |[9:8] |OPMODE5 |IO Operation Mode
\r
480 * | | |00 = PF.9 is input only mode, without pull-up resistor.
\r
481 * | | |01 = PF.9 is output push pull mode.
\r
482 * | | |10 = PF.9 is open drain mode.
\r
483 * | | |11 = PF.9 is quasi-bidirectional mode with with internal pull up.
\r
484 * |[10] |DOUT5 |IO Output Data
\r
485 * | | |0 = PF.9 output low.
\r
486 * | | |1 = PF.9 output high.
\r
487 * |[11] |CTLSEL5 |IO Pin State Backup Selection
\r
488 * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function
\r
489 * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.
\r
490 * | | |0 = PF.9 pin I/O function is controlled by GPIO module.
\r
491 * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off.
\r
492 * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain.
\r
493 * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1.
\r
494 * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
\r
495 * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable Bit
\r
496 * | | |Determine PF.9 I/O pull-up or pull-down.
\r
497 * | | |00 = PF.9 pull-up and pull-down disable.
\r
498 * | | |01 = PF.9 pull-down enable.
\r
499 * | | |10 = PF.9 pull-up enable.
\r
500 * | | |11 = PF.9 pull-up and pull-down disable.
\r
502 * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
\r
503 * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode.
\r
504 * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode.
\r
505 * |[17:16] |OPMODE6 |IO Operation Mode
\r
506 * | | |00 = PF.10 is input only mode, without pull-up resistor.
\r
507 * | | |01 = PF.10 is output push pull mode.
\r
508 * | | |10 = PF.10 is open drain mode.
\r
509 * | | |11 = PF.10 is quasi-bidirectional mode with with internal pull up.
\r
510 * |[18] |DOUT6 |IO Output Data
\r
511 * | | |0 = PF.10 output low.
\r
512 * | | |1 = PF.10 output high.
\r
513 * |[19] |CTLSEL6 |IO Pin State Backup Selection
\r
514 * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function
\r
515 * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.
\r
516 * | | |0 = PF.10 pin I/O function is controlled by GPIO module.
\r
517 * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off.
\r
518 * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain.
\r
519 * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1.
\r
520 * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
\r
521 * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable Bit
\r
522 * | | |Determine PF.10 I/O pull-up or pull-down.
\r
523 * | | |00 = PF.10 pull-up and pull-down disable.
\r
524 * | | |01 = PF.10 pull-down enable.
\r
525 * | | |10 = PF.10 pull-up enable.
\r
526 * | | |11 = PF.10 pull-up and pull-down disable.
\r
528 * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
\r
529 * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode.
\r
530 * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode.
\r
531 * |[25:24] |OPMODE7 |IO Operation Mode
\r
532 * | | |00 = PF.11 is input only mode, without pull-up resistor.
\r
533 * | | |01 = PF.11 is output push pull mode.
\r
534 * | | |10 = PF.11 is open drain mode.
\r
535 * | | |11 = PF.11 is quasi-bidirectional mode with with internal pull up.
\r
536 * |[26] |DOUT7 |IO Output Data
\r
537 * | | |0 = PF.11 output low.
\r
538 * | | |1 = PF.11 output high.
\r
539 * |[27] |CTLSEL7 |IO Pin State Backup Selection
\r
540 * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function
\r
541 * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.
\r
542 * | | |0 = PF.11 pin I/O function is controlled by GPIO module.
\r
543 * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off.
\r
544 * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain.
\r
545 * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1.
\r
546 * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1.
\r
547 * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable Bit
\r
548 * | | |Determine PF.11 I/O pull-up or pull-down.
\r
549 * | | |00 = PF.11 pull-up and pull-down disable.
\r
550 * | | |01 = PF.11 pull-down enable.
\r
551 * | | |10 = PF.11 pull-up enable.
\r
552 * | | |11 = PF.11 pull-up and pull-down disable.
\r
554 * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
\r
555 * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode.
\r
556 * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode.
\r
557 * @var RTC_T::DSTCTL
\r
558 * Offset: 0x110 RTC Daylight Saving Time Control Register
\r
559 * ---------------------------------------------------------------------------------------------------
\r
560 * |Bits |Field |Descriptions
\r
561 * | :----: | :----: | :---- |
\r
562 * |[0] |ADDHR |Add 1 Hour
\r
563 * | | |0 = No effect.
\r
564 * | | |1 = Indicates RTC hour digit has been added one hour for summer time change.
\r
565 * |[1] |SUBHR |Subtract 1 Hour
\r
566 * | | |0 = No effect.
\r
567 * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change.
\r
568 * |[2] |DSBAK |Daylight Saving Back
\r
569 * | | |0= Daylight Saving Change is not performed.
\r
570 * | | |1= Daylight Saving Change is performed.
\r
571 * @var RTC_T::TAMPCTL
\r
572 * Offset: 0x120 RTC Tamper Pin Control Register
\r
573 * ---------------------------------------------------------------------------------------------------
\r
574 * |Bits |Field |Descriptions
\r
575 * | :----: | :----: | :---- |
\r
576 * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select
\r
577 * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.
\r
578 * | | |0 = Tamper input is from Tamper 2.
\r
579 * | | |1 = Tamper input is from Tamper 0.
\r
580 * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
\r
581 * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select
\r
582 * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.
\r
583 * | | |0 = Tamper input is from Tamper 4.
\r
584 * | | |1 = Tamper input is from Tamper 0.
\r
585 * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
\r
586 * |[3:2] |DYNSRC |Dynamic Reference Pattern
\r
587 * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode.
\r
588 * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out.
\r
589 * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out.
\r
590 * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out.
\r
591 * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
\r
592 * |[4] |SEEDRLD |Reload New Seed for PRNG Engine
\r
593 * | | |Setting this bit, the tamper configuration will be reload.
\r
594 * | | |0 = Generating key based on the current seed.
\r
595 * | | |1 = Reload new seed.
\r
596 * | | |Note: Before set this bit, the tamper configuration should be set to complete.
\r
597 * |[7:5] |DYNRATE |Dynamic Change Rate
\r
598 * | | |This item is choice the dynamic tamper output change rate.
\r
599 * | | |000 = 2^10 * RTC_CLK.
\r
600 * | | |001 = 2^11 * RTC_CLK.
\r
601 * | | |010 = 2^12 * RTC_CLK.
\r
602 * | | |011 = 2^13 * RTC_CLK.
\r
603 * | | |100 = 2^14 * RTC_CLK.
\r
604 * | | |101 = 2^15 * RTC_CLK.
\r
605 * | | |110 = 2^16 * RTC_CLK.
\r
606 * | | |111 = 2^17 * RTC_CLK.
\r
607 * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload chage rate immediately.
\r
608 * |[8] |TAMP0EN |Tamper0 Detect Enable Bit
\r
609 * | | |0 = Tamper 0 detect Disabled.
\r
610 * | | |1 = Tamper 0 detect Enabled.
\r
611 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
\r
612 * |[9] |TAMP0LV |Tamper 0 Level
\r
613 * | | |This bit depend on level attribute of tamper pin for static tamper detection.
\r
614 * | | |0 = Detect voltage level is low.
\r
615 * | | |1 = Detect voltage level is high.
\r
616 * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit
\r
617 * | | |0 = Tamper 0 de-bounce Disabled.
\r
618 * | | |1 = Tamper 0 de-bounce Enabled.
\r
619 * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit
\r
620 * | | |0 = Tamper 1 detect Disabled.
\r
621 * | | |1 = Tamper 1 detect Enabled.
\r
622 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
\r
623 * |[13] |TAMP1LV |Tamper 1 Level
\r
624 * | | |This bit depend on level attribute of tamper pin for static tamper detection.
\r
625 * | | |0 = Detect voltage level is low.
\r
626 * | | |1 = Detect voltage level is high.
\r
627 * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit
\r
628 * | | |0 = Tamper 1 de-bounce Disabled.
\r
629 * | | |1 = Tamper 1 de-bounce Enabled.
\r
630 * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit
\r
631 * | | |0 = Static detect.
\r
632 * | | |1 = Dynamic detect.
\r
633 * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit
\r
634 * | | |0 = Tamper 2 detect Disabled.
\r
635 * | | |1 = Tamper 2 detect Enabled.
\r
636 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
\r
637 * |[17] |TAMP2LV |Tamper 2 Level
\r
638 * | | |This bit depend on level attribute of tamper pin for static tamper detection.
\r
639 * | | |0 = Detect voltage level is low.
\r
640 * | | |1 = Detect voltage level is high.
\r
641 * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit
\r
642 * | | |0 = Tamper 2 de-bounce Disabled.
\r
643 * | | |1 = Tamper 2 de-bounce Enabled.
\r
644 * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit
\r
645 * | | |0 = Tamper 3 detect Disabled.
\r
646 * | | |1 = Tamper 3 detect Enabled.
\r
647 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
\r
648 * |[21] |TAMP3LV |Tamper 3 Level
\r
649 * | | |This bit depend on level attribute of tamper pin for static tamper detection.
\r
650 * | | |0 = Detect voltage level is low.
\r
651 * | | |1 = Detect voltage level is high.
\r
652 * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit
\r
653 * | | |0 = Tamper 3 de-bounce Disabled.
\r
654 * | | |1 = Tamper 3 de-bounce Enabled.
\r
655 * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit
\r
656 * | | |0 = Static detect.
\r
657 * | | |1 = Dynamic detect.
\r
658 * |[24] |TAMP4EN |Tamper4 Detect Enable Bit
\r
659 * | | |0 = Tamper 4 detect Disabled.
\r
660 * | | |1 = Tamper 4 detect Enabled.
\r
661 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
\r
662 * |[25] |TAMP4LV |Tamper 4 Level
\r
663 * | | |This bit depend on level attribute of tamper pin for static tamper detection.
\r
664 * | | |0 = Detect voltage level is low.
\r
665 * | | |1 = Detect voltage level is high.
\r
666 * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit
\r
667 * | | |0 = Tamper 4 de-bounce Disabled.
\r
668 * | | |1 = Tamper 4 de-bounce Enabled.
\r
669 * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit
\r
670 * | | |0 = Tamper 5 detect Disabled.
\r
671 * | | |1 = Tamper 5 detect Enabled.
\r
672 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
\r
673 * |[29] |TAMP5LV |Tamper 5 Level
\r
674 * | | |This bit depend on level attribute of tamper pin for static tamper detection.
\r
675 * | | |0 = Detect voltage level is low.
\r
676 * | | |1 = Detect voltage level is high.
\r
677 * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit
\r
678 * | | |0 = Tamper 5 de-bounce Disabled.
\r
679 * | | |1 = Tamper 5 de-bounce Enabled.
\r
680 * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit
\r
681 * | | |0 = Static detect.
\r
682 * | | |1 = Dynamic detect.
\r
683 * @var RTC_T::TAMPSEED
\r
684 * Offset: 0x128 RTC Tamper Dynamic Seed Register
\r
685 * ---------------------------------------------------------------------------------------------------
\r
686 * |Bits |Field |Descriptions
\r
687 * | :----: | :----: | :---- |
\r
688 * |[31:0] |SEED |Seed Value
\r
689 * @var RTC_T::TAMPTIME
\r
690 * Offset: 0x130 RTC Tamper Time Register
\r
691 * ---------------------------------------------------------------------------------------------------
\r
692 * |Bits |Field |Descriptions
\r
693 * | :----: | :----: | :---- |
\r
694 * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9)
\r
695 * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5)
\r
696 * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9)
\r
697 * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5)
\r
698 * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9)
\r
699 * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) Note: 24-hour time scale only .
\r
700 * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F)
\r
701 * @var RTC_T::TAMPCAL
\r
702 * Offset: 0x134 RTC Tamper Calendar Register
\r
703 * ---------------------------------------------------------------------------------------------------
\r
704 * |Bits |Field |Descriptions
\r
705 * | :----: | :----: | :---- |
\r
706 * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9)
\r
707 * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3)
\r
708 * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9)
\r
709 * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1)
\r
710 * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9)
\r
711 * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9)
\r
712 * @var RTC_T::CLKDCTL
\r
713 * Offset: 0x140 Clock Fail Detector Control Register
\r
714 * ---------------------------------------------------------------------------------------------------
\r
715 * |Bits |Field |Descriptions
\r
716 * | :----: | :----: | :---- |
\r
717 * |[0] |LXTFDEN |LXT Clock Fail/Stop Detector Enable Bit
\r
718 * | | |0 = LXT clock fail/stop detector Disabled.
\r
719 * | | |1 = LXT clock fail/stop detector Enabled.
\r
721 * |[1] |LXTFSW |LXT Clock Fail Detector Switch LIRC32K Enable Bit
\r
722 * | | |0 = LXT Clock Fail Detector Switch LIRC32K Disabled.
\r
724 * | | |If LXT clock fail detector flag CLKFIF (RTC_INTSTS[24]) is generated, RTC clock source will switch to LIRC32K automatically.
\r
725 * |[2] |LXTSPSW |LXT Clock Stop Detector Switch LIRC32K Enable Bit
\r
726 * | | |0 = LXT Clock Stop Detector Switch LIRC32K Disabled.
\r
728 * | | |If LXT clock stop detector flag CLKSPIF (RTC_INTSTS[25]) is generated, RTC clock source will switch to LIRC32K automatically
\r
729 * |[16] |CLKSWLIRCF|LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only)
\r
730 * | | |0 = RTC clock source from LXT.
\r
731 * | | |1 = RTC clock source from LIRC32K .
\r
732 * |[17] |LXTFASTF |LXT Faster Than LIRX32K Flag (Read Only)
\r
733 * | | |0 = LXT frequency is slowly.
\r
734 * | | |1 = LXT frequency faster than LIRC32K.
\r
736 * Offset: 0x144 Clock Frequency Detector Boundary Register
\r
737 * ---------------------------------------------------------------------------------------------------
\r
738 * |Bits |Field |Descriptions
\r
739 * | :----: | :----: | :---- |
\r
740 * |[7:0] |STOPBD |LXT Clock Frequency Detector Stop Boundary
\r
741 * | | |The bits define the stop value of frequency monitor window.
\r
742 * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary , the LXT frequency detect Stop interrupt flag will set to 1.
\r
743 * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time.
\r
744 * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary
\r
745 * | | |The bits define the fail value of frequency monitor window.
\r
746 * | | |When LXT frequency monitor counter lower than Clock Frequency Detector fail Boundary , the LXT frequency detect fail interrupt flag will set to 1.
\r
747 * | | |Note: The boundary is defined as the minimum value of LXT among 256 LIRC32K clock time.
\r
749 __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */
\r
750 __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */
\r
751 __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */
\r
752 __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */
\r
753 __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */
\r
754 __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */
\r
755 __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */
\r
756 __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */
\r
757 __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */
\r
758 __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */
\r
759 __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */
\r
760 __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */
\r
761 __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */
\r
762 __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */
\r
763 __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */
\r
764 __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */
\r
765 __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008C] RTC Spare Register 0 ~ 19 */
\r
766 __I uint32_t RESERVE0[28]; /* 0x90 ~ 0xFC */
\r
767 __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */
\r
768 __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */
\r
769 __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */
\r
770 __I uint32_t RESERVE1[1];
\r
771 __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */
\r
772 __I uint32_t RESERVE2[3];
\r
773 __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */
\r
774 __I uint32_t RESERVE3[1];
\r
775 __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */
\r
776 __I uint32_t RESERVE4[1];
\r
777 __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */
\r
778 __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */
\r
779 __I uint32_t RESERVE5[2];
\r
780 __IO uint32_t CLKDCTL; /*!< [0x0140] Clock Fail Detector Control Register */
\r
781 __IO uint32_t CDBR; /*!< [0x0144] Clock Frequency Detector Boundary Register */
\r
786 @addtogroup RTC_CONST RTC Bit Field Definition
\r
787 Constant Definitions for RTC Controller
\r
790 #define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */
\r
791 #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */
\r
793 #define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */
\r
794 #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
\r
796 #define RTC_RWEN_RWEN_Pos (0) /*!< RTC_T::RWEN: RWEN Position */
\r
797 #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC_T::RWEN: RWEN Mask */
\r
799 #define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */
\r
800 #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */
\r
802 #define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */
\r
803 #define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */
\r
805 #define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */
\r
806 #define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */
\r
808 #define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
\r
809 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
\r
811 #define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
\r
812 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
\r
814 #define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
\r
815 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
\r
817 #define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
\r
818 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
\r
820 #define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
\r
821 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
\r
823 #define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
\r
824 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
\r
826 #define RTC_TIME_HZCNT_Pos (24) /*!< RTC_T::TIME: HZCNT Position */
\r
827 #define RTC_TIME_HZCNT_Msk (0x7ful << RTC_TIME_HZCNT_Pos) /*!< RTC_T::TIME: HZCNT Mask */
\r
829 #define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
\r
830 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
\r
832 #define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
\r
833 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
\r
835 #define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
\r
836 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
\r
838 #define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
\r
839 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
\r
841 #define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
\r
842 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
\r
844 #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
\r
845 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
\r
847 #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
\r
848 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
\r
850 #define RTC_CLKFMT_HZCNTEN_Pos (8) /*!< RTC_T::CLKFMT: HZCNTEN Position */
\r
851 #define RTC_CLKFMT_HZCNTEN_Msk (0x1ul << RTC_CLKFMT_HZCNTEN_Pos) /*!< RTC_T::CLKFMT: HZCNTEN Mask */
\r
853 #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
\r
854 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
\r
856 #define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
\r
857 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
\r
859 #define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
\r
860 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
\r
862 #define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
\r
863 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
\r
865 #define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
\r
866 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
\r
868 #define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
\r
869 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
\r
871 #define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
\r
872 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
\r
874 #define RTC_TALM_HZCNT_Pos (24) /*!< RTC_T::TALM: HZCNT Position */
\r
875 #define RTC_TALM_HZCNT_Msk (0x7ful << RTC_TALM_HZCNT_Pos) /*!< RTC_T::TALM: HZCNT Mask */
\r
877 #define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
\r
878 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
\r
880 #define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
\r
881 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
\r
883 #define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
\r
884 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
\r
886 #define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
\r
887 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
\r
889 #define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
\r
890 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
\r
892 #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
\r
893 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
\r
895 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
\r
896 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
\r
898 #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
\r
899 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
\r
901 #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
\r
902 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
\r
904 #define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */
\r
905 #define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */
\r
907 #define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */
\r
908 #define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */
\r
910 #define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */
\r
911 #define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */
\r
913 #define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */
\r
914 #define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */
\r
916 #define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */
\r
917 #define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */
\r
919 #define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */
\r
920 #define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */
\r
922 #define RTC_INTEN_CLKFIEN_Pos (24) /*!< RTC_T::INTEN: CLKFIEN Position */
\r
923 #define RTC_INTEN_CLKFIEN_Msk (0x1ul << RTC_INTEN_CLKFIEN_Pos) /*!< RTC_T::INTEN: CLKFIEN Mask */
\r
925 #define RTC_INTEN_CLKSPIEN_Pos (25) /*!< RTC_T::INTEN: CLKSPIEN Position */
\r
926 #define RTC_INTEN_CLKSPIEN_Msk (0x1ul << RTC_INTEN_CLKSPIEN_Pos) /*!< RTC_T::INTEN: CLKSPIEN Mask */
\r
928 #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
\r
929 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
\r
931 #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
\r
932 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
\r
934 #define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */
\r
935 #define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */
\r
937 #define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */
\r
938 #define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */
\r
940 #define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */
\r
941 #define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */
\r
943 #define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */
\r
944 #define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */
\r
946 #define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */
\r
947 #define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */
\r
949 #define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */
\r
950 #define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */
\r
952 #define RTC_INTSTS_CLKFIF_Pos (24) /*!< RTC_T::INTSTS: CLKFIF Position */
\r
953 #define RTC_INTSTS_CLKFIF_Msk (0x1ul << RTC_INTSTS_CLKFIF_Pos) /*!< RTC_T::INTSTS: CLKFIF Mask */
\r
955 #define RTC_INTSTS_CLKSPIF_Pos (25) /*!< RTC_T::INTSTS: CLKSPIF Position */
\r
956 #define RTC_INTSTS_CLKSPIF_Msk (0x1ul << RTC_INTSTS_CLKSPIF_Pos) /*!< RTC_T::INTSTS: CLKSPIF Mask */
\r
958 #define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
\r
959 #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
\r
961 #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
\r
962 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
\r
964 #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
\r
965 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
\r
967 #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
\r
968 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
\r
970 #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
\r
971 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
\r
973 #define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
\r
974 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
\r
976 #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
\r
977 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
\r
979 #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
\r
980 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
\r
982 #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
\r
983 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
\r
985 #define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
\r
986 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
\r
988 #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
\r
989 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
\r
991 #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
\r
992 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
\r
994 #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
\r
995 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
\r
997 #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
\r
998 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
\r
1000 #define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
\r
1001 #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
\r
1003 #define RTC_SPRCTL_LXTFCLR_Pos (16) /*!< RTC_T::SPRCTL: LXTFCLR Position */
\r
1004 #define RTC_SPRCTL_LXTFCLR_Msk (0x1ul << RTC_SPRCTL_LXTFCLR_Pos) /*!< RTC_T::SPRCTL: LXTFCLR Mask */
\r
1006 #define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */
\r
1007 #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */
\r
1009 #define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */
\r
1010 #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */
\r
1012 #define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */
\r
1013 #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */
\r
1015 #define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */
\r
1016 #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */
\r
1018 #define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */
\r
1019 #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */
\r
1021 #define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */
\r
1022 #define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */
\r
1024 #define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */
\r
1025 #define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */
\r
1027 #define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */
\r
1028 #define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */
\r
1030 #define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */
\r
1031 #define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */
\r
1033 #define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */
\r
1034 #define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */
\r
1036 #define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */
\r
1037 #define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */
\r
1039 #define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */
\r
1040 #define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */
\r
1042 #define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */
\r
1043 #define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */
\r
1045 #define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */
\r
1046 #define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */
\r
1048 #define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */
\r
1049 #define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */
\r
1051 #define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */
\r
1052 #define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */
\r
1054 #define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */
\r
1055 #define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */
\r
1057 #define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */
\r
1058 #define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */
\r
1060 #define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */
\r
1061 #define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */
\r
1063 #define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */
\r
1064 #define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */
\r
1066 #define RTC_LXTCTL_LIRC32KEN_Pos (0) /*!< RTC_T::LXTCTL: LIRC32KEN Position */
\r
1067 #define RTC_LXTCTL_LIRC32KEN_Msk (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos) /*!< RTC_T::LXTCTL: LIRC32KEN Mask */
\r
1069 #define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
\r
1070 #define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
\r
1072 #define RTC_LXTCTL_C32KS_Pos (7) /*!< RTC_T::LXTCTL: C32KS Position */
\r
1073 #define RTC_LXTCTL_C32KS_Msk (0x1ul << RTC_LXTCTL_C32KS_Pos) /*!< RTC_T::LXTCTL: C32KS Mask */
\r
1075 #define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */
\r
1076 #define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */
\r
1078 #define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */
\r
1079 #define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */
\r
1081 #define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */
\r
1082 #define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */
\r
1084 #define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */
\r
1085 #define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */
\r
1087 #define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */
\r
1088 #define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */
\r
1090 #define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */
\r
1091 #define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */
\r
1093 #define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */
\r
1094 #define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */
\r
1096 #define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */
\r
1097 #define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */
\r
1099 #define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */
\r
1100 #define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */
\r
1102 #define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */
\r
1103 #define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */
\r
1105 #define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */
\r
1106 #define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */
\r
1108 #define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */
\r
1109 #define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */
\r
1111 #define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */
\r
1112 #define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */
\r
1114 #define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */
\r
1115 #define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */
\r
1117 #define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */
\r
1118 #define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */
\r
1120 #define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */
\r
1121 #define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */
\r
1123 #define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */
\r
1124 #define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */
\r
1126 #define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */
\r
1127 #define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */
\r
1129 #define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */
\r
1130 #define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */
\r
1132 #define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */
\r
1133 #define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */
\r
1135 #define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */
\r
1136 #define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */
\r
1138 #define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */
\r
1139 #define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */
\r
1141 #define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */
\r
1142 #define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */
\r
1144 #define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */
\r
1145 #define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */
\r
1147 #define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */
\r
1148 #define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */
\r
1150 #define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */
\r
1151 #define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */
\r
1153 #define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */
\r
1154 #define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */
\r
1156 #define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */
\r
1157 #define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */
\r
1159 #define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */
\r
1160 #define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */
\r
1162 #define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */
\r
1163 #define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */
\r
1165 #define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */
\r
1166 #define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */
\r
1168 #define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */
\r
1169 #define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */
\r
1171 #define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */
\r
1172 #define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */
\r
1174 #define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */
\r
1175 #define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */
\r
1177 #define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */
\r
1178 #define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */
\r
1180 #define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */
\r
1181 #define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */
\r
1183 #define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */
\r
1184 #define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */
\r
1186 #define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */
\r
1187 #define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */
\r
1189 #define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */
\r
1190 #define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */
\r
1192 #define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */
\r
1193 #define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */
\r
1195 #define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */
\r
1196 #define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */
\r
1198 #define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */
\r
1199 #define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */
\r
1201 #define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */
\r
1202 #define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */
\r
1204 #define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */
\r
1205 #define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */
\r
1207 #define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */
\r
1208 #define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */
\r
1210 #define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */
\r
1211 #define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */
\r
1213 #define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */
\r
1214 #define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */
\r
1216 #define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */
\r
1217 #define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */
\r
1219 #define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */
\r
1220 #define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */
\r
1222 #define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */
\r
1223 #define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */
\r
1225 #define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */
\r
1226 #define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */
\r
1228 #define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */
\r
1229 #define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */
\r
1231 #define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */
\r
1232 #define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */
\r
1234 #define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */
\r
1235 #define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */
\r
1237 #define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */
\r
1238 #define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */
\r
1240 #define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */
\r
1241 #define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */
\r
1243 #define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */
\r
1244 #define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */
\r
1246 #define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */
\r
1247 #define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */
\r
1249 #define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */
\r
1250 #define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */
\r
1252 #define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */
\r
1253 #define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */
\r
1255 #define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */
\r
1256 #define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */
\r
1258 #define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */
\r
1259 #define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */
\r
1261 #define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */
\r
1262 #define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */
\r
1264 #define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */
\r
1265 #define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */
\r
1267 #define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */
\r
1268 #define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */
\r
1270 #define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */
\r
1271 #define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */
\r
1273 #define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */
\r
1274 #define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */
\r
1276 #define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */
\r
1277 #define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */
\r
1279 #define RTC_TAMPTIME_HZCNT_Pos (24) /*!< RTC_T::TAMPTIME: HZCNT Position */
\r
1280 #define RTC_TAMPTIME_HZCNT_Msk (0x7ful << RTC_TAMPTIME_HZCNT_Pos) /*!< RTC_T::TAMPTIME: HZCNT Mask */
\r
1282 #define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */
\r
1283 #define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */
\r
1285 #define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */
\r
1286 #define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */
\r
1288 #define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */
\r
1289 #define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */
\r
1291 #define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */
\r
1292 #define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */
\r
1294 #define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */
\r
1295 #define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */
\r
1297 #define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */
\r
1298 #define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */
\r
1300 #define RTC_CLKDCTL_LXTFDEN_Pos (0) /*!< RTC_T::CLKDCTL: LXTFDEN Position */
\r
1301 #define RTC_CLKDCTL_LXTFDEN_Msk (0x1ul << RTC_CLKDCTL_LXTFDEN_Pos) /*!< RTC_T::CLKDCTL: LXTFDEN Mask */
\r
1303 #define RTC_CLKDCTL_LXTFSW_Pos (1) /*!< RTC_T::CLKDCTL: LXTFSW Position */
\r
1304 #define RTC_CLKDCTL_LXTFSW_Msk (0x1ul << RTC_CLKDCTL_LXTFSW_Pos) /*!< RTC_T::CLKDCTL: LXTFSW Mask */
\r
1306 #define RTC_CLKDCTL_LXTSPSW_Pos (2) /*!< RTC_T::CLKDCTL: LXTSPSW Position */
\r
1307 #define RTC_CLKDCTL_LXTSPSW_Msk (0x1ul << RTC_CLKDCTL_LXTSPSW_Pos) /*!< RTC_T::CLKDCTL: LXTSPSW Mask */
\r
1309 #define RTC_CLKDCTL_CLKSWLIRCF_Pos (16) /*!< RTC_T::CLKDCTL: CLKSWLIRCF Position */
\r
1310 #define RTC_CLKDCTL_CLKSWLIRCF_Msk (0x1ul << RTC_CLKDCTL_CLKSWLIRCF_Pos) /*!< RTC_T::CLKDCTL: CLKSWLIRCF Mask */
\r
1312 #define RTC_CLKDCTL_LXTFASTF_Pos (17) /*!< RTC_T::CLKDCTL: LXTFASTF Position */
\r
1313 #define RTC_CLKDCTL_LXTFASTF_Msk (0x1ul << RTC_CLKDCTL_LXTFASTF_Pos) /*!< RTC_T::CLKDCTL: LXTFASTF Mask */
\r
1315 #define RTC_CDBR_STOPBD_Pos (0) /*!< RTC_T::CDBR: STOPBD Position */
\r
1316 #define RTC_CDBR_STOPBD_Msk (0xfful << RTC_CDBR_STOPBD_Pos) /*!< RTC_T::CDBR: STOPBD Mask */
\r
1318 #define RTC_CDBR_FAILBD_Pos (16) /*!< RTC_T::CDBR: FAILBD Position */
\r
1319 #define RTC_CDBR_FAILBD_Msk (0xfful << RTC_CDBR_FAILBD_Pos) /*!< RTC_T::CDBR: FAILBD Mask */
\r
1321 /**@}*/ /* RTC_CONST */
\r
1322 /**@}*/ /* end of RTC register group */
\r
1323 /**@}*/ /* end of REGISTER group */
\r
1325 #endif /* __RTC_REG_H__ */
\r
projects / freertos / blob