1 /**************************************************************************//**
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4 * @brief TIMER register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __TIMER_REG_H__
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9 #define __TIMER_REG_H__
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11 /** @addtogroup REGISTER Control Register
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17 /*---------------------- Timer Controller -------------------------*/
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19 @addtogroup TIMER Timer Controller(TIMER)
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20 Memory Mapped Structure for TIMER Controller
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29 * Offset: 0x00 Timer Control Register
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30 * ---------------------------------------------------------------------------------------------------
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31 * |Bits |Field |Descriptions
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32 * | :----: | :----: | :---- |
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33 * |[7:0] |PSC |Prescale Counter
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34 * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter
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35 * | | |If this field is 0 (PSC = 0), then there is no scaling.
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36 * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
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37 * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control
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38 * | | |Setting this bit will enable the inter-timer trigger capture function.
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39 * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event
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40 * | | |Also, Timer1/3 will be in trigger-counting mode of capture function.
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41 * | | |0 = Inter-Timer Trigger Capture mode Disabled.
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42 * | | |1 = Inter-Timer Trigger Capture mode Enabled.
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43 * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0.
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44 * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit
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45 * | | |0 = The behavior selection in periodic mode is Disabled.
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46 * | | |When user updates CMPDAT while timer is running in periodic mode,
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47 * | | |CNT will be reset to default value.
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48 * | | |1 = The behavior selection in periodic mode is Enabled.
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49 * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list,
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50 * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually.
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51 * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately.
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52 * | | |If updated CMPDAT value < CNT, CNT will be reset to default value.
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53 * |[21] |TGLPINSEL |Toggle-output Pin Select
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54 * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin).
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55 * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin).
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56 * |[22] |CAPSRC |Capture Pin Source Selection
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57 * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin.
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58 * | | |1 = Capture Function source is from internal ACMP output signal
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59 * | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source.
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60 * |[23] |WKEN |Wake-up Function Enable Bit
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61 * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
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62 * | | |0 = Wake-up function Disabled if timer interrupt signal generated.
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63 * | | |1 = Wake-up function Enabled if timer interrupt signal generated.
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64 * |[24] |EXTCNTEN |Event Counter Mode Enable Bit
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65 * | | |This bit is for external counting pin function enabled.
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66 * | | |0 = Event counter mode Disabled.
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67 * | | |1 = Event counter mode Enabled.
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68 * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
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69 * |[25] |ACTSTS |Timer Active Status Bit (Read Only)
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70 * | | |This bit indicates the 24-bit up counter status.
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71 * | | |0 = 24-bit up counter is not active.
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72 * | | |1 = 24-bit up counter is active.
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73 * | | |Note: This bit may active when CNT 0 transition to CNT 1.
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74 * |[28:27] |OPMODE |Timer Counting Mode Select
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75 * | | |00 = The Timer controller is operated in One-shot mode.
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76 * | | |01 = The Timer controller is operated in Periodic mode.
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77 * | | |10 = The Timer controller is operated in Toggle-output mode.
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78 * | | |11 = The Timer controller is operated in Continuous Counting mode.
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79 * |[29] |INTEN |Timer Interrupt Enable Bit
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80 * | | |0 = Timer time-out interrupt Disabled.
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81 * | | |1 = Timer time-out interrupt Enabled.
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82 * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
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83 * |[30] |CNTEN |Timer Counting Enable Bit
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84 * | | |0 = Stops/Suspends counting.
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85 * | | |1 = Starts counting.
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86 * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
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87 * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
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88 * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
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89 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
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90 * | | |0 = ICE debug mode acknowledgment effects TIMER counting.
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91 * | | |TIMER counter will be held while CPU is held by ICE.
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92 * | | |1 = ICE debug mode acknowledgment Disabled.
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93 * | | |TIMER counter will keep going no matter CPU is held by ICE or not.
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94 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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96 * Offset: 0x04 Timer Comparator Register
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97 * ---------------------------------------------------------------------------------------------------
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98 * |Bits |Field |Descriptions
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99 * | :----: | :----: | :---- |
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100 * |[23:0] |CMPDAT |Timer Comparator Value
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101 * | | |CMPDAT is a 24-bit compared value register
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102 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
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103 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
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104 * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
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105 * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field
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106 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
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107 * @var TIMER_T::INTSTS
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108 * Offset: 0x08 Timer Interrupt Status Register
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109 * ---------------------------------------------------------------------------------------------------
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110 * |Bits |Field |Descriptions
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111 * | :----: | :----: | :---- |
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112 * |[0] |TIF |Timer Interrupt Flag
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113 * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
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114 * | | |0 = No effect.
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115 * | | |1 = CNT value matches the CMPDAT value.
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116 * | | |Note: This bit is cleared by writing 1 to it.
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117 * |[1] |TWKF |Timer Wake-up Flag
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118 * | | |This bit indicates the interrupt wake-up flag status of timer.
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119 * | | |0 = Timer does not cause CPU wake-up.
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120 * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
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121 * | | |Note: This bit is cleared by writing 1 to it.
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122 * @var TIMER_T::CNT
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123 * Offset: 0x0C Timer Data Register
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124 * ---------------------------------------------------------------------------------------------------
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125 * |Bits |Field |Descriptions
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126 * | :----: | :----: | :---- |
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127 * |[23:0] |CNT |Timer Data Register
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128 * | | |Read operation.
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129 * | | |Read this register to get CNT value. For example:
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130 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.
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131 * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.
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132 * | | |Write operation.
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133 * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
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134 * |[31] |RSTACT |Timer Data Register Reset Active (Read Only)
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135 * | | |This bit indicates if the counter reset operation active.
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136 * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter
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137 * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress
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138 * | | |Once the counter reset operation done, timer clear this bit to 0 automatically.
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139 * | | |0 = Reset operation is done.
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140 * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress.
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141 * | | |Note: This bit is read only.
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142 * @var TIMER_T::CAP
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143 * Offset: 0x10 Timer Capture Data Register
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144 * ---------------------------------------------------------------------------------------------------
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145 * |Bits |Field |Descriptions
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146 * | :----: | :----: | :---- |
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147 * |[23:0] |CAPDAT |Timer Capture Data Register
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148 * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
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149 * @var TIMER_T::EXTCTL
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150 * Offset: 0x14 Timer External Control Register
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151 * ---------------------------------------------------------------------------------------------------
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152 * |Bits |Field |Descriptions
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153 * | :----: | :----: | :---- |
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154 * |[0] |CNTPHASE |Timer External Count Phase
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155 * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3).
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156 * | | |0 = A falling edge of external counting pin will be counted.
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157 * | | |1 = A rising edge of external counting pin will be counted.
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158 * |[3] |CAPEN |Timer External Capture Pin Enable Bit
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159 * | | |This bit enables the TMx_EXT capture pin input function.
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160 * | | |0 =TMx_EXT (x= 0~3) pin Disabled.
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161 * | | |1 =TMx_EXT (x= 0~3) pin Enabled.
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162 * |[4] |CAPFUNCS |Capture Function Selection
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163 * | | |0 = External Capture Mode Enabled.
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164 * | | |1 = External Reset Mode Enabled.
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165 * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field.
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166 * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately.
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167 * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit
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168 * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled.
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169 * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled.
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170 * | | |Note: CAPIEN is used to enable timer external interrupt
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171 * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
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172 * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
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173 * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit
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174 * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled.
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175 * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled.
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176 * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
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177 * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit
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178 * | | |0 = TMx (x= 0~3) pin de-bounce Disabled.
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179 * | | |1 = TMx (x= 0~3) pin de-bounce Enabled.
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180 * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
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181 * |[8] |ACMPSSEL |ACMP Source Selection to Trigger Capture Function
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182 * | | |0 = Capture Function source is from internal ACMP0 output signal.
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183 * | | |1 = Capture Function source is from internal ACMP1 output signal.
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184 * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
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185 * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect
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186 * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
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187 * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin.
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188 * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin.
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189 * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer.
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190 * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer..
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191 * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin.
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192 * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin.
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193 * | | |100, 101 = Reserved.
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194 * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function
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195 * | | |0 = Event Counter input source is from TMx (x= 0~3) pin.
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196 * | | |1 = Event Counter input source is from USB internal SOF output signal.
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197 * @var TIMER_T::EINTSTS
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198 * Offset: 0x18 Timer External Interrupt Status Register
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199 * ---------------------------------------------------------------------------------------------------
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200 * |Bits |Field |Descriptions
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201 * | :----: | :----: | :---- |
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202 * |[0] |CAPIF |Timer External Capture Interrupt Flag
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203 * | | |This bit indicates the timer external capture interrupt flag status.
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204 * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
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205 * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred.
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206 * | | |Note1: This bit is cleared by writing 1 to it.
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207 * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
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208 * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status
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209 * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
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210 * @var TIMER_T::TRGCTL
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211 * Offset: 0x1C Timer Trigger Control Register
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212 * ---------------------------------------------------------------------------------------------------
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213 * |Bits |Field |Descriptions
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214 * | :----: | :----: | :---- |
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215 * |[0] |TRGSSEL |Trigger Source Select Bit
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216 * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
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217 * | | |0 = Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC.
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218 * | | |1 = Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC.
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219 * |[1] |TRGEPWM |Trigger PWM Enable Bit
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220 * | | |If this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source.
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221 * | | |0 = Timer interrupt trigger PWM Disabled.
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222 * | | |1 = Timer interrupt trigger PWM Enabled.
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223 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as PWM counter clock source.
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224 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as PWM counter clock source.
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225 * |[2] |TRGEADC |Trigger EADC Enable Bit
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226 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
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227 * | | |0 = Timer interrupt trigger EADC Disabled.
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228 * | | |1 = Timer interrupt trigger EADC Enabled.
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229 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion.
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230 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger ADC conversion.
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231 * |[3] |TRGDAC |Trigger DAC Enable Bit
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232 * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
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233 * | | |0 = Timer interrupt trigger DAC Disabled.
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234 * | | |1 = Timer interrupt trigger DAC Enabled.
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235 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC.
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236 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC.
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237 * |[4] |TRGPDMA |Trigger PDMA Enable Bit
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238 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
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239 * | | |0 = Timer interrupt trigger PDMA Disabled.
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240 * | | |1 = Timer interrupt trigger PDMA Enabled.
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241 * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer.
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242 * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer.
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243 * @var TIMER_T::ALTCTL
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244 * Offset: 0x20 Timer Alternative Control Register
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245 * ---------------------------------------------------------------------------------------------------
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246 * |Bits |Field |Descriptions
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247 * | :----: | :----: | :---- |
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248 * |[0] |FUNCSEL |Function Selection
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249 * | | |0 = Timer controller is used as timer function.
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250 * | | |1 = Timer controller is used as PWM function.
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251 * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
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252 * @var TIMER_T::PWMCTL
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253 * Offset: 0x40 Timer PWM Control Register
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254 * ---------------------------------------------------------------------------------------------------
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255 * |Bits |Field |Descriptions
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256 * | :----: | :----: | :---- |
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257 * |[0] |CNTEN |PWM Counter Enable Bit
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258 * | | |0 = PWM counter and clock prescale Stop Running.
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259 * | | |1 = PWM counter and clock prescale Start Running.
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260 * |[2:1] |CNTTYPE |PWM Counter Behavior Type
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261 * | | |00 = Up count type.
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262 * | | |01 = Down count type.
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263 * | | |10 = Up-down count type.
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264 * | | |11 = Reserved.
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265 * |[3] |CNTMODE |PWM Counter Mode
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266 * | | |0 = Auto-reload mode.
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267 * | | |1 = One-shot mode.
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268 * |[8] |CTRLD |Center Re-load
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269 * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
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270 * |[9] |IMMLDEN |Immediately Load Enable Bit
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271 * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled
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272 * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period.
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273 * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP.
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274 * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid.
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275 * |[16] |OUTMODE |PWM Output Mode
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276 * | | |This bit controls the output mode of corresponding PWM channel.
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277 * | | |0 = PWM independent mode.
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278 * | | |1 = PWM complementary mode.
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279 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
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280 * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.
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281 * | | |0 = ICE debug mode counter halt disable.
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282 * | | |1 = ICE debug mode counter halt enable.
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283 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
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284 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
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285 * | | |0 = ICE debug mode acknowledgment effects PWM output.
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286 * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged.
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287 * | | |1 = ICE debug mode acknowledgment disabled.
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288 * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not.
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289 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
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290 * @var TIMER_T::PWMCLKSRC
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291 * Offset: 0x44 Timer PWM Counter Clock Source Register
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292 * ---------------------------------------------------------------------------------------------------
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293 * |Bits |Field |Descriptions
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294 * | :----: | :----: | :---- |
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295 * |[2:0] |CLKSRC |PWM Counter Clock Source Select
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296 * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.
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297 * | | |000 = TMRx_CLK.
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298 * | | |001 = Internal TIMER0 time-out or capture event.
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299 * | | |010 = Internal TIMER1 time-out or capture event.
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300 * | | |011 = Internal TIMER2 time-out or capture event.
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301 * | | |100 = Internal TIMER3 time-out or capture event.
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302 * | | |Others = Reserved.
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303 * | | |Note: If Timer PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
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304 * @var TIMER_T::PWMCLKPSC
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305 * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register
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306 * ---------------------------------------------------------------------------------------------------
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307 * |Bits |Field |Descriptions
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308 * | :----: | :----: | :---- |
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309 * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale
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310 * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)
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311 * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source.
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312 * @var TIMER_T::PWMCNTCLR
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313 * Offset: 0x4C Timer PWM Clear Counter Register
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314 * ---------------------------------------------------------------------------------------------------
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315 * |Bits |Field |Descriptions
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316 * | :----: | :----: | :---- |
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317 * |[0] |CNTCLR |Clear PWM Counter Control Bit
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318 * | | |It is automatically cleared by hardware.
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319 * | | |0 = No effect.
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320 * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type.
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321 * @var TIMER_T::PWMPERIOD
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322 * Offset: 0x50 Timer PWM Period Register
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323 * ---------------------------------------------------------------------------------------------------
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324 * |Bits |Field |Descriptions
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325 * | :----: | :----: | :---- |
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326 * |[15:0] |PERIOD |PWM Period Register
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327 * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.
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328 * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.
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329 * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
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330 * | | |In up and down count type:
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331 * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK.
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332 * | | |In up-down count type:
\r
333 * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK.
\r
334 * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.
\r
335 * @var TIMER_T::PWMCMPDAT
\r
336 * Offset: 0x54 Timer PWM Comparator Register
\r
337 * ---------------------------------------------------------------------------------------------------
\r
338 * |Bits |Field |Descriptions
\r
339 * | :----: | :----: | :---- |
\r
340 * |[15:0] |CMP |PWM Comparator Register
\r
341 * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert.
\r
342 * @var TIMER_T::PWMDTCTL
\r
343 * Offset: 0x58 Timer PWM Dead-Time Control Register
\r
344 * ---------------------------------------------------------------------------------------------------
\r
345 * |Bits |Field |Descriptions
\r
346 * | :----: | :----: | :---- |
\r
347 * |[11:0] |DTCNT |Dead-time Counter (Write Protect)
\r
348 * | | |The dead-time can be calculated from the following two formulas:
\r
349 * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0.
\r
350 * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1.
\r
351 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
352 * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)
\r
353 * | | |Dead-time insertion function is only active when PWM complementary mode is enabled
\r
354 * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.
\r
355 * | | |0 = Dead-time insertion Disabled on the pin pair.
\r
356 * | | |1 = Dead-time insertion Enabled on the pin pair.
\r
357 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
358 * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect)
\r
359 * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale.
\r
360 * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale.
\r
361 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
362 * @var TIMER_T::PWMCNT
\r
363 * Offset: 0x5C Timer PWM Counter Register
\r
364 * ---------------------------------------------------------------------------------------------------
\r
365 * |Bits |Field |Descriptions
\r
366 * | :----: | :----: | :---- |
\r
367 * |[15:0] |CNT |PWM Counter Value Register (Read Only)
\r
368 * | | |User can monitor CNT to know the current counter value in 16-bit period counter.
\r
369 * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only)
\r
370 * | | |0 = Counter is active in down count.
\r
371 * | | |1 = Counter is active up count.
\r
372 * @var TIMER_T::PWMMSKEN
\r
373 * Offset: 0x60 Timer PWM Output Mask Enable Register
\r
374 * ---------------------------------------------------------------------------------------------------
\r
375 * |Bits |Field |Descriptions
\r
376 * | :----: | :----: | :---- |
\r
377 * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit
\r
378 * | | |The PWMx_CH0 output signal will be masked when this bit is enabled
\r
379 * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.
\r
380 * | | |0 = PWMx_CH0 output signal is non-masked.
\r
381 * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data.
\r
382 * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit
\r
383 * | | |The PWMx_CH1 output signal will be masked when this bit is enabled
\r
384 * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.
\r
385 * | | |0 = PWMx_CH1 output signal is non-masked.
\r
386 * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data.
\r
387 * @var TIMER_T::PWMMSK
\r
388 * Offset: 0x64 Timer PWM Output Mask Data Control Register
\r
389 * ---------------------------------------------------------------------------------------------------
\r
390 * |Bits |Field |Descriptions
\r
391 * | :----: | :----: | :---- |
\r
392 * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit
\r
393 * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1).
\r
394 * | | |0 = Output logic Low to PWMx_CH0.
\r
395 * | | |1 = Output logic High to PWMx_CH0.
\r
396 * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit
\r
397 * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1).
\r
398 * | | |0 = Output logic Low to PWMx_CH1.
\r
399 * | | |1 = Output logic High to PWMx_CH1.
\r
400 * @var TIMER_T::PWMBNF
\r
401 * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register
\r
402 * ---------------------------------------------------------------------------------------------------
\r
403 * |Bits |Field |Descriptions
\r
404 * | :----: | :----: | :---- |
\r
405 * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit
\r
406 * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled.
\r
407 * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled.
\r
408 * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection
\r
409 * | | |000 = Noise filter clock is PCLKx.
\r
410 * | | |001 = Noise filter clock is PCLKx/2.
\r
411 * | | |010 = Noise filter clock is PCLKx/4.
\r
412 * | | |011 = Noise filter clock is PCLKx/8.
\r
413 * | | |100 = Noise filter clock is PCLKx/16.
\r
414 * | | |101 = Noise filter clock is PCLKx/32.
\r
415 * | | |110 = Noise filter clock is PCLKx/64.
\r
416 * | | |111 = Noise filter clock is PCLKx/128.
\r
417 * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count
\r
418 * | | |The fields is used to control the active noise filter sample time.
\r
419 * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT.
\r
420 * |[7] |BRKPINV |Brake Pin Detection Control Bit
\r
421 * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect.
\r
422 * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect .
\r
423 * |[17:16] |BKPINSRC |Brake Pin Source Select
\r
424 * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin.
\r
425 * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin.
\r
426 * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin.
\r
427 * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin.
\r
428 * @var TIMER_T::PWMFAILBRK
\r
429 * Offset: 0x6C Timer PWM System Fail Brake Control Register
\r
430 * ---------------------------------------------------------------------------------------------------
\r
431 * |Bits |Field |Descriptions
\r
432 * | :----: | :----: | :---- |
\r
433 * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit
\r
434 * | | |0 = Brake Function triggered by clock fail detection Disabled.
\r
435 * | | |1 = Brake Function triggered by clock fail detection Enabled.
\r
436 * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit
\r
437 * | | |0 = Brake Function triggered by BOD event Disabled.
\r
438 * | | |1 = Brake Function triggered by BOD event Enabled.
\r
439 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit
\r
440 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
\r
441 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
\r
442 * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit
\r
443 * | | |0 = Brake Function triggered by core lockup event Disabled.
\r
444 * | | |1 = Brake Function triggered by core lockup event Enabled.
\r
445 * @var TIMER_T::PWMBRKCTL
\r
446 * Offset: 0x70 Timer PWM Brake Control Register
\r
447 * ---------------------------------------------------------------------------------------------------
\r
448 * |Bits |Field |Descriptions
\r
449 * | :----: | :----: | :---- |
\r
450 * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
\r
451 * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled.
\r
452 * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled.
\r
453 * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
\r
454 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
\r
455 * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
\r
456 * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled.
\r
457 * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled.
\r
458 * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
\r
459 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
\r
460 * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)
\r
461 * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled.
\r
462 * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled.
\r
463 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
464 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect)
\r
465 * | | |0 = System fail condition as edge-detect brake source Disabled.
\r
466 * | | |1 = System fail condition as edge-detect brake source Enabled.
\r
467 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
468 * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
\r
469 * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled.
\r
470 * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled.
\r
471 * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
\r
472 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
\r
473 * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
\r
474 * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled.
\r
475 * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled.
\r
476 * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
\r
477 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
478 * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)
\r
479 * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled.
\r
480 * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled.
\r
481 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
482 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect)
\r
483 * | | |0 = System fail condition as level-detect brake source Disabled.
\r
484 * | | |1 = System fail condition as level-detect brake source Enabled.
\r
485 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
486 * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect)
\r
487 * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output.
\r
488 * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened.
\r
489 * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened.
\r
490 * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened.
\r
491 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
492 * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect)
\r
493 * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output.
\r
494 * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened.
\r
495 * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened.
\r
496 * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened.
\r
497 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
498 * @var TIMER_T::PWMPOLCTL
\r
499 * Offset: 0x74 Timer PWM Pin Output Polar Control Register
\r
500 * ---------------------------------------------------------------------------------------------------
\r
501 * |Bits |Field |Descriptions
\r
502 * | :----: | :----: | :---- |
\r
503 * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit
\r
504 * | | |The bit is used to control polarity state of PWMx_CH0 output pin.
\r
505 * | | |0 = PWMx_CH0 output pin polar inverse Disabled.
\r
506 * | | |1 = PWMx_CH0 output pin polar inverse Enabled.
\r
507 * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit
\r
508 * | | |The bit is used to control polarity state of PWMx_CH1 output pin.
\r
509 * | | |0 = PWMx_CH1 output pin polar inverse Disabled.
\r
510 * | | |1 = PWMx_CH1 output pin polar inverse Enabled.
\r
511 * @var TIMER_T::PWMPOEN
\r
512 * Offset: 0x78 Timer PWM Pin Output Enable Register
\r
513 * ---------------------------------------------------------------------------------------------------
\r
514 * |Bits |Field |Descriptions
\r
515 * | :----: | :----: | :---- |
\r
516 * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit
\r
517 * | | |0 = PWMx_CH0 pin at tri-state mode.
\r
518 * | | |1 = PWMx_CH0 pin in output mode.
\r
519 * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit
\r
520 * | | |0 = PWMx_CH1 pin at tri-state mode.
\r
521 * | | |1 = PWMx_CH1 pin in output mode.
\r
522 * @var TIMER_T::PWMSWBRK
\r
523 * Offset: 0x7C Timer PWM Software Trigger Brake Control Register
\r
524 * ---------------------------------------------------------------------------------------------------
\r
525 * |Bits |Field |Descriptions
\r
526 * | :----: | :----: | :---- |
\r
527 * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)
\r
528 * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
\r
529 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
530 * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect)
\r
531 * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
\r
532 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
533 * @var TIMER_T::PWMINTEN0
\r
534 * Offset: 0x80 Timer PWM Interrupt Enable Register 0
\r
535 * ---------------------------------------------------------------------------------------------------
\r
536 * |Bits |Field |Descriptions
\r
537 * | :----: | :----: | :---- |
\r
538 * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit
\r
539 * | | |0 = Zero point interrupt Disabled.
\r
540 * | | |1 = Zero point interrupt Enabled.
\r
541 * |[1] |PIEN |PWM Period Point Interrupt Enable Bit
\r
542 * | | |0 = Period point interrupt Disabled.
\r
543 * | | |1 = Period point interrupt Enabled.
\r
544 * | | |Note: When in up-down count type, period point means the center point of current PWM period.
\r
545 * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit
\r
546 * | | |0 = Compare up count interrupt Disabled.
\r
547 * | | |1 = Compare up count interrupt Enabled.
\r
548 * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit
\r
549 * | | |0 = Compare down count interrupt Disabled.
\r
550 * | | |1 = Compare down count interrupt Enabled.
\r
551 * @var TIMER_T::PWMINTEN1
\r
552 * Offset: 0x84 Timer PWM Interrupt Enable Register 1
\r
553 * ---------------------------------------------------------------------------------------------------
\r
554 * |Bits |Field |Descriptions
\r
555 * | :----: | :----: | :---- |
\r
556 * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect)
\r
557 * | | |0 = PWM edge-detect brake interrupt Disabled.
\r
558 * | | |1 = PWM edge-detect brake interrupt Enabled.
\r
559 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
560 * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect)
\r
561 * | | |0 = PWM level-detect brake interrupt Disabled.
\r
562 * | | |1 = PWM level-detect brake interrupt Enabled.
\r
563 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register.
\r
564 * @var TIMER_T::PWMINTSTS0
\r
565 * Offset: 0x88 Timer PWM Interrupt Status Register 0
\r
566 * ---------------------------------------------------------------------------------------------------
\r
567 * |Bits |Field |Descriptions
\r
568 * | :----: | :----: | :---- |
\r
569 * |[0] |ZIF |PWM Zero Point Interrupt Flag
\r
570 * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero.
\r
571 * | | |Note: This bit is cleared by writing 1 to it.
\r
572 * |[1] |PIF |PWM Period Point Interrupt Flag
\r
573 * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.
\r
574 * | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period.
\r
575 * | | |Note2: This bit is cleared by writing 1 to it.
\r
576 * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag
\r
577 * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.
\r
578 * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type..
\r
579 * | | |Note2: This bit is cleared by writing 1 to it.
\r
580 * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag
\r
581 * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.
\r
582 * | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.
\r
583 * | | |Note2: This bit is cleared by writing 1 to it.
\r
584 * @var TIMER_T::PWMINTSTS1
\r
585 * Offset: 0x8C Timer PWM Interrupt Status Register 1
\r
586 * ---------------------------------------------------------------------------------------------------
\r
587 * |Bits |Field |Descriptions
\r
588 * | :----: | :----: | :---- |
\r
589 * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
\r
590 * | | |0 = PWMx_CH0 edge-detect brake event do not happened.
\r
591 * | | |1 = PWMx_CH0 edge-detect brake event happened.
\r
592 * | | |Note1: This bit is cleared by writing 1 to it.
\r
593 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
\r
594 * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)
\r
595 * | | |0 = PWMx_CH1 edge-detect brake event do not happened.
\r
596 * | | |1 = PWMx_CH1 edge-detect brake event happened.
\r
597 * | | |Note1: This bit is cleared by writing 1 to it.
\r
598 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
\r
599 * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
\r
600 * | | |0 = PWMx_CH0 level-detect brake event do not happened.
\r
601 * | | |1 = PWMx_CH0 level-detect brake event happened.
\r
602 * | | |Note1: This bit is cleared by writing 1 to it.
\r
603 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
\r
604 * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)
\r
605 * | | |0 = PWMx_CH1 level-detect brake event do not happened.
\r
606 * | | |1 = PWMx_CH1 level-detect brake event happened.
\r
607 * | | |Note1: This bit is cleared by writing 1 to it.
\r
608 * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register.
\r
609 * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only)
\r
610 * | | |0 = PWMx_CH0 edge-detect brake state is released.
\r
611 * | | |1 = PWMx_CH0 at edge-detect brake state.
\r
612 * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period.
\r
613 * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only)
\r
614 * | | |0 = PWMx_CH1 edge-detect brake state is released.
\r
615 * | | |1 = PWMx_CH1 at edge-detect brake state.
\r
616 * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period.
\r
617 * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only)
\r
618 * | | |0 = PWMx_CH0 level-detect brake state is released.
\r
619 * | | |1 = PWMx_CH0 at level-detect brake state.
\r
620 * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
\r
621 * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only)
\r
622 * | | |0 = PWMx_CH1 level-detect brake state is released.
\r
623 * | | |1 = PWMx_CH1 at level-detect brake state.
\r
624 * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
\r
625 * @var TIMER_T::PWMEADCTS
\r
626 * Offset: 0x90 Timer PWM ADC Trigger Source Select Register
\r
627 * ---------------------------------------------------------------------------------------------------
\r
628 * |Bits |Field |Descriptions
\r
629 * | :----: | :----: | :---- |
\r
630 * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion
\r
631 * | | |000 = Trigger EADC conversion at zero point (ZIF).
\r
632 * | | |001 = Trigger EADC conversion at period point (PIF).
\r
633 * | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF).
\r
634 * | | |011 = Trigger EADC conversion at compare up count point (CMPUIF).
\r
635 * | | |100 = Trigger EADC conversion at compare down count point (CMPDIF).
\r
636 * | | |Others = Reserved.
\r
637 * |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit
\r
638 * | | |0 = PWM counter event trigger EADC conversion Disabled.
\r
639 * | | |1 = PWM counter event trigger EADC conversion Enabled.
\r
640 * @var TIMER_T::PWMSCTL
\r
641 * Offset: 0x94 Timer PWM Synchronous Control Register
\r
642 * ---------------------------------------------------------------------------------------------------
\r
643 * |Bits |Field |Descriptions
\r
644 * | :----: | :----: | :---- |
\r
645 * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select
\r
646 * | | |00 = PWM synchronous function Disabled.
\r
647 * | | |01 = PWM synchronous counter start function Enabled.
\r
648 * | | |10 = Reserved.
\r
649 * | | |11 = PWM synchronous counter clear function Enabled.
\r
650 * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select
\r
651 * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN.
\r
652 * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN.
\r
653 * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.
\r
654 * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.
\r
655 * @var TIMER_T::PWMSTRG
\r
656 * Offset: 0x98 Timer PWM Synchronous Trigger Register
\r
657 * ---------------------------------------------------------------------------------------------------
\r
658 * |Bits |Field |Descriptions
\r
659 * | :----: | :----: | :---- |
\r
660 * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only)
\r
661 * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.
\r
662 * | | |Note: This bit is only available in TIMER0 and TIMER2.
\r
663 * @var TIMER_T::PWMSTATUS
\r
664 * Offset: 0x9C Timer PWM Status Register
\r
665 * ---------------------------------------------------------------------------------------------------
\r
666 * |Bits |Field |Descriptions
\r
667 * | :----: | :----: | :---- |
\r
668 * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag
\r
669 * | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF.
\r
670 * | | |1 = Indicates the PWM counter value has reached its maximum value.
\r
671 * | | |Note: This bit is cleared by writing 1 to it.
\r
672 * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag
\r
673 * | | |0 = PWM counter event trigger EADC start conversion is not occurred.
\r
674 * | | |1 = PWM counter event trigger EADC start conversion has occurred.
\r
675 * | | |Note: This bit is cleared by writing 1 to it.
\r
676 * @var TIMER_T::PWMPBUF
\r
677 * Offset: 0xA0 Timer PWM Period Buffer Register
\r
678 * ---------------------------------------------------------------------------------------------------
\r
679 * |Bits |Field |Descriptions
\r
680 * | :----: | :----: | :---- |
\r
681 * |[15:0] |PBUF |PWM Period Buffer Register (Read Only)
\r
682 * | | |Used as PERIOD active register.
\r
683 * @var TIMER_T::PWMCMPBUF
\r
684 * Offset: 0xA4 Timer PWM Comparator Buffer Register
\r
685 * ---------------------------------------------------------------------------------------------------
\r
686 * |Bits |Field |Descriptions
\r
687 * | :----: | :----: | :---- |
\r
688 * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only)
\r
689 * | | |Used as CMP active register.
\r
691 __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */
\r
692 __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */
\r
693 __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */
\r
694 __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */
\r
695 __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */
\r
696 __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */
\r
697 __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */
\r
698 __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */
\r
699 __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */
\r
700 __I uint32_t RESERVE0[7];
\r
701 __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */
\r
702 __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */
\r
703 __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */
\r
704 __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */
\r
705 __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */
\r
706 __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */
\r
707 __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */
\r
708 __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */
\r
709 __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */
\r
710 __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */
\r
711 __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */
\r
712 __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */
\r
713 __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */
\r
714 __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */
\r
715 __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */
\r
716 __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */
\r
717 __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */
\r
718 __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */
\r
719 __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */
\r
720 __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */
\r
721 __IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM ADC Trigger Source Select Register */
\r
722 __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */
\r
723 __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */
\r
724 __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */
\r
725 __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */
\r
726 __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */
\r
731 @addtogroup TIMER_CONST TIMER Bit Field Definition
\r
732 Constant Definitions for TIMER Controller
\r
735 #define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
\r
736 #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
\r
738 #define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */
\r
739 #define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */
\r
741 #define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */
\r
742 #define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */
\r
744 #define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */
\r
745 #define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
\r
747 #define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */
\r
748 #define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */
\r
750 #define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
\r
751 #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
\r
753 #define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
\r
754 #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
\r
756 #define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
\r
757 #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
\r
759 #define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
\r
760 #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
\r
762 #define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
\r
763 #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
\r
765 #define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
\r
766 #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
\r
768 #define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
\r
769 #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
\r
771 #define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
\r
772 #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
\r
774 #define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
\r
775 #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
\r
777 #define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
\r
778 #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
\r
780 #define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
\r
781 #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
\r
783 #define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */
\r
784 #define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */
\r
786 #define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
\r
787 #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
\r
789 #define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
\r
790 #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
\r
792 #define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
\r
793 #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
\r
795 #define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
\r
796 #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
\r
798 #define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
\r
799 #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
\r
801 #define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
\r
802 #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
\r
804 #define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
\r
805 #define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
\r
807 #define TIMER_EXTCTL_ACMPSSEL_Pos (8) /*!< TIMER_T::EXTCTL: ACMPSSEL Position */
\r
808 #define TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos) /*!< TIMER_T::EXTCTL: ACMPSSEL Mask */
\r
810 #define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
\r
811 #define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
\r
813 #define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */
\r
814 #define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */
\r
816 #define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
\r
817 #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
\r
819 #define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */
\r
820 #define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */
\r
822 #define TIMER_TRGCTL_TRGEPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGEPWM Position */
\r
823 #define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) /*!< TIMER_T::TRGCTL: TRGEPWM Mask */
\r
825 #define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */
\r
826 #define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */
\r
828 #define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */
\r
829 #define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */
\r
831 #define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */
\r
832 #define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */
\r
834 #define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */
\r
835 #define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */
\r
837 #define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */
\r
838 #define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */
\r
840 #define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */
\r
841 #define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */
\r
843 #define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */
\r
844 #define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */
\r
846 #define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */
\r
847 #define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */
\r
849 #define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */
\r
850 #define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */
\r
852 #define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */
\r
853 #define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */
\r
855 #define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */
\r
856 #define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */
\r
858 #define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */
\r
859 #define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */
\r
861 #define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */
\r
862 #define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */
\r
864 #define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */
\r
865 #define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */
\r
867 #define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */
\r
868 #define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */
\r
870 #define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */
\r
871 #define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */
\r
873 #define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */
\r
874 #define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */
\r
876 #define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */
\r
877 #define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */
\r
879 #define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */
\r
880 #define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */
\r
882 #define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */
\r
883 #define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */
\r
885 #define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */
\r
886 #define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */
\r
888 #define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */
\r
889 #define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */
\r
891 #define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */
\r
892 #define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */
\r
894 #define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */
\r
895 #define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */
\r
897 #define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */
\r
898 #define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */
\r
900 #define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */
\r
901 #define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */
\r
903 #define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */
\r
904 #define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */
\r
906 #define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */
\r
907 #define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */
\r
909 #define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */
\r
910 #define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */
\r
912 #define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */
\r
913 #define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */
\r
915 #define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */
\r
916 #define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */
\r
918 #define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */
\r
919 #define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */
\r
921 #define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */
\r
922 #define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */
\r
924 #define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */
\r
925 #define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */
\r
927 #define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */
\r
928 #define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */
\r
930 #define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */
\r
931 #define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */
\r
933 #define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */
\r
934 #define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */
\r
936 #define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */
\r
937 #define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */
\r
939 #define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */
\r
940 #define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */
\r
942 #define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */
\r
943 #define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */
\r
945 #define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */
\r
946 #define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */
\r
948 #define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */
\r
949 #define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */
\r
951 #define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */
\r
952 #define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */
\r
954 #define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */
\r
955 #define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */
\r
957 #define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */
\r
958 #define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */
\r
960 #define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */
\r
961 #define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */
\r
963 #define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */
\r
964 #define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */
\r
966 #define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */
\r
967 #define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */
\r
969 #define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */
\r
970 #define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */
\r
972 #define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */
\r
973 #define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */
\r
975 #define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */
\r
976 #define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */
\r
978 #define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */
\r
979 #define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */
\r
981 #define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */
\r
982 #define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */
\r
984 #define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */
\r
985 #define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */
\r
987 #define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */
\r
988 #define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */
\r
990 #define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */
\r
991 #define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */
\r
993 #define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */
\r
994 #define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */
\r
996 #define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */
\r
997 #define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */
\r
999 #define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */
\r
1000 #define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */
\r
1002 #define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */
\r
1003 #define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */
\r
1005 #define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */
\r
1006 #define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */
\r
1008 #define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */
\r
1009 #define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */
\r
1011 #define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */
\r
1012 #define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */
\r
1014 #define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */
\r
1015 #define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */
\r
1017 #define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */
\r
1018 #define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */
\r
1020 #define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */
\r
1021 #define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */
\r
1023 #define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */
\r
1024 #define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */
\r
1026 #define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */
\r
1027 #define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */
\r
1029 #define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */
\r
1030 #define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */
\r
1032 #define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */
\r
1033 #define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */
\r
1035 #define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */
\r
1036 #define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */
\r
1038 #define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */
\r
1039 #define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */
\r
1041 #define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */
\r
1042 #define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */
\r
1044 #define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */
\r
1045 #define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */
\r
1047 #define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */
\r
1048 #define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */
\r
1050 #define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */
\r
1051 #define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */
\r
1053 #define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */
\r
1054 #define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */
\r
1056 #define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */
\r
1057 #define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */
\r
1059 /**@}*/ /* TIMER_CONST */
\r
1060 /**@}*/ /* end of TIMER register group */
\r
1061 /**@}*/ /* end of REGISTER group */
\r
1063 #endif /* __TIMER_REG_H__ */
\r
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