1 /**************************************************************************//**
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4 * @brief UI2C register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __UI2C_REG_H__
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9 #define __UI2C_REG_H__
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11 /** @addtogroup REGISTER Control Register
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17 /*---------------------- I2C Mode of USCI Controller -------------------------*/
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19 @addtogroup UI2C I2C Mode of USCI Controller(UI2C)
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20 Memory Mapped Structure for UI2C Controller
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29 * Offset: 0x00 USCI Control Register
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30 * ---------------------------------------------------------------------------------------------------
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31 * |Bits |Field |Descriptions
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32 * | :----: | :----: | :---- |
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33 * |[2:0] |FUNMODE |Function Mode
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34 * | | |This bit field selects the protocol for this USCI controller
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35 * | | |Selecting a protocol that is not available or a reserved combination disables the USCI
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36 * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
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37 * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
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38 * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state.
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39 * | | |001 = The SPI protocol is selected.
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40 * | | |010 = The UART protocol is selected.
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41 * | | |100 = The I2C protocol is selected.
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42 * | | |Note: Other bit combinations are reserved.
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43 * @var UI2C_T::BRGEN
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44 * Offset: 0x08 USCI Baud Rate Generator Register
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45 * ---------------------------------------------------------------------------------------------------
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46 * |Bits |Field |Descriptions
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47 * | :----: | :----: | :---- |
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48 * |[0] |RCLKSEL |Reference Clock Source Selection
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49 * | | |This bit selects the source signal of reference clock (fREF_CLK).
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50 * | | |0 = Peripheral device clock fPCLK.
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51 * | | |1 = Reserved.
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52 * |[1] |PTCLKSEL |Protocol Clock Source Selection
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53 * | | |This bit selects the source signal of protocol clock (fPROT_CLK).
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54 * | | |0 = Reference clock fREF_CLK.
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55 * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
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56 * |[3:2] |SPCLKSEL |Sample Clock Source Selection
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57 * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
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58 * | | |00 = fSAMP_CLK = fDIV_CLK.
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59 * | | |01 = fSAMP_CLK = fPROT_CLK.
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60 * | | |10 = fSAMP_CLK = fSCLK.
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61 * | | |11 = fSAMP_CLK = fREF_CLK.
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62 * |[4] |TMCNTEN |Time Measurement Counter Enable Bit
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63 * | | |This bit enables the 10-bit timing measurement counter.
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64 * | | |0 = Time measurement counter is Disabled.
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65 * | | |1 = Time measurement counter is Enabled.
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66 * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection
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67 * | | |0 = Time measurement counter with fPROT_CLK.
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68 * | | |1 = Time measurement counter with fDIV_CLK.
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69 * |[9:8] |PDSCNT |Pre-divider for Sample Counter
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70 * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
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71 * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
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72 * |[14:10] |DSCNT |Denominator for Sample Counter
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73 * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
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74 * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
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75 * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
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76 * |[25:16] |CLKDIV |Clock Divider
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77 * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
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78 * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled
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79 * | | |The revised value is the average bit time between bit 5 and bit 6
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80 * | | |The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate.
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81 * @var UI2C_T::LINECTL
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82 * Offset: 0x2C USCI Line Control Register
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83 * ---------------------------------------------------------------------------------------------------
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84 * |Bits |Field |Descriptions
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85 * | :----: | :----: | :---- |
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86 * |[0] |LSB |LSB First Transmission Selection
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87 * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
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88 * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
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89 * |[11:8] |DWIDTH |Word Length of Transmission
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90 * | | |This bit field defines the data word length (amount of bits) for reception and transmission
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91 * | | |The data word is always right-aligned in the data buffer
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92 * | | |USCI support word length from 4 to 16 bits.
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93 * | | |0x0: The data word contains 16 bits located at bit positions [15:0].
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94 * | | |0x1: Reserved.
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95 * | | |0x2: Reserved.
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96 * | | |0x3: Reserved.
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97 * | | |0x4: The data word contains 4 bits located at bit positions [3:0].
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98 * | | |0x5: The data word contains 5 bits located at bit positions [4:0].
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100 * | | |0xF: The data word contains 15 bits located at bit positions [14:0].
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101 * | | |Note: In UART protocol, the length can be configured as 6~13 bits.
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102 * @var UI2C_T::TXDAT
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103 * Offset: 0x30 USCI Transmit Data Register
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104 * ---------------------------------------------------------------------------------------------------
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105 * |Bits |Field |Descriptions
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106 * | :----: | :----: | :---- |
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107 * |[15:0] |TXDAT |Transmit Data
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108 * | | |Software can use this bit field to write 16-bit transmit data for transmission.
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109 * @var UI2C_T::RXDAT
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110 * Offset: 0x34 USCI Receive Data Register
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111 * ---------------------------------------------------------------------------------------------------
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112 * |Bits |Field |Descriptions
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113 * | :----: | :----: | :---- |
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114 * |[15:0] |RXDAT |Received Data
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115 * | | |This bit field monitors the received data which stored in receive data buffer.
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116 * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
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117 * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UI2C_PROTSTS[7:5]).
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118 * @var UI2C_T::DEVADDR0
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119 * Offset: 0x44 USCI Device Address Register 0
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120 * ---------------------------------------------------------------------------------------------------
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121 * |Bits |Field |Descriptions
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122 * | :----: | :----: | :---- |
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123 * |[9:0] |DEVADDR |Device Address
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124 * | | |In I2C protocol, this bit field contains the programmed slave address
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125 * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
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126 * | | |Then the second address byte is also compared to DEVADDR[7:0].
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127 * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
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128 * @var UI2C_T::DEVADDR1
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129 * Offset: 0x48 USCI Device Address Register 1
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130 * ---------------------------------------------------------------------------------------------------
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131 * |Bits |Field |Descriptions
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132 * | :----: | :----: | :---- |
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133 * |[9:0] |DEVADDR |Device Address
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134 * | | |In I2C protocol, this bit field contains the programmed slave address
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135 * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
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136 * | | |Then the second address byte is also compared to DEVADDR[7:0].
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137 * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.
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138 * @var UI2C_T::ADDRMSK0
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139 * Offset: 0x4C USCI Device Address Mask Register 0
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140 * ---------------------------------------------------------------------------------------------------
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141 * |Bits |Field |Descriptions
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142 * | :----: | :----: | :---- |
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143 * |[9:0] |ADDRMSK |USCI Device Address Mask
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144 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
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145 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
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146 * | | |USCI support multiple address recognition with two address mask register
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147 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
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148 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
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149 * | | |Note: The wake-up function can not set address mask.
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150 * @var UI2C_T::ADDRMSK1
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151 * Offset: 0x50 USCI Device Address Mask Register 1
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152 * ---------------------------------------------------------------------------------------------------
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153 * |Bits |Field |Descriptions
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154 * | :----: | :----: | :---- |
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155 * |[9:0] |ADDRMSK |USCI Device Address Mask
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156 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
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157 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
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158 * | | |USCI support multiple address recognition with two address mask register
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159 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
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160 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
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161 * | | |Note: The wake-up function can not set address mask.
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162 * @var UI2C_T::WKCTL
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163 * Offset: 0x54 USCI Wake-up Control Register
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164 * ---------------------------------------------------------------------------------------------------
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165 * |Bits |Field |Descriptions
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166 * | :----: | :----: | :---- |
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167 * |[0] |WKEN |Wake-up Enable Bit
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168 * | | |0 = Wake-up function Disabled.
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169 * | | |1 = Wake-up function Enabled.
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170 * |[1] |WKADDREN |Wake-up Address Match Enable Bit
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171 * | | |0 = The chip is woken up according data toggle.
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172 * | | |1 = The chip is woken up according address match.
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173 * @var UI2C_T::WKSTS
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174 * Offset: 0x58 USCI Wake-up Status Register
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175 * ---------------------------------------------------------------------------------------------------
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176 * |Bits |Field |Descriptions
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177 * | :----: | :----: | :---- |
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178 * |[0] |WKF |Wake-up Flag
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179 * | | |When chip is woken up from Power-down mode, this bit is set to 1
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180 * | | |Software can write 1 to clear this bit.
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181 * @var UI2C_T::PROTCTL
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182 * Offset: 0x5C USCI Protocol Control Register
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183 * ---------------------------------------------------------------------------------------------------
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184 * |Bits |Field |Descriptions
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185 * | :----: | :----: | :---- |
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186 * |[0] |GCFUNC |General Call Function
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187 * | | |0 = General Call Function Disabled.
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188 * | | |1 = General Call Function Enabled.
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189 * |[1] |AA |Assert Acknowledge Control
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190 * | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
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191 * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
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192 * |[2] |STO |I2C STOP Control
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193 * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically
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194 * | | |In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode when bus error (UI2C_PROTSTS.ERRIF = 1).
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195 * |[3] |STA |I2C START Control
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196 * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
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197 * |[4] |ADDR10EN |Address 10-bit Function Enable Bit
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198 * | | |0 = Address match 10 bit function is disabled.
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199 * | | |1 = Address match 10 bit function is enabled.
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200 * |[5] |PTRG |I2C Protocol Trigger (Write Only)
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201 * | | |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested
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202 * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
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203 * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead.
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204 * | | |1 = I2C's stretch active.
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205 * |[8] |SCLOUTEN |SCL Output Enable Bit
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206 * | | |This bit enables monitor pulling SCL to low
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207 * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
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208 * | | |0 = SCL output will be forced high due to open drain mechanism.
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209 * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.
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210 * |[9] |MONEN |Monitor Mode Enable Bit
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211 * | | |This bit enables monitor mode
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212 * | | |In monitor mode the SDA output will be put in high impedance mode
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213 * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
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214 * | | |0 = The monitor mode is disabled.
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215 * | | |1 = The monitor mode is enabled.
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216 * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
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217 * |[25:16] |TOCNT |Time-out Clock Cycle
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218 * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear
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219 * | | |The time-out is enable when TOCNT bigger than 0.
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220 * | | |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
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221 * |[31] |PROTEN |I2C Protocol Enable Bit
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222 * | | |0 = I2C Protocol disable.
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223 * | | |1 = I2C Protocol enable.
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224 * @var UI2C_T::PROTIEN
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225 * Offset: 0x60 USCI Protocol Interrupt Enable Register
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226 * ---------------------------------------------------------------------------------------------------
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227 * |Bits |Field |Descriptions
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228 * | :----: | :----: | :---- |
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229 * |[0] |TOIEN |Time-out Interrupt Enable Control
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230 * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
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231 * | | |0 = The time-out interrupt is disabled.
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232 * | | |1 = The time-out interrupt is enabled.
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233 * |[1] |STARIEN |Start Condition Received Interrupt Enable Control
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234 * | | |This bit enables the generation of a protocol interrupt if a start condition is detected.
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235 * | | |0 = The start condition interrupt is disabled.
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236 * | | |1 = The start condition interrupt is enabled.
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237 * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control
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238 * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected.
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239 * | | |0 = The stop condition interrupt is disabled.
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240 * | | |1 = The stop condition interrupt is enabled.
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241 * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control
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242 * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
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243 * | | |0 = The non - acknowledge interrupt is disabled.
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244 * | | |1 = The non - acknowledge interrupt is enabled.
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245 * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control
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246 * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
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247 * | | |0 = The arbitration lost interrupt is disabled.
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248 * | | |1 = The arbitration lost interrupt is enabled.
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249 * |[5] |ERRIEN |Error Interrupt Enable Control
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250 * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
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251 * | | |0 = The error interrupt is disabled.
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252 * | | |1 = The error interrupt is enabled.
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253 * |[6] |ACKIEN |Acknowledge Interrupt Enable Control
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254 * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
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255 * | | |0 = The acknowledge interrupt is disabled.
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256 * | | |1 = The acknowledge interrupt is enabled.
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257 * @var UI2C_T::PROTSTS
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258 * Offset: 0x64 USCI Protocol Status Register
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259 * ---------------------------------------------------------------------------------------------------
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260 * |Bits |Field |Descriptions
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261 * | :----: | :----: | :---- |
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262 * |[5] |TOIF |Time-out Interrupt Flag
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263 * | | |0 = A time-out interrupt status has not occurred.
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264 * | | |1 = A time-out interrupt status has occurred.
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265 * | | |Note: It is cleared by software writing one into this bit
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266 * |[6] |ONBUSY |On Bus Busy
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267 * | | |Indicates that a communication is in progress on the bus
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268 * | | |It is set by hardware when a START condition is detected
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269 * | | |It is cleared by hardware when a STOP condition is detected
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270 * | | |0 = The bus is IDLE (both SCLK and SDA High).
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271 * | | |1 = The bus is busy.
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272 * |[8] |STARIF |Start Condition Received Interrupt Flag
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273 * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode
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274 * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode.
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275 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1.
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276 * | | |0 = A start condition has not yet been detected.
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277 * | | |1 = A start condition has been detected.
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278 * | | |It is cleared by software writing one into this bit
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279 * |[9] |STORIF |Stop Condition Received Interrupt Flag
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280 * | | |This bit indicates that a stop condition has been detected on the I2C bus lines
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281 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1.
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282 * | | |0 = A stop condition has not yet been detected.
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283 * | | |1 = A stop condition has been detected.
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284 * | | |It is cleared by software writing one into this bit
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285 * | | |Note: This bit is set when slave RX mode.
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286 * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag
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287 * | | |This bit indicates that a non - acknowledge has been received in master mode
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288 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1.
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289 * | | |0 = A non - acknowledge has not been received.
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290 * | | |1 = A non - acknowledge has been received.
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291 * | | |It is cleared by software writing one into this bit
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292 * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag
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293 * | | |This bit indicates that an arbitration has been lost
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294 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1.
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295 * | | |0 = An arbitration has not been lost.
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296 * | | |1 = An arbitration has been lost.
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297 * | | |It is cleared by software writing one into this bit
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298 * |[12] |ERRIF |Error Interrupt Flag
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299 * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
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300 * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit
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301 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1.
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302 * | | |0 = An I2C error has not been detected.
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303 * | | |1 = An I2C error has been detected.
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304 * | | |It is cleared by software writing one into this bit
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305 * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined not addressed slave mode.
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306 * |[13] |ACKIF |Acknowledge Received Interrupt Flag
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307 * | | |This bit indicates that an acknowledge has been received in master mode
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308 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1.
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309 * | | |0 = An acknowledge has not been received.
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310 * | | |1 = An acknowledge has been received.
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311 * | | |It is cleared by software writing one into this bit
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312 * |[14] |SLASEL |Slave Select Status
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313 * | | |This bit indicates that this device has been selected as slave.
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314 * | | |0 = The device is not selected as slave.
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315 * | | |1 = The device is selected as slave.
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316 * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
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317 * |[15] |SLAREAD |Slave Read Request Status
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318 * | | |This bit indicates that a slave read request has been detected.
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319 * | | |0 = A slave R/W bit is 1 has not been detected.
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320 * | | |1 = A slave R/W bit is 1 has been detected.
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321 * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
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322 * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done
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323 * | | |0 = The ACK bit cycle of address match frame isn't done.
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324 * | | |1 = The ACK bit cycle of address match frame is done in power-down.
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325 * | | |Note: This bit can't release when WKUPIF is set.
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326 * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame
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327 * | | |0 = Write command be record on the address match wakeup frame.
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328 * | | |1 = Read command be record on the address match wakeup frame.
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329 * |[18] |BUSHANG |Bus Hang-up
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330 * | | |This bit indicates bus hang-up status
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331 * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK
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332 * | | |The hang-up counter will count to overflow and set this bit when SDA is low
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333 * | | |The counter will be reset by falling edge of SCL signal.
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334 * | | |0 = The bus is normal status for transmission.
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335 * | | |1 = The bus is hang-up status for transmission.
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336 * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
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337 * |[19] |ERRARBLO |Error Arbitration Lost
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338 * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor
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339 * | | |The I2C can send start condition when ERRARBLO is set
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340 * | | |Thus this bit doesn't be cared on slave mode.
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341 * | | |0 = The bus is normal status for transmission.
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342 * | | |1 = The bus is error arbitration lost status for transmission.
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343 * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
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344 * @var UI2C_T::ADMAT
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345 * Offset: 0x88 I2C Slave Match Address Register
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346 * ---------------------------------------------------------------------------------------------------
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347 * |Bits |Field |Descriptions
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348 * | :----: | :----: | :---- |
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349 * |[0] |ADMAT0 |USCI Address 0 Match Status Register
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350 * | | |When address 0 is matched, hardware will inform which address used
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351 * | | |This bit will set to 1, and software can write 1 to clear this bit.
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352 * |[1] |ADMAT1 |USCI Address 1 Match Status Register
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353 * | | |When address 1 is matched, hardware will inform which address used
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354 * | | |This bit will set to 1, and software can write 1 to clear this bit.
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355 * @var UI2C_T::TMCTL
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356 * Offset: 0x8C I2C Timing Configure Control Register
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357 * ---------------------------------------------------------------------------------------------------
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358 * |Bits |Field |Descriptions
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359 * | :----: | :----: | :---- |
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360 * |[8:0] |STCTL |Setup Time Configure Control Register
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361 * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
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362 * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.
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363 * |[24:16] |HTCTL |Hold Time Configure Control Register
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364 * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in
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365 * | | |transmission mode.
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366 * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.
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368 __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */
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369 __I uint32_t RESERVE0[1];
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370 __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */
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371 __I uint32_t RESERVE1[8];
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372 __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */
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373 __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */
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374 __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */
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375 __I uint32_t RESERVE2[3];
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376 __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */
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377 __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */
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378 __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */
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379 __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */
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380 __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */
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381 __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */
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382 __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */
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383 __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */
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384 __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */
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385 __I uint32_t RESERVE3[8];
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386 __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */
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387 __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */
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392 @addtogroup UI2C_CONST UI2C Bit Field Definition
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393 Constant Definitions for UI2C Controller
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396 #define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */
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397 #define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */
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399 #define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */
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400 #define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */
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402 #define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */
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403 #define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */
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405 #define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */
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406 #define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */
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408 #define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */
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409 #define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */
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411 #define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */
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412 #define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */
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414 #define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */
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415 #define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */
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417 #define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */
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418 #define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */
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420 #define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */
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421 #define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */
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423 #define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */
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424 #define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */
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426 #define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */
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427 #define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */
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429 #define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */
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430 #define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */
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432 #define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */
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433 #define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */
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435 #define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */
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436 #define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */
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438 #define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */
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439 #define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */
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441 #define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */
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442 #define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */
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444 #define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */
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445 #define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */
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447 #define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */
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448 #define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */
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450 #define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */
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451 #define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */
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453 #define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */
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454 #define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */
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456 #define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */
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457 #define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */
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459 #define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */
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460 #define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */
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462 #define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */
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463 #define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */
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465 #define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */
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466 #define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */
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468 #define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */
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469 #define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */
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471 #define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */
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472 #define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */
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474 #define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */
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475 #define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */
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477 #define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */
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478 #define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */
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480 #define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */
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481 #define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */
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483 #define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */
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484 #define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */
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486 #define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */
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487 #define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */
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489 #define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */
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490 #define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */
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492 #define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */
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493 #define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */
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495 #define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */
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496 #define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */
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498 #define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */
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499 #define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */
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501 #define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */
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502 #define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */
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504 #define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */
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505 #define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */
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507 #define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */
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508 #define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */
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510 #define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */
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511 #define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */
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513 #define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */
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514 #define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */
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516 #define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */
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517 #define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */
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519 #define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */
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520 #define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */
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522 #define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */
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523 #define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */
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525 #define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */
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526 #define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */
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528 #define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */
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529 #define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */
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531 #define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */
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532 #define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */
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534 #define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */
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535 #define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */
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537 #define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */
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538 #define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */
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540 #define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */
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541 #define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */
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543 #define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */
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544 #define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */
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546 #define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */
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547 #define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */
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549 #define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */
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550 #define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */
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552 #define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */
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553 #define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */
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555 #define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */
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556 #define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */
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558 #define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */
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559 #define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */
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561 /**@}*/ /* UI2C_CONST */
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562 /**@}*/ /* end of UI2C register group */
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563 /**@}*/ /* end of REGISTER group */
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565 #endif /* __UI2C_REG_H__ */
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