1 /**************************************************************************//**
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4 * @brief USBD register definition header file
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6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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7 *****************************************************************************/
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8 #ifndef __USBD_REG_H__
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9 #define __USBD_REG_H__
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11 /** @addtogroup REGISTER Control Register
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17 /*---------------------- USB Device Controller -------------------------*/
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19 @addtogroup USBD USB Device Controller(USBD)
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20 Memory Mapped Structure for USBD Controller
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26 * @brief USBD endpoints register
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31 * @var USBD_EP_T::BUFSEG
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32 * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570/0x580/0x590/0x5A0/0x5B0 Endpoint Buffer Segmentation Register
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33 * ---------------------------------------------------------------------------------------------------
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34 * |Bits |Field |Descriptions
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35 * | :----: | :----: | :---- |
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36 * |[8:3] |BUFSEG |Endpoint Buffer Segmentation
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37 * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
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38 * | | |USBD_SRAM address + { BUFSEG, 3'b000}
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39 * | | |Where the USBD_SRAM address = USBD_BA+0x100h.
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40 * | | |Refer to the section 6.29.5.7 for the endpoint SRAM structure and its description.
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41 * @var USBD_EP_T::MXPLD
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42 * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574/0x584/0x594/0x5A4/0x5B4 Endpoint Maximal Payload Register
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43 * ---------------------------------------------------------------------------------------------------
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44 * |Bits |Field |Descriptions
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45 * | :----: | :----: | :---- |
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46 * |[8:0] |MXPLD |Maximal Payload
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47 * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
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48 * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
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49 * | | |(1) When the register is written by CPU,
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50 * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
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51 * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
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52 * | | |(2) When the register is read by CPU,
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53 * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
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54 * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
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55 * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
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56 * @var USBD_EP_T::CFG
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57 * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578/0x588/0x598/0x5A8/0x5B8 Endpoint Configuration Register
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58 * ---------------------------------------------------------------------------------------------------
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59 * |Bits |Field |Descriptions
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60 * | :----: | :----: | :---- |
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61 * |[3:0] |EPNUM |Endpoint Number
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62 * | | |These bits are used to define the endpoint number of the current endpoint
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63 * |[4] |ISOCH |Isochronous Endpoint
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64 * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
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65 * | | |0 = No Isochronous endpoint.
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66 * | | |1 = Isochronous endpoint.
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67 * |[6:5] |STATE |Endpoint STATE
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68 * | | |00 = Endpoint is Disabled.
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69 * | | |01 = Out endpoint.
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70 * | | |10 = IN endpoint.
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71 * | | |11 = Undefined.
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72 * |[7] |DSQSYNC |Data Sequence Synchronization
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73 * | | |0 = DATA0 PID.
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74 * | | |1 = DATA1 PID.
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75 * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction
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76 * | | |hardware will toggle automatically in IN token base on the bit.
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77 * |[9] |CSTALL |Clear STALL Response
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78 * | | |0 = Disable the device to clear the STALL handshake in setup stage.
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79 * | | |1 = Clear the device to response STALL handshake in setup stage.
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80 * @var USBD_EP_T::CFGP
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81 * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C/0x58C/0x59C/0x5AC/0x5BC Endpoint Set Stall and Clear In/Out Ready Control Register
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82 * ---------------------------------------------------------------------------------------------------
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83 * |Bits |Field |Descriptions
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84 * | :----: | :----: | :---- |
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85 * |[0] |CLRRDY |Clear Ready
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86 * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data
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87 * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.
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88 * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
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89 * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
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90 * | | |This bit is write 1 only and is always 0 when it is read back.
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91 * |[1] |SSTALL |Set STALL
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92 * | | |0 = Disable the device to response STALL.
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93 * | | |1 = Set the device to respond STALL automatically.
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95 __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint Buffer Segmentation Register */
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96 __IO uint32_t MXPLD; /*!< [0x0004] Endpoint Maximal Payload Register */
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97 __IO uint32_t CFG; /*!< [0x0008] Endpoint Configuration Register */
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98 __IO uint32_t CFGP; /*!< [0x000c] Endpoint Set Stall and Clear In/Out Ready Control Register */
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107 * @var USBD_T::INTEN
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108 * Offset: 0x00 USB Device Interrupt Enable Register
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109 * ---------------------------------------------------------------------------------------------------
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110 * |Bits |Field |Descriptions
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111 * | :----: | :----: | :---- |
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112 * |[0] |BUSIEN |Bus Event Interrupt Enable Bit
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113 * | | |0 = BUS event interrupt Disabled.
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114 * | | |1 = BUS event interrupt Enabled.
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115 * |[1] |USBIEN |USB Event Interrupt Enable Bit
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116 * | | |0 = USB event interrupt Disabled.
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117 * | | |1 = USB event interrupt Enabled.
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118 * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit
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119 * | | |0 = VBUS detection Interrupt Disabled.
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120 * | | |1 = VBUS detection Interrupt Enabled.
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121 * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit
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122 * | | |0 = No-event-wake-up Interrupt Disabled.
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123 * | | |1 = No-event-wake-up Interrupt Enabled.
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124 * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit
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125 * | | |0 = SOF Interrupt Disabled.
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126 * | | |1 = SOF Interrupt Enabled.
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127 * |[8] |WKEN |Wake-up Function Enable Bit
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128 * | | |0 = USB wake-up function Disabled.
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129 * | | |1 = USB wake-up function Enabled.
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130 * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token
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131 * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted.
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132 * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.
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133 * @var USBD_T::INTSTS
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134 * Offset: 0x04 USB Device Interrupt Event Status Register
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135 * ---------------------------------------------------------------------------------------------------
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136 * |Bits |Field |Descriptions
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137 * | :----: | :----: | :---- |
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138 * |[0] |BUSIF |BUS Interrupt Status
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139 * | | |The BUS event means that there is one of the suspense or the resume function in the bus.
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140 * | | |0 = No BUS event occurred.
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141 * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0].
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142 * |[1] |USBIF |USB Event Interrupt Status
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143 * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
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144 * | | |0 = No USB event occurred.
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145 * | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).
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146 * |[2] |VBDETIF |VBUS Detection Interrupt Status
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147 * | | |0 = There is not attached/detached event in the USB.
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148 * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2].
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149 * |[3] |NEVWKIF |No-event-wake-up Interrupt Status
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150 * | | |0 = NEVWK event does not occur.
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151 * | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3].
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152 * |[4] |SOFIF |Start of Frame Interrupt Status
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153 * | | |0 = SOF event does not occur.
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154 * | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].
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155 * |[16] |EPEVT0 |Endpoint 0's USB Event Status
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156 * | | |0 = No event occurred in endpoint 0.
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157 * | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1].
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158 * |[17] |EPEVT1 |Endpoint 1's USB Event Status
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159 * | | |0 = No event occurred in endpoint 1.
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160 * | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1].
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161 * |[18] |EPEVT2 |Endpoint 2's USB Event Status
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162 * | | |0 = No event occurred in endpoint 2.
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163 * | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
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164 * |[19] |EPEVT3 |Endpoint 3's USB Event Status
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165 * | | |0 = No event occurred in endpoint 3.
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166 * | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1].
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167 * |[20] |EPEVT4 |Endpoint 4's USB Event Status
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168 * | | |0 = No event occurred in endpoint 4.
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169 * | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1].
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170 * |[21] |EPEVT5 |Endpoint 5's USB Event Status
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171 * | | |0 = No event occurred in endpoint 5.
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172 * | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1].
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173 * |[22] |EPEVT6 |Endpoint 6's USB Event Status
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174 * | | |0 = No event occurred in endpoint 6.
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175 * | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
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176 * |[23] |EPEVT7 |Endpoint 7's USB Event Status
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177 * | | |0 = No event occurred in endpoint 7.
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178 * | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1].
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179 * |[24] |EPEVT8 |Endpoint 8's USB Event Status
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180 * | | |0 = No event occurred in endpoint 8.
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181 * | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1].
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182 * |[25] |EPEVT9 |Endpoint 9's USB Event Status
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183 * | | |0 = No event occurred in endpoint 9.
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184 * | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1].
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185 * |[26] |EPEVT10 |Endpoint 10's USB Event Status
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186 * | | |0 = No event occurred in endpoint 10.
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187 * | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1].
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188 * |[27] |EPEVT11 |Endpoint 11's USB Event Status
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189 * | | |0 = No event occurred in endpoint 11.
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190 * | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1].
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191 * |[31] |SETUP |Setup Event Status
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192 * | | |0 = No Setup event.
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193 * | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31].
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194 * @var USBD_T::FADDR
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195 * Offset: 0x08 USB Device Function Address Register
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196 * ---------------------------------------------------------------------------------------------------
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197 * |Bits |Field |Descriptions
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198 * | :----: | :----: | :---- |
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199 * |[6:0] |FADDR |USB Device Function Address
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200 * @var USBD_T::EPSTS
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201 * Offset: 0x0C USB Device Endpoint Status Register
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202 * ---------------------------------------------------------------------------------------------------
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203 * |Bits |Field |Descriptions
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204 * | :----: | :----: | :---- |
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205 * |[7] |OV |Overrun
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206 * | | |It indicates that the received data is over the maximum payload number or not.
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207 * | | |0 = No overrun.
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208 * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
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209 * @var USBD_T::ATTR
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210 * Offset: 0x10 USB Device Bus Status and Attribution Register
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211 * ---------------------------------------------------------------------------------------------------
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212 * |Bits |Field |Descriptions
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213 * | :----: | :----: | :---- |
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214 * |[0] |USBRST |USB Reset Status
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215 * | | |0 = Bus no reset.
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216 * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.
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217 * | | |Note: This bit is read only.
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218 * |[1] |SUSPEND |Suspend Status
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219 * | | |0 = Bus no suspend.
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220 * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
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221 * | | |Note: This bit is read only.
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222 * |[2] |RESUME |Resume Status
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223 * | | |0 = No bus resume.
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224 * | | |1 = Resume from suspend.
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225 * | | |Note: This bit is read only.
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226 * |[3] |TOUT |Time-out Status
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227 * | | |0 = No time-out.
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228 * | | |1 = No Bus response more than 18 bits time.
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229 * | | |Note: This bit is read only.
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230 * |[4] |PHYEN |PHY Transceiver Function Enable Bit
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231 * | | |0 = PHY transceiver function Disabled.
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232 * | | |1 = PHY transceiver function Enabled.
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233 * |[5] |RWAKEUP |Remote Wake-up
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234 * | | |0 = Release the USB bus from K state.
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235 * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.
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236 * |[7] |USBEN |USB Controller Enable Bit
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237 * | | |0 = USB Controller Disabled.
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238 * | | |1 = USB Controller Enabled.
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239 * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit
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240 * | | |0 = Pull-up resistor in USB_D+ bus Disabled.
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241 * | | |1 = Pull-up resistor in USB_D+ bus Active.
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242 * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
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243 * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
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244 * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
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245 * |[11] |LPMACK |LPM Token Acknowledge Enable Bit
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246 * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.
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247 * | | |0= the valid LPM Token will be NYET.
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248 * | | |1= the valid LPM Token will be ACK.
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249 * |[12] |L1SUSPEND |LPM L1 Suspend
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250 * | | |0 = Bus no L1 state suspend.
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251 * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.
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252 * | | |Note: This bit is read only.
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253 * |[13] |L1RESUME |LPM L1 Resume
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254 * | | |0 = Bus no LPM L1 state resume.
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255 * | | |1 = LPM L1 state Resume from LPM L1 state suspend.
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256 * | | |Note: This bit is read only.
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257 * @var USBD_T::VBUSDET
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258 * Offset: 0x14 USB Device VBUS Detection Register
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259 * ---------------------------------------------------------------------------------------------------
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260 * |Bits |Field |Descriptions
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261 * | :----: | :----: | :---- |
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262 * |[0] |VBUSDET |Device VBUS Detection
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263 * | | |0 = Controller is not attached to the USB host.
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264 * | | |1 = Controller is attached to the USB host.
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265 * @var USBD_T::STBUFSEG
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266 * Offset: 0x18 SETUP Token Buffer Segmentation Register
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267 * ---------------------------------------------------------------------------------------------------
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268 * |Bits |Field |Descriptions
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269 * | :----: | :----: | :---- |
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270 * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation
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271 * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
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272 * | | |USBD_SRAM address + {STBUFSEG, 3'b000}
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273 * | | |Where the USBD_SRAM address = USBD_BA+0x100h.
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274 * | | |Note: It is used for SETUP token only.
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275 * @var USBD_T::EPSTS0
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276 * Offset: 0x20 USB Device Endpoint Status Register 0
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277 * ---------------------------------------------------------------------------------------------------
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278 * |Bits |Field |Descriptions
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279 * | :----: | :----: | :---- |
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280 * |[3:0] |EPSTS0 |Endpoint 0 Status
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281 * | | |These bits are used to indicate the current status of this endpoint
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282 * | | |0000 = In ACK.
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283 * | | |0001 = In NAK.
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284 * | | |0010 = Out Packet Data0 ACK.
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285 * | | |0011 = Setup ACK.
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286 * | | |0110 = Out Packet Data1 ACK.
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287 * | | |0111 = Isochronous transfer end.
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288 * |[7:4] |EPSTS1 |Endpoint 1 Status
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289 * | | |These bits are used to indicate the current status of this endpoint
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290 * | | |0000 = In ACK.
\r
291 * | | |0001 = In NAK.
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292 * | | |0010 = Out Packet Data0 ACK.
\r
293 * | | |0011 = Setup ACK.
\r
294 * | | |0110 = Out Packet Data1 ACK.
\r
295 * | | |0111 = Isochronous transfer end.
\r
296 * |[11:8] |EPSTS2 |Endpoint 2 Status
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297 * | | |These bits are used to indicate the current status of this endpoint
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298 * | | |0000 = In ACK.
\r
299 * | | |0001 = In NAK.
\r
300 * | | |0010 = Out Packet Data0 ACK.
\r
301 * | | |0011 = Setup ACK.
\r
302 * | | |0110 = Out Packet Data1 ACK.
\r
303 * | | |0111 = Isochronous transfer end.
\r
304 * |[15:12] |EPSTS3 |Endpoint 3 Status
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305 * | | |These bits are used to indicate the current status of this endpoint
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306 * | | |0000 = In ACK.
\r
307 * | | |0001 = In NAK.
\r
308 * | | |0010 = Out Packet Data0 ACK.
\r
309 * | | |0011 = Setup ACK.
\r
310 * | | |0110 = Out Packet Data1 ACK.
\r
311 * | | |0111 = Isochronous transfer end.
\r
312 * |[19:16] |EPSTS4 |Endpoint 4 Status
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313 * | | |These bits are used to indicate the current status of this endpoint
\r
314 * | | |0000 = In ACK.
\r
315 * | | |0001 = In NAK.
\r
316 * | | |0010 = Out Packet Data0 ACK.
\r
317 * | | |0011 = Setup ACK.
\r
318 * | | |0110 = Out Packet Data1 ACK.
\r
319 * | | |0111 = Isochronous transfer end.
\r
320 * |[23:20] |EPSTS5 |Endpoint 5 Status
\r
321 * | | |These bits are used to indicate the current status of this endpoint
\r
322 * | | |0000 = In ACK.
\r
323 * | | |0001 = In NAK.
\r
324 * | | |0010 = Out Packet Data0 ACK.
\r
325 * | | |0011 = Setup ACK.
\r
326 * | | |0110 = Out Packet Data1 ACK.
\r
327 * | | |0111 = Isochronous transfer end.
\r
328 * |[27:24] |EPSTS6 |Endpoint 6 Status
\r
329 * | | |These bits are used to indicate the current status of this endpoint
\r
330 * | | |0000 = In ACK.
\r
331 * | | |0001 = In NAK.
\r
332 * | | |0010 = Out Packet Data0 ACK.
\r
333 * | | |0011 = Setup ACK.
\r
334 * | | |0110 = Out Packet Data1 ACK.
\r
335 * | | |0111 = Isochronous transfer end.
\r
336 * |[31:28] |EPSTS7 |Endpoint 7 Status
\r
337 * | | |These bits are used to indicate the current status of this endpoint
\r
338 * | | |0000 = In ACK.
\r
339 * | | |0001 = In NAK.
\r
340 * | | |0010 = Out Packet Data0 ACK.
\r
341 * | | |0011 = Setup ACK.
\r
342 * | | |0110 = Out Packet Data1 ACK.
\r
343 * | | |0111 = Isochronous transfer end.
\r
344 * @var USBD_T::EPSTS1
\r
345 * Offset: 0x24 USB Device Endpoint Status Register 1
\r
346 * ---------------------------------------------------------------------------------------------------
\r
347 * |Bits |Field |Descriptions
\r
348 * | :----: | :----: | :---- |
\r
349 * |[3:0] |EPSTS8 |Endpoint 8 Status
\r
350 * | | |These bits are used to indicate the current status of this endpoint
\r
351 * | | |0000 = In ACK.
\r
352 * | | |0001 = In NAK.
\r
353 * | | |0010 = Out Packet Data0 ACK.
\r
354 * | | |0011 = Setup ACK.
\r
355 * | | |0110 = Out Packet Data1 ACK.
\r
356 * | | |0111 = Isochronous transfer end.
\r
357 * |[7:4] |EPSTS9 |Endpoint 9 Status
\r
358 * | | |These bits are used to indicate the current status of this endpoint
\r
359 * | | |0000 = In ACK.
\r
360 * | | |0001 = In NAK.
\r
361 * | | |0010 = Out Packet Data0 ACK.
\r
362 * | | |0011 = Setup ACK.
\r
363 * | | |0110 = Out Packet Data1 ACK.
\r
364 * | | |0111 = Isochronous transfer end.
\r
365 * |[11:8] |EPSTS10 |Endpoint 10 Status
\r
366 * | | |These bits are used to indicate the current status of this endpoint
\r
367 * | | |0000 = In ACK.
\r
368 * | | |0001 = In NAK.
\r
369 * | | |0010 = Out Packet Data0 ACK.
\r
370 * | | |0011 = Setup ACK.
\r
371 * | | |0110 = Out Packet Data1 ACK.
\r
372 * | | |0111 = Isochronous transfer end.
\r
373 * |[15:12] |EPSTS11 |Endpoint 11 Status
\r
374 * | | |These bits are used to indicate the current status of this endpoint
\r
375 * | | |0000 = In ACK.
\r
376 * | | |0001 = In NAK.
\r
377 * | | |0010 = Out Packet Data0 ACK.
\r
378 * | | |0011 = Setup ACK.
\r
379 * | | |0110 = Out Packet Data1 ACK.
\r
380 * | | |0111 = Isochronous transfer end.
\r
381 * @var USBD_T::LPMATTR
\r
382 * Offset: 0x88 USB LPM Attribution Register
\r
383 * ---------------------------------------------------------------------------------------------------
\r
384 * |Bits |Field |Descriptions
\r
385 * | :----: | :----: | :---- |
\r
386 * |[3:0] |LPMLINKSTS|LPM Link State
\r
387 * | | |These bits contain the bLinkState received with last ACK LPM Token
\r
388 * | | |0000 = Reserve.
\r
389 * | | |0001 = L1 (Sleep).
\r
390 * | | |0010 - 1111 = Reserve.
\r
391 * |[7:4] |LPMBESL |LPM Best Effort Service Latency
\r
392 * | | |These bits contain the BESL value received with last ACK LPM Token
\r
393 * | | |0000 = 125us.
\r
394 * | | |0001 = 150us.
\r
395 * | | |0010 = 200us.
\r
396 * | | |0011 = 300us.
\r
397 * | | |0100 = 400us.
\r
398 * | | |0101 = 500us.
\r
399 * | | |0110 = 1000us.
\r
400 * | | |0111 = 2000us.
\r
401 * | | |1000 = 3000us.
\r
402 * | | |1001 = 4000us.
\r
403 * | | |1010 = 5000us.
\r
404 * | | |1011 = 6000us.
\r
405 * | | |1100 = 7000us.
\r
406 * | | |1101 = 8000us.
\r
407 * | | |1110 = 9000us.
\r
408 * | | |1111 = 10000us.
\r
409 * |[8] |LPMRWAKUP |LPM Remote Wakeup
\r
410 * | | |This bit contains the bRemoteWake value received with last ACK LPM Token
\r
412 * Offset: 0x8C USB Frame number Register
\r
413 * ---------------------------------------------------------------------------------------------------
\r
414 * |Bits |Field |Descriptions
\r
415 * | :----: | :----: | :---- |
\r
416 * |[10:0] |FN |Frame Number
\r
417 * | | |These bits contain the 11-bits frame number in the last received SOF packet.
\r
419 * Offset: 0x90 USB Device Drive SE0 Control Register
\r
420 * ---------------------------------------------------------------------------------------------------
\r
421 * |Bits |Field |Descriptions
\r
422 * | :----: | :----: | :---- |
\r
423 * |[0] |SE0 |Drive Single Ended Zero in USB Bus
\r
424 * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
\r
425 * | | |0 = Normal operation.
\r
426 * | | |1 = Force USB PHY transceiver to drive SE0.
\r
429 __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */
\r
430 __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */
\r
431 __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */
\r
432 __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */
\r
433 __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */
\r
434 __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */
\r
435 __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */
\r
436 __I uint32_t RESERVE0[1];
\r
437 __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */
\r
438 __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */
\r
439 __I uint32_t RESERVE1[24];
\r
440 __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */
\r
441 __I uint32_t FN; /*!< [0x008c] USB Frame number Register */
\r
442 __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */
\r
443 __I uint32_t RESERVE2[283];
\r
444 USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */
\r
449 @addtogroup USBD_CONST USBD Bit Field Definition
\r
450 Constant Definitions for USBD Controller
\r
453 #define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
\r
454 #define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
\r
456 #define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
\r
457 #define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
\r
459 #define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
\r
460 #define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
\r
462 #define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
\r
463 #define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
\r
465 #define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */
\r
466 #define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */
\r
468 #define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
\r
469 #define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
\r
471 #define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
\r
472 #define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
\r
474 #define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
\r
475 #define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
\r
477 #define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
\r
478 #define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
\r
480 #define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
\r
481 #define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
\r
483 #define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
\r
484 #define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
\r
486 #define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */
\r
487 #define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */
\r
489 #define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
\r
490 #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
\r
492 #define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
\r
493 #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
\r
495 #define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
\r
496 #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
\r
498 #define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
\r
499 #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
\r
501 #define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
\r
502 #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
\r
504 #define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
\r
505 #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
\r
507 #define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
\r
508 #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
\r
510 #define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
\r
511 #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
\r
513 #define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */
\r
514 #define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */
\r
516 #define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */
\r
517 #define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */
\r
519 #define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */
\r
520 #define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */
\r
522 #define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */
\r
523 #define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */
\r
525 #define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
\r
526 #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
\r
528 #define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
\r
529 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
\r
531 #define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
\r
532 #define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
\r
534 #define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
\r
535 #define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
\r
537 #define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
\r
538 #define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
\r
540 #define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
\r
541 #define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
\r
543 #define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
\r
544 #define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
\r
546 #define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
\r
547 #define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
\r
549 #define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
\r
550 #define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
\r
552 #define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
\r
553 #define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
\r
555 #define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
\r
556 #define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
\r
558 #define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
\r
559 #define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
\r
561 #define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */
\r
562 #define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */
\r
564 #define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */
\r
565 #define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */
\r
567 #define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */
\r
568 #define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */
\r
570 #define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
\r
571 #define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
\r
573 #define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
\r
574 #define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
\r
576 #define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */
\r
577 #define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */
\r
579 #define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */
\r
580 #define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */
\r
582 #define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */
\r
583 #define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */
\r
585 #define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */
\r
586 #define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */
\r
588 #define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */
\r
589 #define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */
\r
591 #define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */
\r
592 #define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */
\r
594 #define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */
\r
595 #define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */
\r
597 #define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */
\r
598 #define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */
\r
600 #define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */
\r
601 #define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */
\r
603 #define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */
\r
604 #define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */
\r
606 #define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */
\r
607 #define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */
\r
609 #define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */
\r
610 #define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */
\r
612 #define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */
\r
613 #define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */
\r
615 #define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */
\r
616 #define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */
\r
618 #define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */
\r
619 #define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */
\r
621 #define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */
\r
622 #define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */
\r
624 #define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
\r
625 #define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
\r
627 #define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
\r
628 #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
\r
630 #define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
\r
631 #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
\r
633 #define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
\r
634 #define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
\r
636 #define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
\r
637 #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
\r
639 #define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
\r
640 #define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
\r
642 #define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
\r
643 #define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
\r
645 #define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
\r
646 #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
\r
648 #define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
\r
649 #define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
\r
651 #define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
\r
652 #define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
\r
655 /**@}*/ /* USBD_CONST */
\r
656 /**@}*/ /* end of USBD register group */
\r
657 /**@}*/ /* end of REGISTER group */
\r
659 #endif /* __USBD_REG_H__ */
\r
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