1 /****************************************************************************//**
2 * @file startup_M2351.S
4 * @brief CMSIS Device Startup File
6 * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
7 *****************************************************************************/
17 .equ Stack_Size, 0x00000800
23 .size __StackLimit, . - __StackLimit
25 .size __StackTop, . - __StackTop
30 .equ Heap_Size, 0x00000100
39 .size __HeapBase, . - __HeapBase
41 .size __HeapLimit, . - __HeapLimit
47 .long __StackTop /* Top of Stack */
48 .long Reset_Handler /* Reset Handler */
49 .long NMI_Handler /* NMI Handler */
50 .long HardFault_Handler /* Hard Fault Handler */
51 .long 0 /* Reserved */
52 .long 0 /* Reserved */
53 .long 0 /* Reserved */
54 .long 0 /* Reserved */
55 .long 0 /* Reserved */
56 .long 0 /* Reserved */
57 .long 0 /* Reserved */
58 .long SVC_Handler /* SVCall Handler */
59 .long 0 /* Reserved */
60 .long 0 /* Reserved */
61 .long PendSV_Handler /* PendSV Handler */
62 .long SysTick_Handler /* SysTick Handler */
64 /* External interrupts */
65 .long BOD_IRQHandler /* 0 */
66 .long IRC_IRQHandler /* 1 */
67 .long PWRWU_IRQHandler /* 2 */
68 .long SRAM_IRQHandler /* 3 */
69 .long CLKFAIL_IRQHandler /* 4 */
70 .long Default_Handler /* 5 */
71 .long RTC_IRQHandler /* 6 */
72 .long TAMPER_IRQHandler /* 7 */
73 .long WDT_IRQHandler /* 8 */
74 .long WWDT_IRQHandler /* 9 */
75 .long EINT0_IRQHandler /* 10 */
76 .long EINT1_IRQHandler /* 11 */
77 .long EINT2_IRQHandler /* 12 */
78 .long EINT3_IRQHandler /* 13 */
79 .long EINT4_IRQHandler /* 14 */
80 .long EINT5_IRQHandler /* 15 */
81 .long GPA_IRQHandler /* 16 */
82 .long GPB_IRQHandler /* 17 */
83 .long GPC_IRQHandler /* 18 */
84 .long GPD_IRQHandler /* 19 */
85 .long GPE_IRQHandler /* 20 */
86 .long GPF_IRQHandler /* 21 */
87 .long QSPI0_IRQHandler /* 22 */
88 .long SPI0_IRQHandler /* 23 */
89 .long BRAKE0_IRQHandler /* 24 */
90 .long EPWM0_P0_IRQHandler /* 25 */
91 .long EPWM0_P1_IRQHandler /* 26 */
92 .long EPWM0_P2_IRQHandler /* 27 */
93 .long BRAKE1_IRQHandler /* 28 */
94 .long EPWM1_P0_IRQHandler /* 29 */
95 .long EPWM1_P1_IRQHandler /* 30 */
96 .long EPWM1_P2_IRQHandler /* 31 */
97 .long TMR0_IRQHandler /* 32 */
98 .long TMR1_IRQHandler /* 33 */
99 .long TMR2_IRQHandler /* 34 */
100 .long TMR3_IRQHandler /* 35 */
101 .long UART0_IRQHandler /* 36 */
102 .long UART1_IRQHandler /* 37 */
103 .long I2C0_IRQHandler /* 38 */
104 .long I2C1_IRQHandler /* 39 */
105 .long PDMA0_IRQHandler /* 40 */
106 .long DAC_IRQHandler /* 41 */
107 .long EADC0_IRQHandler /* 42 */
108 .long EADC1_IRQHandler /* 43 */
109 .long ACMP01_IRQHandler /* 44 */
110 .long Default_Handler /* 45 */
111 .long EADC2_IRQHandler /* 46 */
112 .long EADC3_IRQHandler /* 47 */
113 .long UART2_IRQHandler /* 48 */
114 .long UART3_IRQHandler /* 49 */
115 .long Default_Handler /* 50 */
116 .long SPI1_IRQHandler /* 51 */
117 .long SPI2_IRQHandler /* 52 */
118 .long USBD_IRQHandler /* 53 */
119 .long USBH_IRQHandler /* 54 */
120 .long USBOTG_IRQHandler /* 55 */
121 .long CAN0_IRQHandler /* 56 */
122 .long Default_Handler /* 57 */
123 .long SC0_IRQHandler /* 58 */
124 .long SC1_IRQHandler /* 59 */
125 .long SC2_IRQHandler /* 60 */
126 .long Default_Handler /* 61 */
127 .long SPI3_IRQHandler /* 62 */
128 .long Default_Handler /* 63 */
129 .long SDH0_IRQHandler /* 64 */
130 .long Default_Handler /* 65 */
131 .long Default_Handler /* 66 */
132 .long Default_Handler /* 67 */
133 .long I2S0_IRQHandler /* 68 */
134 .long Default_Handler /* 69 */
135 .long OPA0_IRQHandler /* 70 */
136 .long CRPT_IRQHandler /* 71 */
137 .long GPG_IRQHandler /* 72 */
138 .long EINT6_IRQHandler /* 73 */
139 .long UART4_IRQHandler /* 74 */
140 .long UART5_IRQHandler /* 75 */
141 .long USCI0_IRQHandler /* 76 */
142 .long USCI1_IRQHandler /* 77 */
143 .long BPWM0_IRQHandler /* 78 */
144 .long BPWM1_IRQHandler /* 79 */
145 .long Default_Handler /* 80 */
146 .long Default_Handler /* 81 */
147 .long I2C2_IRQHandler /* 82 */
148 .long Default_Handler /* 83 */
149 .long QEI0_IRQHandler /* 84 */
150 .long QEI1_IRQHandler /* 85 */
151 .long ECAP0_IRQHandler /* 86 */
152 .long ECAP1_IRQHandler /* 87 */
153 .long GPH_IRQHandler /* 88 */
154 .long EINT7_IRQHandler /* 89 */
155 .long Default_Handler /* 90 */
156 .long Default_Handler /* 91 */
157 .long Default_Handler /* 92 */
158 .long Default_Handler /* 93 */
159 .long Default_Handler /* 94 */
160 .long Default_Handler /* 95 */
161 .long Default_Handler /* 96 */
162 .long Default_Handler /* 97 */
163 .long PDMA1_IRQHandler /* 98 */
164 .long SCU_IRQHandler /* 99 */
165 .long Default_Handler /* 100 */
166 .long TRNG_IRQHandler /* 101 */
169 .size __Vectors, . - __Vectors
177 .global Reset_Handler
178 .type Reset_Handler, % function
182 /* Firstly it copies data from read only memory to RAM. There are two schemes
183 * to copy. One can copy more than one sections. Another can only copy
184 * one section. The former scheme needs more instructions and read-only
185 * data to implement than the latter.
186 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
188 #ifdef __STARTUP_COPY_MULTIPLE
189 /* Multiple sections scheme.
191 * Between symbol address __copy_table_start__ and __copy_table_end__,
192 * there are array of triplets, each of which specify:
193 * offset 0: LMA of start of a section to copy from
194 * offset 4: VMA of start of a section to copy to
195 * offset 8: size of the section to copy. Must be multiply of 4
197 * All addresses must be aligned to 4 bytes boundary.
199 ldr r4, = __copy_table_start__
200 ldr r5, = __copy_table_end__
222 /* Single section scheme.
224 * The ranges of copy from/to are specified by following symbols
225 * __etext: LMA of start of the section to copy from. Usually end of text
226 * __data_start__: VMA of start of the section to copy to
227 * __data_end__: VMA of end of the section to copy to
229 * All addresses must be aligned to 4 bytes boundary.
232 ldr r2, = __data_start__
233 ldr r3, = __data_end__
245 #endif /*__STARTUP_COPY_MULTIPLE */
247 /* This part of work usually is done in C library startup code. Otherwise,
248 * define this macro to enable it in this startup.
250 * There are two schemes too. One can clear multiple BSS sections. Another
251 * can only clear one section. The former is more size expensive than the
254 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
255 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
257 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
258 /* Multiple sections scheme.
260 * Between symbol address __copy_table_start__ and __copy_table_end__,
261 * there are array of tuples specifying:
262 * offset 0: Start of a BSS section
263 * offset 4: Size of this BSS section. Must be multiply of 4
265 ldr r3, = __zero_table_start__
266 ldr r4, = __zero_table_end__
286 #elif defined (__STARTUP_CLEAR_BSS)
287 /* Single BSS section scheme.
289 * The BSS section is specified by following symbols
290 * __bss_start__: start of the BSS section.
291 * __bss_end__: end of the BSS section.
293 * Both addresses must be aligned to 4 bytes boundary.
295 ldr r1, = __bss_start__
296 ldr r2, = __bss_end__
308 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
312 #ifndef __NO_SYSTEM_INIT
318 #define __START _start
323 .size Reset_Handler, . - Reset_Handler
327 .weak Default_Handler
328 .type Default_Handler, % function
332 .size Default_Handler, . - Default_Handler
334 /* Macro to define default handlers. Default handler
335 * will be weak symbol and just dead loops. They can be
336 * overwritten by other handlers */
338 .macro def_irq_handler handler_name
340 .set \handler_name, Default_Handler
343 def_irq_handler NMI_Handler
344 def_irq_handler HardFault_Handler
345 def_irq_handler SVC_Handler
346 def_irq_handler PendSV_Handler
347 def_irq_handler SysTick_Handler
349 def_irq_handler BOD_IRQHandler
350 def_irq_handler IRC_IRQHandler
351 def_irq_handler PWRWU_IRQHandler
352 def_irq_handler SRAM_IRQHandler
353 def_irq_handler CLKFAIL_IRQHandler
355 def_irq_handler RTC_IRQHandler
356 def_irq_handler TAMPER_IRQHandler
357 def_irq_handler WDT_IRQHandler
358 def_irq_handler WWDT_IRQHandler
359 def_irq_handler EINT0_IRQHandler
360 def_irq_handler EINT1_IRQHandler
361 def_irq_handler EINT2_IRQHandler
362 def_irq_handler EINT3_IRQHandler
363 def_irq_handler EINT4_IRQHandler
364 def_irq_handler EINT5_IRQHandler
365 def_irq_handler GPA_IRQHandler
366 def_irq_handler GPB_IRQHandler
367 def_irq_handler GPC_IRQHandler
368 def_irq_handler GPD_IRQHandler
369 def_irq_handler GPE_IRQHandler
370 def_irq_handler GPF_IRQHandler
371 def_irq_handler QSPI0_IRQHandler
372 def_irq_handler SPI0_IRQHandler
373 def_irq_handler BRAKE0_IRQHandler
374 def_irq_handler EPWM0_P0_IRQHandler
375 def_irq_handler EPWM0_P1_IRQHandler
376 def_irq_handler EPWM0_P2_IRQHandler
377 def_irq_handler BRAKE1_IRQHandler
378 def_irq_handler EPWM1_P0_IRQHandler
379 def_irq_handler EPWM1_P1_IRQHandler
380 def_irq_handler EPWM1_P2_IRQHandler
381 def_irq_handler TMR0_IRQHandler
382 def_irq_handler TMR1_IRQHandler
383 def_irq_handler TMR2_IRQHandler
384 def_irq_handler TMR3_IRQHandler
385 def_irq_handler UART0_IRQHandler
386 def_irq_handler UART1_IRQHandler
387 def_irq_handler I2C0_IRQHandler
388 def_irq_handler I2C1_IRQHandler
389 def_irq_handler PDMA0_IRQHandler
390 def_irq_handler DAC_IRQHandler
391 def_irq_handler EADC0_IRQHandler
392 def_irq_handler EADC1_IRQHandler
393 def_irq_handler ACMP01_IRQHandler
395 def_irq_handler EADC2_IRQHandler
396 def_irq_handler EADC3_IRQHandler
397 def_irq_handler UART2_IRQHandler
398 def_irq_handler UART3_IRQHandler
400 def_irq_handler SPI1_IRQHandler
401 def_irq_handler SPI2_IRQHandler
402 def_irq_handler USBD_IRQHandler
403 def_irq_handler USBH_IRQHandler
404 def_irq_handler USBOTG_IRQHandler
405 def_irq_handler CAN0_IRQHandler
407 def_irq_handler SC0_IRQHandler
408 def_irq_handler SC1_IRQHandler
409 def_irq_handler SC2_IRQHandler
411 def_irq_handler SPI3_IRQHandler
413 def_irq_handler SDH0_IRQHandler
417 def_irq_handler I2S0_IRQHandler
419 def_irq_handler OPA0_IRQHandler
420 def_irq_handler CRPT_IRQHandler
421 def_irq_handler GPG_IRQHandler
422 def_irq_handler EINT6_IRQHandler
423 def_irq_handler UART4_IRQHandler
424 def_irq_handler UART5_IRQHandler
425 def_irq_handler USCI0_IRQHandler
426 def_irq_handler USCI1_IRQHandler
427 def_irq_handler BPWM0_IRQHandler
428 def_irq_handler BPWM1_IRQHandler
431 def_irq_handler I2C2_IRQHandler
433 def_irq_handler QEI0_IRQHandler
434 def_irq_handler QEI1_IRQHandler
435 def_irq_handler ECAP0_IRQHandler
436 def_irq_handler ECAP1_IRQHandler
437 def_irq_handler GPH_IRQHandler
438 def_irq_handler EINT7_IRQHandler
447 def_irq_handler PDMA1_IRQHandler
448 def_irq_handler SCU_IRQHandler
450 def_irq_handler TRNG_IRQHandler
454 /* ;int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0) */
457 .type SH_DoCommand, % function
461 BKPT 0xAB /* ; Wait ICE or HardFault */
464 BLX R3 /* ; Call SH_Return. The return value is in R0 */
465 BX R4 /* ; Return value = R0 */
466 .size SH_DoCommand, . - SH_DoCommand
471 .type __PC, % function