1 /******************************************************************************
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4 * @brief M2351 series EADC driver header file
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7 * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
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8 *****************************************************************************/
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18 /** @addtogroup Standard_Driver Standard Driver
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22 /** @addtogroup EADC_Driver EADC Driver
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26 /** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
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30 /*---------------------------------------------------------------------------------------------------------*/
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31 /* EADC_CTL Constant Definitions */
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32 /*---------------------------------------------------------------------------------------------------------*/
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33 #define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode */
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34 #define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode */
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36 #define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result */
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37 #define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result */
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40 /*---------------------------------------------------------------------------------------------------------*/
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41 /* EADC_SCTL Constant Definitions */
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42 /*---------------------------------------------------------------------------------------------------------*/
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43 #define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection */
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44 #define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection */
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45 #define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time */
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47 #define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger */
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48 #define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger */
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49 #define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger */
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50 #define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger */
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51 #define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger */
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52 #define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger */
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53 #define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger */
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54 #define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger */
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55 #define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger */
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56 #define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger */
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57 #define EADC_PWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG0 trigger */
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58 #define EADC_PWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG1 trigger */
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59 #define EADC_PWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG2 trigger */
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60 #define EADC_PWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG3 trigger */
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61 #define EADC_PWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG4 trigger */
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62 #define EADC_PWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG5 trigger */
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63 #define EADC_PWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG0 trigger */
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64 #define EADC_PWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG1 trigger */
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65 #define EADC_PWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG2 trigger */
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66 #define EADC_PWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG3 trigger */
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67 #define EADC_PWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG4 trigger */
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68 #define EADC_PWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG5 trigger */
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69 #define EADC_BPWM0TG_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM0TG trigger */
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70 #define EADC_BPWM1TG_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM1TG trigger */
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72 #define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 */
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73 #define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 */
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74 #define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 */
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75 #define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 */
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78 /*---------------------------------------------------------------------------------------------------------*/
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79 /* EADC_CMP Constant Definitions */
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80 /*---------------------------------------------------------------------------------------------------------*/
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81 #define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" */
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82 #define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */
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83 #define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable */
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84 #define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable */
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85 #define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable */
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86 #define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable */
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88 /*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */
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90 /** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
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93 /*---------------------------------------------------------------------------------------------------------*/
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94 /* EADC Macro Definitions */
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95 /*---------------------------------------------------------------------------------------------------------*/
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98 * @brief A/D Converter Control Circuits Reset.
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99 * @param[in] eadc The pointer of the specified EADC module.
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101 * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
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103 #define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)
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106 * @brief Enable PDMA transfer.
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107 * @param[in] eadc The pointer of the specified EADC module.
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109 * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
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110 * user can enable this bit to generate a PDMA data transfer request.
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111 * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
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113 #define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
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116 * @brief Disable PDMA transfer.
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117 * @param[in] eadc The pointer of the specified EADC module.
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119 * @details This macro is used to disable PDMA transfer.
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121 #define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
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124 * @brief Enable double buffer mode.
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125 * @param[in] eadc The pointer of the specified EADC module.
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126 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
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128 * @details The ADC controller supports a double buffer mode in sample module 0~3.
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129 * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
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131 #define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
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134 * @brief Disable double buffer mode.
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135 * @param[in] eadc The pointer of the specified EADC module.
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136 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
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138 * @details Sample has one sample result register.
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140 #define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
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143 * @brief Set ADIFn at A/D end of conversion.
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144 * @param[in] eadc The pointer of the specified EADC module.
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145 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
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147 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
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149 #define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
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152 * @brief Set ADIFn at A/D start of conversion.
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153 * @param[in] eadc The pointer of the specified EADC module.
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154 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
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156 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
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158 #define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
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161 * @brief Enable the interrupt.
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162 * @param[in] eadc The pointer of the specified EADC module.
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163 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
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164 * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
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166 * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
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167 * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
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169 #define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
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172 * @brief Disable the interrupt.
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173 * @param[in] eadc The pointer of the specified EADC module.
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174 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
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175 * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
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177 * @details Specific sample module A/D ADINT0 interrupt function Disabled.
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179 #define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
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182 * @brief Enable the sample module interrupt.
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183 * @param[in] eadc The pointer of the specified EADC module.
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184 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
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185 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
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186 * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
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188 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
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190 #define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
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193 * @brief Disable the sample module interrupt.
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194 * @param[in] eadc The pointer of the specified EADC module.
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195 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
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196 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
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197 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
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199 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
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201 #define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
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204 * @brief Set the input mode output format.
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205 * @param[in] eadc The pointer of the specified EADC module.
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206 * @param[in] u32Format Decides the output format. Valid values are:
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207 * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result.
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208 * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
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210 * @details The macro is used to set A/D input mode output format.
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212 #define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
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215 * @brief Start the A/D conversion.
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216 * @param[in] eadc The pointer of the specified EADC module.
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217 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
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218 * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
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219 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
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221 * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
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223 #define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
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226 * @brief Cancel the conversion for sample module.
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227 * @param[in] eadc The pointer of the specified EADC module.
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228 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
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229 * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
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230 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
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232 * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
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234 #define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
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237 * @brief Get the conversion pending flag.
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238 * @param[in] eadc The pointer of the specified EADC module.
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239 * @return Return the conversion pending sample module.
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240 * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
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241 * the STPFn (n=0~18) bit is automatically cleared to 0.
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243 #define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
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246 * @brief Get the conversion data of the user-specified sample module.
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247 * @param[in] eadc The pointer of the specified EADC module.
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248 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
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249 * @return Return the conversion data of the user-specified sample module.
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250 * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
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252 #define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
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255 * @brief Get the data overrun flag of the user-specified sample module.
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256 * @param[in] eadc The pointer of the specified EADC module.
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257 * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
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258 * @return Return the data overrun flag of the user-specified sample module.
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259 * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
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261 #define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
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264 * @brief Get the data valid flag of the user-specified sample module.
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265 * @param[in] eadc The pointer of the specified EADC module.
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266 * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
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267 * @return Return the data valid flag of the user-specified sample module.
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268 * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status.
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270 #define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
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273 * @brief Get the double data of the user-specified sample module.
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274 * @param[in] eadc The pointer of the specified EADC module.
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275 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
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276 * @return Return the double data of the user-specified sample module.
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277 * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
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279 #define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk)
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282 * @brief Get the user-specified interrupt flags.
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283 * @param[in] eadc The pointer of the specified EADC module.
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284 * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
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285 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
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286 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
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287 * @return Return the user-specified interrupt flags.
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288 * @details This macro is used to get the user-specified interrupt flags.
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290 #define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
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293 * @brief Get the user-specified sample module overrun flags.
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294 * @param[in] eadc The pointer of the specified EADC module.
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295 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
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296 * @return Return the user-specified sample module overrun flags.
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297 * @details This macro is used to get the user-specified sample module overrun flags.
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299 #define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
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302 * @brief Clear the selected interrupt status bits.
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303 * @param[in] eadc The pointer of the specified EADC module.
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304 * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
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305 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
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306 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
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308 * @details This macro is used to clear clear the selected interrupt status bits.
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310 #define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
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313 * @brief Clear the selected sample module overrun status bits.
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314 * @param[in] eadc The pointer of the specified EADC module.
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315 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
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316 * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
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318 * @details This macro is used to clear the selected sample module overrun status bits.
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320 #define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
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323 * @brief Check all sample module A/D result data register overrun flags.
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324 * @param[in] eadc The pointer of the specified EADC module.
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325 * @retval 0 None of sample module data register overrun flag is set to 1.
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326 * @retval 1 Any one of sample module data register overrun flag is set to 1.
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327 * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
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329 #define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
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332 * @brief Check all sample module A/D result data register valid flags.
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333 * @param[in] eadc The pointer of the specified EADC module.
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334 * @retval 0 None of sample module data register valid flag is set to 1.
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335 * @retval 1 Any one of sample module data register valid flag is set to 1.
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336 * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
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338 #define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
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341 * @brief Check all A/D sample module start of conversion overrun flags.
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342 * @param[in] eadc The pointer of the specified EADC module.
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343 * @retval 0 None of sample module event overrun flag is set to 1.
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344 * @retval 1 Any one of sample module event overrun flag is set to 1.
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345 * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
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347 #define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
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350 * @brief Check all A/D interrupt flag overrun bits.
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351 * @param[in] eadc The pointer of the specified EADC module.
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352 * @retval 0 None of ADINT interrupt flag is overwritten to 1.
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353 * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
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354 * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
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356 #define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
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359 * @brief Get the busy state of EADC.
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360 * @param[in] eadc The pointer of the specified EADC module.
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361 * @retval 0 Idle state.
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362 * @retval 1 Busy state.
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363 * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
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365 #define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
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368 * @brief Configure the comparator 0 and enable it.
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369 * @param[in] eadc The pointer of the specified EADC module.
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370 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
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371 * @param[in] u32Condition specifies the compare condition. Valid values are:
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372 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
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373 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
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374 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
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375 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
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377 * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
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378 * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
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379 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
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381 #define EADC_ENABLE_CMP0(eadc,\
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385 u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
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387 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
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388 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\
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389 EADC_CMP_ADCMPEN_Msk))
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392 * @brief Configure the comparator 1 and enable it.
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393 * @param[in] eadc The pointer of the specified EADC module.
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394 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
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395 * @param[in] u32Condition specifies the compare condition. Valid values are:
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396 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
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397 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
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398 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
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399 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
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401 * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
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402 * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
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403 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
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405 #define EADC_ENABLE_CMP1(eadc,\
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409 u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
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411 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
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412 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\
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413 EADC_CMP_ADCMPEN_Msk))
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416 * @brief Configure the comparator 2 and enable it.
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417 * @param[in] eadc The pointer of the specified EADC module.
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418 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
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419 * @param[in] u32Condition specifies the compare condition. Valid values are:
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420 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
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421 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
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422 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
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423 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
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425 * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
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426 * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
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427 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
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429 #define EADC_ENABLE_CMP2(eadc,\
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433 u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
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435 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
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436 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\
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437 EADC_CMP_ADCMPEN_Msk))
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440 * @brief Configure the comparator 3 and enable it.
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441 * @param[in] eadc The pointer of the specified EADC module.
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442 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
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443 * @param[in] u32Condition specifies the compare condition. Valid values are:
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444 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
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445 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
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446 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
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447 * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
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449 * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
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450 * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
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451 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
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453 #define EADC_ENABLE_CMP3(eadc,\
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457 u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
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459 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
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460 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\
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461 EADC_CMP_ADCMPEN_Msk))
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464 * @brief Enable the compare window mode.
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465 * @param[in] eadc The pointer of the specified EADC module.
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466 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
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468 * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
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470 #define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
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473 * @brief Disable the compare window mode.
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474 * @param[in] eadc The pointer of the specified EADC module.
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475 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
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477 * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
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479 #define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
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482 * @brief Enable the compare interrupt.
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483 * @param[in] eadc The pointer of the specified EADC module.
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484 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
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486 * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
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487 * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
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488 * if ADCMPIE is set to 1, a compare interrupt request is generated.
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490 #define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
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493 * @brief Disable the compare interrupt.
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494 * @param[in] eadc The pointer of the specified EADC module.
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495 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
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497 * @details This macro is used to disable the compare interrupt.
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499 #define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
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502 * @brief Disable comparator 0.
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503 * @param[in] eadc The pointer of the specified EADC module.
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505 * @details This macro is used to disable comparator 0.
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507 #define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0UL)
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510 * @brief Disable comparator 1.
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511 * @param[in] eadc The pointer of the specified EADC module.
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513 * @details This macro is used to disable comparator 1.
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515 #define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0UL)
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518 * @brief Disable comparator 2.
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519 * @param[in] eadc The pointer of the specified EADC module.
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521 * @details This macro is used to disable comparator 2.
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523 #define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0UL)
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526 * @brief Disable comparator 3.
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527 * @param[in] eadc The pointer of the specified EADC module.
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529 * @details This macro is used to disable comparator 3.
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531 #define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0UL)
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533 /*---------------------------------------------------------------------------------------------------------*/
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534 /* Define EADC functions prototype */
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535 /*---------------------------------------------------------------------------------------------------------*/
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536 void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
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537 void EADC_Close(EADC_T *eadc);
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538 void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel);
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539 void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
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540 void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
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542 /*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
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544 /*@}*/ /* end of group EADC_Driver */
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546 /*@}*/ /* end of group Standard_Driver */
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552 #endif /* __EADC_H__ */
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554 /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
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