1 /**************************************************************************//**
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4 * @brief M2351 series System Manager (SYS) driver header file
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7 * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
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9 ******************************************************************************/
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19 /** @addtogroup Standard_Driver Standard Driver
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23 /** @addtogroup SYS_Driver SYS Driver
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27 /** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
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31 /*---------------------------------------------------------------------------------------------------------*/
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32 /* Module Reset Control Resister constant definitions. */
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33 /*---------------------------------------------------------------------------------------------------------*/
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34 #define PDMA0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA0RST_Pos) /*!< PDMA0 reset is one of the SYS_ResetModule parameter */
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35 #define EBI_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_EBIRST_Pos) /*!< EBI reset is one of the SYS_ResetModule parameter */
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36 #define USBH_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_USBHRST_Pos) /*!< USBH reset is one of the SYS_ResetModule parameter */
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37 #define SDH0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_SDH0RST_Pos) /*!< SDH0 reset is one of the SYS_ResetModule parameter */
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38 #define CRC_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRCRST_Pos) /*!< CRC reset is one of the SYS_ResetModule parameter */
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39 #define CRPT_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRPTRST_Pos) /*!< CRPT reset is one of the SYS_ResetModule parameter */
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40 #define PDMA1_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA1RST_Pos) /*!< PDMA1 reset is one of the SYS_ResetModule parameter */
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42 #define GPIO_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_GPIORST_Pos) /*!< GPIO reset is one of the SYS_ResetModule parameter */
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43 #define TMR0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR0RST_Pos) /*!< TMR0 reset is one of the SYS_ResetModule parameter */
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44 #define TMR1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR1RST_Pos) /*!< TMR1 reset is one of the SYS_ResetModule parameter */
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45 #define TMR2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR2RST_Pos) /*!< TMR2 reset is one of the SYS_ResetModule parameter */
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46 #define TMR3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR3RST_Pos) /*!< TMR3 reset is one of the SYS_ResetModule parameter */
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47 #define ACMP01_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_ACMP01RST_Pos) /*!< ACMP01 reset is one of the SYS_ResetModule parameter */
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48 #define I2C0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C0RST_Pos) /*!< I2C0 reset is one of the SYS_ResetModule parameter */
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49 #define I2C1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C1RST_Pos) /*!< I2C1 reset is one of the SYS_ResetModule parameter */
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50 #define I2C2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C2RST_Pos) /*!< I2C2 reset is one of the SYS_ResetModule parameter */
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51 #define QSPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_QSPI0RST_Pos) /*!< QSPI0 reset is one of the SYS_ResetModule parameter */
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52 #define SPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI0RST_Pos) /*!< SPI0 reset is one of the SYS_ResetModule parameter */
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53 #define SPI1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI1RST_Pos) /*!< SPI1 reset is one of the SYS_ResetModule parameter */
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54 #define SPI2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI2RST_Pos) /*!< SPI2 reset is one of the SYS_ResetModule parameter */
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55 #define UART0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART0RST_Pos) /*!< UART0 reset is one of the SYS_ResetModule parameter */
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56 #define UART1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART1RST_Pos) /*!< UART1 reset is one of the SYS_ResetModule parameter */
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57 #define UART2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART2RST_Pos) /*!< UART2 reset is one of the SYS_ResetModule parameter */
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58 #define UART3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART3RST_Pos) /*!< UART3 reset is one of the SYS_ResetModule parameter */
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59 #define UART4_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART4RST_Pos) /*!< UART4 reset is one of the SYS_ResetModule parameter */
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60 #define UART5_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART5RST_Pos) /*!< UART5 reset is one of the SYS_ResetModule parameter */
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61 #define CAN0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_CAN0RST_Pos) /*!< CAN0 reset is one of the SYS_ResetModule parameter */
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62 #define OTG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_OTGRST_Pos) /*!< OTG reset is one of the SYS_ResetModule parameter */
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63 #define USBD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_USBDRST_Pos) /*!< USBD reset is one of the SYS_ResetModule parameter */
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64 #define EADC_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_EADCRST_Pos) /*!< EADC reset is one of the SYS_ResetModule parameter */
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65 #define I2S0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2S0RST_Pos) /*!< I2S0 reset is one of the SYS_ResetModule parameter */
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66 #define TRNG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TRNGRST_Pos) /*!< TRNG reset is one of the SYS_ResetModule parameter */
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68 #define SC0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC0RST_Pos) /*!< SC0 reset is one of the SYS_ResetModule parameter */
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69 #define SC1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC1RST_Pos) /*!< SC1 reset is one of the SYS_ResetModule parameter */
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70 #define SC2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC2RST_Pos) /*!< SC2 reset is one of the SYS_ResetModule parameter */
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71 #define SPI3_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI3RST_Pos) /*!< SPI3 reset is one of the SYS_ResetModule parameter */
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72 #define USCI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI0RST_Pos) /*!< USCI0 reset is one of the SYS_ResetModule parameter */
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73 #define USCI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI1RST_Pos) /*!< USCI1 reset is one of the SYS_ResetModule parameter */
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74 #define USCI2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI2RST_Pos) /*!< USCI2 reset is one of the SYS_ResetModule parameter */
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75 #define DAC_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_DACRST_Pos) /*!< DAC reset is one of the SYS_ResetModule parameter */
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76 #define EPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM0RST_Pos) /*!< EPWM0 reset is one of the SYS_ResetModule parameter */
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77 #define EPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM1RST_Pos) /*!< EPWM1 reset is one of the SYS_ResetModule parameter */
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78 #define BPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM0RST_Pos) /*!< BPWM0 reset is one of the SYS_ResetModule parameter */
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79 #define BPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM1RST_Pos) /*!< BPWM1 reset is one of the SYS_ResetModule parameter */
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80 #define QEI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI0RST_Pos) /*!< QEI0 reset is one of the SYS_ResetModule parameter */
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81 #define QEI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI1RST_Pos) /*!< QEI1 reset is one of the SYS_ResetModule parameter */
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82 #define ECAP0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP0RST_Pos) /*!< ECAP0 reset is one of the SYS_ResetModule parameter */
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83 #define ECAP1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP1RST_Pos) /*!< ECAP1 reset is one of the SYS_ResetModule parameter */
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86 /*---------------------------------------------------------------------------------------------------------*/
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87 /* Brown Out Detector Threshold Voltage Selection constant definitions. */
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88 /*---------------------------------------------------------------------------------------------------------*/
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89 #define SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable */
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90 #define SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable */
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91 #define SYS_BODCTL_BODVL_3_0V (7UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V */
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92 #define SYS_BODCTL_BODVL_2_8V (6UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V */
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93 #define SYS_BODCTL_BODVL_2_6V (5UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V */
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94 #define SYS_BODCTL_BODVL_2_4V (4UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V */
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95 #define SYS_BODCTL_BODVL_2_2V (3UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */
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96 #define SYS_BODCTL_BODVL_2_0V (2UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V */
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97 #define SYS_BODCTL_BODVL_1_8V (1UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V */
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98 #define SYS_BODCTL_BODVL_1_6V (0UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V */
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101 /*---------------------------------------------------------------------------------------------------------*/
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102 /* VREFCTL constant definitions. (Write-Protection Register) */
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103 /*---------------------------------------------------------------------------------------------------------*/
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104 #define SYS_VREFCTL_VREF_PIN (0x0UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin */
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105 #define SYS_VREFCTL_VREF_1_6V (0x3UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V */
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106 #define SYS_VREFCTL_VREF_2_0V (0x7UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V */
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107 #define SYS_VREFCTL_VREF_2_5V (0xBUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V */
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108 #define SYS_VREFCTL_VREF_3_0V (0xFUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V */
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109 #define SYS_VREFCTL_VREF_AVDD (0x10UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = AVDD */
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112 /*---------------------------------------------------------------------------------------------------------*/
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113 /* USBPHY constant definitions. (Write-Protection Register) */
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114 /*---------------------------------------------------------------------------------------------------------*/
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115 #define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device */
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116 #define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host */
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117 #define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device */
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118 #define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device */
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121 /*---------------------------------------------------------------------------------------------------------*/
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122 /* PLCTL constant definitions. (Write-Protection Register) */
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123 /*---------------------------------------------------------------------------------------------------------*/
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124 #define SYS_PLCTL_PLSEL_PL0 (0x0UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 0 */
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125 #define SYS_PLCTL_PLSEL_PL1 (0x1UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 1 */
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126 #define SYS_PLCTL_MVRS_LDO (0x0UL<<SYS_PLCTL_MVRS_Pos) /*!< Set main voltage regulator type to LDO */
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127 #define SYS_PLCTL_MVRS_DCDC (0x1UL<<SYS_PLCTL_MVRS_Pos) /*!< Set main voltage regulator type to DCDC */
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130 /*---------------------------------------------------------------------------------------------------------*/
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131 /* PLSTS constant definitions. (Write-Protection Register) */
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132 /*---------------------------------------------------------------------------------------------------------*/
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133 #define SYS_PLSTS_PLSTATUS_PL0 (0x0UL<<SYS_PLSTS_PLSTATUS_Pos) /*!< Power level is power level 0 */
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134 #define SYS_PLSTS_PLSTATUS_PL1 (0x1UL<<SYS_PLSTS_PLSTATUS_Pos) /*!< Power level is power level 1 */
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135 #define SYS_PLSTS_CURMVR_LDO (0x0UL<<SYS_PLSTS_CURMVR_Pos) /*!< Main voltage regulator type is LDO */
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136 #define SYS_PLSTS_CURMVR_DCDC (0x1UL<<SYS_PLSTS_CURMVR_Pos) /*!< Main voltage regulator type is DCDC */
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139 /*---------------------------------------------------------------------------------------------------------*/
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140 /* SRAMPCTL constant definitions. (Write-Protection Register) */
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141 /*---------------------------------------------------------------------------------------------------------*/
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142 #define SYS_SRAMPCTL_SRAM_NORMAL 0x0UL /*!< Select system SRAM power mode to normal mode */
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143 #define SYS_SRAMPCTL_SRAM_RETENTION 0x1UL /*!< Select system SRAM power mode to retention mode */
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144 #define SYS_SRAMPCTL_SRAM_POWER_SHUT_DOWN 0x2UL /*!< Select system SRAM power mode to power shut down mode */
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146 /*---------------------------------------------------------------------------------------------------------*/
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147 /* SRAMPPCTL constant definitions. (Write-Protection Register) */
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148 /*---------------------------------------------------------------------------------------------------------*/
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149 #define SYS_SRAMPPCT_SRAM_NORMAL 0x0UL /*!< Select peripheral SRAM power mode to normal mode */
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150 #define SYS_SRAMPPCT_SRAM_RETENTION 0x1UL /*!< Select peripheral SRAM power mode to retention mode */
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151 #define SYS_SRAMPPCT_SRAM_POWER_SHUT_DOWN 0x2UL /*!< Select peripheral SRAM power mode to power shut down mode */
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153 /*---------------------------------------------------------------------------------------------------------*/
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154 /* Multi-Function constant definitions. */
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155 /*---------------------------------------------------------------------------------------------------------*/
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157 /* How to use below #define?
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159 Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial function,
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160 user can issue following command to achieve it.
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162 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk)) | SYS_GPA_MFPL_PA0MFP_UART0_RXD;
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163 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA1MFP_Msk)) | SYS_GPA_MFPL_PA1MFP_UART0_TXD;
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167 #define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO */
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168 #define SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for QSPI0_MOSI0 */
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169 #define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI (0x04UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SPI0_MOSI */
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170 #define SYS_GPA_MFPL_PA0MFP_SC0_CLK (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SC0_CLK */
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171 #define SYS_GPA_MFPL_PA0MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART0_RXD */
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172 #define SYS_GPA_MFPL_PA0MFP_UART1_nRTS (0x08UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_nRTS */
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173 #define SYS_GPA_MFPL_PA0MFP_I2C2_SDA (0x09UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for I2C2_SDA */
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174 #define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 (0x0cUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for BPWM0_CH0 */
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175 #define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 (0x0dUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for EPWM0_CH5 */
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176 #define SYS_GPA_MFPL_PA0MFP_DAC0_ST (0x0fUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for DAC0_ST */
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179 #define SYS_GPA_MFPL_PA1MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO */
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180 #define SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for QSPI0_MISO0 */
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181 #define SYS_GPA_MFPL_PA1MFP_SPI0_MISO (0x04UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SPI0_MISO */
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182 #define SYS_GPA_MFPL_PA1MFP_SC0_DAT (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SC0_DAT */
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183 #define SYS_GPA_MFPL_PA1MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART0_TXD */
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184 #define SYS_GPA_MFPL_PA1MFP_UART1_nCTS (0x08UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_nCTS */
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185 #define SYS_GPA_MFPL_PA1MFP_I2C2_SCL (0x09UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for I2C2_SCL */
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186 #define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 (0x0cUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for BPWM0_CH1 */
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187 #define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 (0x0dUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for EPWM0_CH4 */
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188 #define SYS_GPA_MFPL_PA1MFP_DAC1_ST (0x0fUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for DAC1_ST */
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191 #define SYS_GPA_MFPL_PA2MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO */
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192 #define SYS_GPA_MFPL_PA2MFP_QSPI0_CLK (0x03UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for QSPI0_CLK */
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193 #define SYS_GPA_MFPL_PA2MFP_SPI0_CLK (0x04UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SPI0_CLK */
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194 #define SYS_GPA_MFPL_PA2MFP_SC0_RST (0x06UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SC0_RST */
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195 #define SYS_GPA_MFPL_PA2MFP_UART4_RXD (0x07UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART4_RXD */
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196 #define SYS_GPA_MFPL_PA2MFP_UART1_RXD (0x08UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART1_RXD */
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197 #define SYS_GPA_MFPL_PA2MFP_I2C1_SDA (0x09UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C1_SDA */
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198 #define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 (0x0cUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for BPWM0_CH2 */
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199 #define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 (0x0dUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for EPWM0_CH3 */
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202 #define SYS_GPA_MFPL_PA3MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO */
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203 #define SYS_GPA_MFPL_PA3MFP_QSPI0_SS (0x03UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for QSPI0_SS */
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204 #define SYS_GPA_MFPL_PA3MFP_SPI0_SS (0x04UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SPI0_SS */
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205 #define SYS_GPA_MFPL_PA3MFP_SC0_PWR (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SC0_PWR */
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206 #define SYS_GPA_MFPL_PA3MFP_UART4_TXD (0x07UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART4_TXD */
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207 #define SYS_GPA_MFPL_PA3MFP_UART1_TXD (0x08UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART1_TXD */
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208 #define SYS_GPA_MFPL_PA3MFP_I2C1_SCL (0x09UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C1_SCL */
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209 #define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 (0x0cUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for BPWM0_CH3 */
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210 #define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 (0x0dUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EPWM0_CH2 */
\r
211 #define SYS_GPA_MFPL_PA3MFP_QEI0_B (0x0eUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for QEI0_B */
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214 #define SYS_GPA_MFPL_PA4MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO */
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215 #define SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for QSPI0_MOSI1 */
\r
216 #define SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI0_I2SMCLK*/
\r
217 #define SYS_GPA_MFPL_PA4MFP_SC0_nCD (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SC0_nCD */
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218 #define SYS_GPA_MFPL_PA4MFP_UART0_nRTS (0x07UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART0_nRTS */
\r
219 #define SYS_GPA_MFPL_PA4MFP_UART5_RXD (0x08UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART5_RXD */
\r
220 #define SYS_GPA_MFPL_PA4MFP_I2C0_SDA (0x09UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for I2C0_SDA */
\r
221 #define SYS_GPA_MFPL_PA4MFP_CAN0_RXD (0x0aUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for CAN0_RXD */
\r
222 #define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 (0x0cUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for BPWM0_CH4 */
\r
223 #define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 (0x0dUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for EPWM0_CH1 */
\r
224 #define SYS_GPA_MFPL_PA4MFP_QEI0_A (0x0eUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for QEI0_A */
\r
227 #define SYS_GPA_MFPL_PA5MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO */
\r
228 #define SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1 (0x03UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for QSPI0_MISO1 */
\r
229 #define SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SPI1_I2SMCLK*/
\r
230 #define SYS_GPA_MFPL_PA5MFP_SC2_nCD (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SC2_nCD */
\r
231 #define SYS_GPA_MFPL_PA5MFP_UART0_nCTS (0x07UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART0_nCTS */
\r
232 #define SYS_GPA_MFPL_PA5MFP_UART5_TXD (0x08UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART5_TXD */
\r
233 #define SYS_GPA_MFPL_PA5MFP_I2C0_SCL (0x09UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for I2C0_SCL */
\r
234 #define SYS_GPA_MFPL_PA5MFP_CAN0_TXD (0x0aUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for CAN0_TXD */
\r
235 #define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 (0x0cUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for BPWM0_CH5 */
\r
236 #define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 (0x0dUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for EPWM0_CH0 */
\r
237 #define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX (0x0eUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for QEI0_INDEX */
\r
240 #define SYS_GPA_MFPL_PA6MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO */
\r
241 #define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_AD6 */
\r
242 #define SYS_GPA_MFPL_PA6MFP_SPI1_SS (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SPI1_SS */
\r
243 #define SYS_GPA_MFPL_PA6MFP_SC2_CLK (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SC2_CLK */
\r
244 #define SYS_GPA_MFPL_PA6MFP_UART0_RXD (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for UART0_RXD */
\r
245 #define SYS_GPA_MFPL_PA6MFP_I2C1_SDA (0x08UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for I2C1_SDA */
\r
246 #define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 (0x0bUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EPWM1_CH5 */
\r
247 #define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 (0x0cUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for BPWM1_CH3 */
\r
248 #define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT (0x0dUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for ACMP1_WLAT */
\r
249 #define SYS_GPA_MFPL_PA6MFP_TM3 (0x0eUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for TM3 */
\r
250 #define SYS_GPA_MFPL_PA6MFP_INT0 (0x0fUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for INT0 */
\r
253 #define SYS_GPA_MFPL_PA7MFP_GPIO (0x00UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO */
\r
254 #define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (0x02UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_AD7 */
\r
255 #define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (0x04UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SPI1_CLK */
\r
256 #define SYS_GPA_MFPL_PA7MFP_SC2_DAT (0x06UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SC2_DAT */
\r
257 #define SYS_GPA_MFPL_PA7MFP_UART0_TXD (0x07UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for UART0_TXD */
\r
258 #define SYS_GPA_MFPL_PA7MFP_I2C1_SCL (0x08UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for I2C1_SCL */
\r
259 #define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 (0x0bUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EPWM1_CH4 */
\r
260 #define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 (0x0cUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for BPWM1_CH2 */
\r
261 #define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT (0x0dUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for ACMP0_WLAT */
\r
262 #define SYS_GPA_MFPL_PA7MFP_TM2 (0x0eUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for TM2 */
\r
263 #define SYS_GPA_MFPL_PA7MFP_INT1 (0x0fUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for INT1 */
\r
266 #define SYS_GPA_MFPH_PA8MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO */
\r
267 #define SYS_GPA_MFPH_PA8MFP_EBI_ALE (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for EBI_ALE */
\r
268 #define SYS_GPA_MFPH_PA8MFP_SC2_CLK (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SC2_CLK */
\r
269 #define SYS_GPA_MFPH_PA8MFP_SPI2_MOSI (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SPI2_MOSI */
\r
270 #define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for USCI0_CTL1 */
\r
271 #define SYS_GPA_MFPH_PA8MFP_UART1_RXD (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for UART1_RXD */
\r
272 #define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for BPWM0_CH3 */
\r
273 #define SYS_GPA_MFPH_PA8MFP_QEI1_B (0x0aUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for QEI1_B */
\r
274 #define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 (0x0bUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for ECAP0_IC2 */
\r
275 #define SYS_GPA_MFPH_PA8MFP_TM3_EXT (0x0dUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for TM3_EXT */
\r
276 #define SYS_GPA_MFPH_PA8MFP_INT4 (0x0fUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for INT4 */
\r
279 #define SYS_GPA_MFPH_PA9MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO */
\r
280 #define SYS_GPA_MFPH_PA9MFP_EBI_MCLK (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for EBI_MCLK */
\r
281 #define SYS_GPA_MFPH_PA9MFP_SC2_DAT (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SC2_DAT */
\r
282 #define SYS_GPA_MFPH_PA9MFP_SPI2_MISO (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SPI2_MISO */
\r
283 #define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for USCI0_DAT1 */
\r
284 #define SYS_GPA_MFPH_PA9MFP_UART1_TXD (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for UART1_TXD */
\r
285 #define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 (0x09UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for BPWM0_CH2 */
\r
286 #define SYS_GPA_MFPH_PA9MFP_QEI1_A (0x0aUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for QEI1_A */
\r
287 #define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 (0x0bUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for ECAP0_IC1 */
\r
288 #define SYS_GPA_MFPH_PA9MFP_TM2_EXT (0x0dUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for TM2_EXT */
\r
291 #define SYS_GPA_MFPH_PA10MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for GPIO */
\r
292 #define SYS_GPA_MFPH_PA10MFP_ACMP1_P0 (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for ACMP1_P0 */
\r
293 #define SYS_GPA_MFPH_PA10MFP_EBI_nWR (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for EBI_nWR */
\r
294 #define SYS_GPA_MFPH_PA10MFP_SC2_RST (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for SC2_RST */
\r
295 #define SYS_GPA_MFPH_PA10MFP_SPI2_CLK (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for SPI2_CLK */
\r
296 #define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 (0x06UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for USCI0_DAT0 */
\r
297 #define SYS_GPA_MFPH_PA10MFP_I2C2_SDA (0x07UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for I2C2_SDA */
\r
298 #define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 (0x09UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for BPWM0_CH1 */
\r
299 #define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX (0x0aUL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for QEI1_INDEX */
\r
300 #define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 (0x0bUL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for ECAP0_IC0 */
\r
301 #define SYS_GPA_MFPH_PA10MFP_TM1_EXT (0x0dUL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for TM1_EXT */
\r
302 #define SYS_GPA_MFPH_PA10MFP_DAC0_ST (0x0eUL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for DAC0_ST */
\r
305 #define SYS_GPA_MFPH_PA11MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for GPIO */
\r
306 #define SYS_GPA_MFPH_PA11MFP_ACMP0_P0 (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for ACMP0_P0 */
\r
307 #define SYS_GPA_MFPH_PA11MFP_EBI_nRD (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for EBI_nRD */
\r
308 #define SYS_GPA_MFPH_PA11MFP_SC2_PWR (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for SC2_PWR */
\r
309 #define SYS_GPA_MFPH_PA11MFP_SPI2_SS (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for SPI2_SS */
\r
310 #define SYS_GPA_MFPH_PA11MFP_USCI0_CLK (0x06UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for USCI0_CLK */
\r
311 #define SYS_GPA_MFPH_PA11MFP_I2C2_SCL (0x07UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for I2C2_SCL */
\r
312 #define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for BPWM0_CH0 */
\r
313 #define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT (0x0aUL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for EPWM0_SYNC_OUT*/
\r
314 #define SYS_GPA_MFPH_PA11MFP_TM0_EXT (0x0dUL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for TM0_EXT */
\r
315 #define SYS_GPA_MFPH_PA11MFP_DAC1_ST (0x0eUL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for DAC1_ST */
\r
318 #define SYS_GPA_MFPH_PA12MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for GPIO */
\r
319 #define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK (0x02UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for I2S0_BCLK */
\r
320 #define SYS_GPA_MFPH_PA12MFP_UART4_TXD (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for UART4_TXD */
\r
321 #define SYS_GPA_MFPH_PA12MFP_I2C1_SCL (0x04UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for I2C1_SCL */
\r
322 #define SYS_GPA_MFPH_PA12MFP_SPI2_SS (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for SPI2_SS */
\r
323 #define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (0x06UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for CAN0_TXD */
\r
324 #define SYS_GPA_MFPH_PA12MFP_SC2_PWR (0x07UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for SC2_PWR */
\r
325 #define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 (0x0bUL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for BPWM1_CH2 */
\r
326 #define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX (0x0cUL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for QEI1_INDEX */
\r
327 #define SYS_GPA_MFPH_PA12MFP_USB_VBUS (0x0eUL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for USB_VBUS */
\r
330 #define SYS_GPA_MFPH_PA13MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for GPIO */
\r
331 #define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK (0x02UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for I2S0_MCLK */
\r
332 #define SYS_GPA_MFPH_PA13MFP_UART4_RXD (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for UART4_RXD */
\r
333 #define SYS_GPA_MFPH_PA13MFP_I2C1_SDA (0x04UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for I2C1_SDA */
\r
334 #define SYS_GPA_MFPH_PA13MFP_SPI2_CLK (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for SPI2_CLK */
\r
335 #define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for CAN0_RXD */
\r
336 #define SYS_GPA_MFPH_PA13MFP_SC2_RST (0x07UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for SC2_RST */
\r
337 #define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 (0x0bUL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for BPWM1_CH3 */
\r
338 #define SYS_GPA_MFPH_PA13MFP_QEI1_A (0x0cUL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for QEI1_A */
\r
339 #define SYS_GPA_MFPH_PA13MFP_USB_D_N (0x0eUL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for USB_D_N */
\r
342 #define SYS_GPA_MFPH_PA14MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for GPIO */
\r
343 #define SYS_GPA_MFPH_PA14MFP_I2S0_DI (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for I2S0_DI */
\r
344 #define SYS_GPA_MFPH_PA14MFP_UART0_TXD (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for UART0_TXD */
\r
345 #define SYS_GPA_MFPH_PA14MFP_SPI2_MISO (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for SPI2_MISO */
\r
346 #define SYS_GPA_MFPH_PA14MFP_I2C2_SCL (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for I2C2_SCL */
\r
347 #define SYS_GPA_MFPH_PA14MFP_SC2_DAT (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for SC2_DAT */
\r
348 #define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 (0x0bUL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for BPWM1_CH4 */
\r
349 #define SYS_GPA_MFPH_PA14MFP_QEI1_B (0x0cUL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for QEI1_B */
\r
350 #define SYS_GPA_MFPH_PA14MFP_USB_D_P (0x0eUL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for USB_D_P */
\r
353 #define SYS_GPA_MFPH_PA15MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for GPIO */
\r
354 #define SYS_GPA_MFPH_PA15MFP_I2S0_DO (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for I2S0_DO */
\r
355 #define SYS_GPA_MFPH_PA15MFP_UART0_RXD (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for UART0_RXD */
\r
356 #define SYS_GPA_MFPH_PA15MFP_SPI2_MOSI (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for SPI2_MOSI */
\r
357 #define SYS_GPA_MFPH_PA15MFP_I2C2_SDA (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for I2C2_SDA */
\r
358 #define SYS_GPA_MFPH_PA15MFP_SC2_CLK (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for SC2_CLK */
\r
359 #define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 (0x0bUL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for BPWM1_CH5 */
\r
360 #define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN (0x0cUL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for EPWM0_SYNC_IN*/
\r
361 #define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID (0x0eUL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for USB_OTG_ID */
\r
364 #define SYS_GPB_MFPL_PB0MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO */
\r
365 #define SYS_GPB_MFPL_PB0MFP_EADC0_CH0 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EADC0_CH0 */
\r
366 #define SYS_GPB_MFPL_PB0MFP_EBI_ADR9 (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_ADR9 */
\r
367 #define SYS_GPB_MFPL_PB0MFP_SD0_CMD (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SD0_CMD */
\r
368 #define SYS_GPB_MFPL_PB0MFP_UART2_RXD (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD */
\r
369 #define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_I2SMCLK*/
\r
370 #define SYS_GPB_MFPL_PB0MFP_I2C1_SDA (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for I2C1_SDA */
\r
371 #define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 (0x0bUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EPWM0_CH5 */
\r
372 #define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 (0x0cUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EPWM1_CH5 */
\r
373 #define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 (0x0dUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EPWM0_BRAKE1*/
\r
376 #define SYS_GPB_MFPL_PB1MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO */
\r
377 #define SYS_GPB_MFPL_PB1MFP_EADC0_CH1 (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EADC0_CH1 */
\r
378 #define SYS_GPB_MFPL_PB1MFP_EBI_ADR8 (0x02UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EBI_ADR8 */
\r
379 #define SYS_GPB_MFPL_PB1MFP_SD0_CLK (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SD0_CLK */
\r
380 #define SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI1_I2SMCLK*/
\r
381 #define SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK (0x06UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI3_I2SMCLK*/
\r
382 #define SYS_GPB_MFPL_PB1MFP_UART2_TXD (0x07UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for UART2_TXD */
\r
383 #define SYS_GPB_MFPL_PB1MFP_USCI1_CLK (0x08UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for USCI1_CLK */
\r
384 #define SYS_GPB_MFPL_PB1MFP_I2C1_SCL (0x09UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for I2C1_SCL */
\r
385 #define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK (0x0aUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for I2S0_LRCK */
\r
386 #define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 (0x0bUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EPWM0_CH4 */
\r
387 #define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 (0x0cUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EPWM1_CH4 */
\r
388 #define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 (0x0dUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EPWM0_BRAKE0*/
\r
391 #define SYS_GPB_MFPL_PB2MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO */
\r
392 #define SYS_GPB_MFPL_PB2MFP_EADC0_CH2 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EADC0_CH2 */
\r
393 #define SYS_GPB_MFPL_PB2MFP_ACMP0_P1 (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for ACMP0_P1 */
\r
394 #define SYS_GPB_MFPL_PB2MFP_EBI_ADR3 (0x02UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EBI_ADR3 */
\r
395 #define SYS_GPB_MFPL_PB2MFP_SD0_DAT0 (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SD0_DAT0 */
\r
396 #define SYS_GPB_MFPL_PB2MFP_SPI1_SS (0x05UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI1_SS */
\r
397 #define SYS_GPB_MFPL_PB2MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD */
\r
398 #define SYS_GPB_MFPL_PB2MFP_UART5_nCTS (0x07UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART5_nCTS */
\r
399 #define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 (0x08UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for USCI1_DAT0 */
\r
400 #define SYS_GPB_MFPL_PB2MFP_SC0_PWR (0x09UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SC0_PWR */
\r
401 #define SYS_GPB_MFPL_PB2MFP_I2S0_DO (0x0aUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for I2S0_DO */
\r
402 #define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 (0x0bUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EPWM0_CH3 */
\r
403 #define SYS_GPB_MFPL_PB2MFP_TM3 (0x0eUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for TM3 */
\r
404 #define SYS_GPB_MFPL_PB2MFP_INT3 (0x0fUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for INT3 */
\r
407 #define SYS_GPB_MFPL_PB3MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO */
\r
408 #define SYS_GPB_MFPL_PB3MFP_EADC0_CH3 (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EADC0_CH3 */
\r
409 #define SYS_GPB_MFPL_PB3MFP_ACMP0_N (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for ACMP0_N */
\r
410 #define SYS_GPB_MFPL_PB3MFP_EBI_ADR2 (0x02UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EBI_ADR2 */
\r
411 #define SYS_GPB_MFPL_PB3MFP_SD0_DAT1 (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SD0_DAT1 */
\r
412 #define SYS_GPB_MFPL_PB3MFP_SPI1_CLK (0x05UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI1_CLK */
\r
413 #define SYS_GPB_MFPL_PB3MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD */
\r
414 #define SYS_GPB_MFPL_PB3MFP_UART5_nRTS (0x07UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART5_nRTS */
\r
415 #define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 (0x08UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for USCI1_DAT1 */
\r
416 #define SYS_GPB_MFPL_PB3MFP_SC0_RST (0x09UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SC0_RST */
\r
417 #define SYS_GPB_MFPL_PB3MFP_I2S0_DI (0x0aUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for I2S0_DI */
\r
418 #define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 (0x0bUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EPWM0_CH2 */
\r
419 #define SYS_GPB_MFPL_PB3MFP_TM2 (0x0eUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for TM2 */
\r
420 #define SYS_GPB_MFPL_PB3MFP_INT2 (0x0fUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for INT2 */
\r
423 #define SYS_GPB_MFPL_PB4MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO */
\r
424 #define SYS_GPB_MFPL_PB4MFP_EADC0_CH4 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EADC0_CH4 */
\r
425 #define SYS_GPB_MFPL_PB4MFP_ACMP1_P1 (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ACMP1_P1 */
\r
426 #define SYS_GPB_MFPL_PB4MFP_EBI_ADR1 (0x02UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_ADR1 */
\r
427 #define SYS_GPB_MFPL_PB4MFP_SD0_DAT2 (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SD0_DAT2 */
\r
428 #define SYS_GPB_MFPL_PB4MFP_SPI1_MOSI (0x05UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI1_MOSI */
\r
429 #define SYS_GPB_MFPL_PB4MFP_I2C0_SDA (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for I2C0_SDA */
\r
430 #define SYS_GPB_MFPL_PB4MFP_UART5_RXD (0x07UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART5_RXD */
\r
431 #define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 (0x08UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for USCI1_CTL1 */
\r
432 #define SYS_GPB_MFPL_PB4MFP_SC0_DAT (0x09UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SC0_DAT */
\r
433 #define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK (0x0aUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for I2S0_MCLK */
\r
434 #define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 (0x0bUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EPWM0_CH1 */
\r
435 #define SYS_GPB_MFPL_PB4MFP_TM1 (0x0eUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for TM1 */
\r
436 #define SYS_GPB_MFPL_PB4MFP_INT1 (0x0fUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for INT1 */
\r
439 #define SYS_GPB_MFPL_PB5MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO */
\r
440 #define SYS_GPB_MFPL_PB5MFP_EADC0_CH5 (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EADC0_CH5 */
\r
441 #define SYS_GPB_MFPL_PB5MFP_ACMP1_N (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ACMP1_N */
\r
442 #define SYS_GPB_MFPL_PB5MFP_EBI_ADR0 (0x02UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_ADR0 */
\r
443 #define SYS_GPB_MFPL_PB5MFP_SD0_DAT3 (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SD0_DAT3 */
\r
444 #define SYS_GPB_MFPL_PB5MFP_SPI1_MISO (0x05UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI1_MISO */
\r
445 #define SYS_GPB_MFPL_PB5MFP_I2C0_SCL (0x06UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for I2C0_SCL */
\r
446 #define SYS_GPB_MFPL_PB5MFP_UART5_TXD (0x07UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART5_TXD */
\r
447 #define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 (0x08UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for USCI1_CTL0 */
\r
448 #define SYS_GPB_MFPL_PB5MFP_SC0_CLK (0x09UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SC0_CLK */
\r
449 #define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK (0x0aUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for I2S0_BCLK */
\r
450 #define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 (0x0bUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EPWM0_CH0 */
\r
451 #define SYS_GPB_MFPL_PB5MFP_TM0 (0x0eUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for TM0 */
\r
452 #define SYS_GPB_MFPL_PB5MFP_INT0 (0x0fUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for INT0 */
\r
455 #define SYS_GPB_MFPL_PB6MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO */
\r
456 #define SYS_GPB_MFPL_PB6MFP_EADC0_CH6 (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EADC0_CH6 */
\r
457 #define SYS_GPB_MFPL_PB6MFP_EBI_nWRH (0x02UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_nWRH */
\r
458 #define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for USCI1_DAT1 */
\r
459 #define SYS_GPB_MFPL_PB6MFP_UART1_RXD (0x06UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for UART1_RXD */
\r
460 #define SYS_GPB_MFPL_PB6MFP_EBI_nCS1 (0x08UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_nCS1 */
\r
461 #define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 (0x0aUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for BPWM1_CH5 */
\r
462 #define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 (0x0bUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EPWM1_BRAKE1*/
\r
463 #define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 (0x0cUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EPWM1_CH5 */
\r
464 #define SYS_GPB_MFPL_PB6MFP_INT4 (0x0dUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for INT4 */
\r
465 #define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN (0x0eUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for USB_VBUS_EN */
\r
466 #define SYS_GPB_MFPL_PB6MFP_ACMP1_O (0x0fUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ACMP1_O */
\r
469 #define SYS_GPB_MFPL_PB7MFP_GPIO (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO */
\r
470 #define SYS_GPB_MFPL_PB7MFP_EADC0_CH7 (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EADC0_CH7 */
\r
471 #define SYS_GPB_MFPL_PB7MFP_EBI_nWRL (0x02UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_nWRL */
\r
472 #define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for USCI1_DAT0 */
\r
473 #define SYS_GPB_MFPL_PB7MFP_UART1_TXD (0x06UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for UART1_TXD */
\r
474 #define SYS_GPB_MFPL_PB7MFP_EBI_nCS0 (0x08UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_nCS0 */
\r
475 #define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 (0x0aUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for BPWM1_CH4 */
\r
476 #define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 (0x0bUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EPWM1_BRAKE0*/
\r
477 #define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 (0x0cUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EPWM1_CH4 */
\r
478 #define SYS_GPB_MFPL_PB7MFP_INT5 (0x0dUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for INT5 */
\r
479 #define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST (0x0eUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for USB_VBUS_ST */
\r
480 #define SYS_GPB_MFPL_PB7MFP_ACMP0_O (0x0fUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ACMP0_O */
\r
483 #define SYS_GPB_MFPH_PB8MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO */
\r
484 #define SYS_GPB_MFPH_PB8MFP_EADC0_CH8 (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EADC0_CH8 */
\r
485 #define SYS_GPB_MFPH_PB8MFP_EBI_ADR19 (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EBI_ADR19 */
\r
486 #define SYS_GPB_MFPH_PB8MFP_USCI1_CLK (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for USCI1_CLK */
\r
487 #define SYS_GPB_MFPH_PB8MFP_UART0_RXD (0x05UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART0_RXD */
\r
488 #define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (0x06UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART1_nRTS */
\r
489 #define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for I2C1_SMBSUS */
\r
490 #define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 (0x0aUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for BPWM1_CH3 */
\r
491 #define SYS_GPB_MFPH_PB8MFP_SPI3_MOSI (0x0bUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for SPI3_MOSI */
\r
492 #define SYS_GPB_MFPH_PB8MFP_INT6 (0x0dUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for INT6 */
\r
495 #define SYS_GPB_MFPH_PB9MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO */
\r
496 #define SYS_GPB_MFPH_PB9MFP_EADC0_CH9 (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EADC0_CH9 */
\r
497 #define SYS_GPB_MFPH_PB9MFP_EBI_ADR18 (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EBI_ADR18 */
\r
498 #define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for USCI1_CTL1 */
\r
499 #define SYS_GPB_MFPH_PB9MFP_UART0_TXD (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART0_TXD */
\r
500 #define SYS_GPB_MFPH_PB9MFP_UART1_nCTS (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART1_nCTS */
\r
501 #define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for I2C1_SMBAL */
\r
502 #define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 (0x0aUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for BPWM1_CH2 */
\r
503 #define SYS_GPB_MFPH_PB9MFP_SPI3_MISO (0x0bUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for SPI3_MISO */
\r
504 #define SYS_GPB_MFPH_PB9MFP_INT7 (0x0dUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for INT7 */
\r
507 #define SYS_GPB_MFPH_PB10MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for GPIO */
\r
508 #define SYS_GPB_MFPH_PB10MFP_EADC0_CH10 (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for EADC0_CH10 */
\r
509 #define SYS_GPB_MFPH_PB10MFP_EBI_ADR17 (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for EBI_ADR17 */
\r
510 #define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for USCI1_CTL0 */
\r
511 #define SYS_GPB_MFPH_PB10MFP_UART0_nRTS (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for UART0_nRTS */
\r
512 #define SYS_GPB_MFPH_PB10MFP_UART4_RXD (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for UART4_RXD */
\r
513 #define SYS_GPB_MFPH_PB10MFP_I2C1_SDA (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for I2C1_SDA */
\r
514 #define SYS_GPB_MFPH_PB10MFP_CAN0_RXD (0x08UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for CAN0_RXD */
\r
515 #define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 (0x0aUL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for BPWM1_CH1 */
\r
516 #define SYS_GPB_MFPH_PB10MFP_SPI3_SS (0x0bUL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for SPI3_SS */
\r
519 #define SYS_GPB_MFPH_PB11MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for GPIO */
\r
520 #define SYS_GPB_MFPH_PB11MFP_EADC0_CH11 (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for EADC0_CH11 */
\r
521 #define SYS_GPB_MFPH_PB11MFP_EBI_ADR16 (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for EBI_ADR16 */
\r
522 #define SYS_GPB_MFPH_PB11MFP_UART0_nCTS (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for UART0_nCTS */
\r
523 #define SYS_GPB_MFPH_PB11MFP_UART4_TXD (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for UART4_TXD */
\r
524 #define SYS_GPB_MFPH_PB11MFP_I2C1_SCL (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for I2C1_SCL */
\r
525 #define SYS_GPB_MFPH_PB11MFP_CAN0_TXD (0x08UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for CAN0_TXD */
\r
526 #define SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for SPI0_I2SMCLK*/
\r
527 #define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 (0x0aUL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for BPWM1_CH0 */
\r
528 #define SYS_GPB_MFPH_PB11MFP_SPI3_CLK (0x0bUL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for SPI3_CLK */
\r
531 #define SYS_GPB_MFPH_PB12MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for GPIO */
\r
532 #define SYS_GPB_MFPH_PB12MFP_EADC0_CH12 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for EADC0_CH12 */
\r
533 #define SYS_GPB_MFPH_PB12MFP_DAC0_OUT (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for DAC0_OUT */
\r
534 #define SYS_GPB_MFPH_PB12MFP_ACMP0_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for ACMP0_P2 */
\r
535 #define SYS_GPB_MFPH_PB12MFP_ACMP1_P2 (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for ACMP1_P2 */
\r
536 #define SYS_GPB_MFPH_PB12MFP_EBI_AD15 (0x02UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for EBI_AD15 */
\r
537 #define SYS_GPB_MFPH_PB12MFP_SC1_CLK (0x03UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for SC1_CLK */
\r
538 #define SYS_GPB_MFPH_PB12MFP_SPI0_MOSI (0x04UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for SPI0_MOSI */
\r
539 #define SYS_GPB_MFPH_PB12MFP_USCI0_CLK (0x05UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for USCI0_CLK */
\r
540 #define SYS_GPB_MFPH_PB12MFP_UART0_RXD (0x06UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for UART0_RXD */
\r
541 #define SYS_GPB_MFPH_PB12MFP_UART3_nCTS (0x07UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for UART3_nCTS */
\r
542 #define SYS_GPB_MFPH_PB12MFP_I2C2_SDA (0x08UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for I2C2_SDA */
\r
543 #define SYS_GPB_MFPH_PB12MFP_SD0_nCD (0x09UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for SD0_nCD */
\r
544 #define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 (0x0bUL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for EPWM1_CH3 */
\r
545 #define SYS_GPB_MFPH_PB12MFP_TM3_EXT (0x0dUL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for TM3_EXT */
\r
548 #define SYS_GPB_MFPH_PB13MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for GPIO */
\r
549 #define SYS_GPB_MFPH_PB13MFP_EADC0_CH13 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for EADC0_CH13 */
\r
550 #define SYS_GPB_MFPH_PB13MFP_DAC1_OUT (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for DAC1_OUT */
\r
551 #define SYS_GPB_MFPH_PB13MFP_ACMP0_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for ACMP0_P3 */
\r
552 #define SYS_GPB_MFPH_PB13MFP_ACMP1_P3 (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for ACMP1_P3 */
\r
553 #define SYS_GPB_MFPH_PB13MFP_EBI_AD14 (0x02UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for EBI_AD14 */
\r
554 #define SYS_GPB_MFPH_PB13MFP_SC1_DAT (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for SC1_DAT */
\r
555 #define SYS_GPB_MFPH_PB13MFP_SPI0_MISO (0x04UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for SPI0_MISO */
\r
556 #define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 (0x05UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for USCI0_DAT0 */
\r
557 #define SYS_GPB_MFPH_PB13MFP_UART0_TXD (0x06UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for UART0_TXD */
\r
558 #define SYS_GPB_MFPH_PB13MFP_UART3_nRTS (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for UART3_nRTS */
\r
559 #define SYS_GPB_MFPH_PB13MFP_I2C2_SCL (0x08UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for I2C2_SCL */
\r
560 #define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 (0x0bUL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for EPWM1_CH2 */
\r
561 #define SYS_GPB_MFPH_PB13MFP_TM2_EXT (0x0dUL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for TM2_EXT */
\r
564 #define SYS_GPB_MFPH_PB14MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for GPIO */
\r
565 #define SYS_GPB_MFPH_PB14MFP_EADC0_CH14 (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for EADC0_CH14 */
\r
566 #define SYS_GPB_MFPH_PB14MFP_EBI_AD13 (0x02UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for EBI_AD13 */
\r
567 #define SYS_GPB_MFPH_PB14MFP_SC1_RST (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for SC1_RST */
\r
568 #define SYS_GPB_MFPH_PB14MFP_SPI0_CLK (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for SPI0_CLK */
\r
569 #define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 (0x05UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for USCI0_DAT1 */
\r
570 #define SYS_GPB_MFPH_PB14MFP_UART0_nRTS (0x06UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for UART0_nRTS */
\r
571 #define SYS_GPB_MFPH_PB14MFP_UART3_RXD (0x07UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for UART3_RXD */
\r
572 #define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS (0x08UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for I2C2_SMBSUS*/
\r
573 #define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 (0x0bUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for EPWM1_CH1 */
\r
574 #define SYS_GPB_MFPH_PB14MFP_TM1_EXT (0x0dUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for TM1_EXT */
\r
575 #define SYS_GPB_MFPH_PB14MFP_CLKO (0x0eUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for CLKO */
\r
576 #define SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST (0x0fUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for USB_VBUS_ST*/
\r
579 #define SYS_GPB_MFPH_PB15MFP_GPIO (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for GPIO */
\r
580 #define SYS_GPB_MFPH_PB15MFP_EADC0_CH15 (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for EADC0_CH15 */
\r
581 #define SYS_GPB_MFPH_PB15MFP_EBI_AD12 (0x02UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for EBI_AD12 */
\r
582 #define SYS_GPB_MFPH_PB15MFP_SC1_PWR (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for SC1_PWR */
\r
583 #define SYS_GPB_MFPH_PB15MFP_SPI0_SS (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for SPI0_SS */
\r
584 #define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 (0x05UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for USCI0_CTL1 */
\r
585 #define SYS_GPB_MFPH_PB15MFP_UART0_nCTS (0x06UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for UART0_nCTS */
\r
586 #define SYS_GPB_MFPH_PB15MFP_UART3_TXD (0x07UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for UART3_TXD */
\r
587 #define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL (0x08UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for I2C2_SMBAL */
\r
588 #define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 (0x0bUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for EPWM1_CH0 */
\r
589 #define SYS_GPB_MFPH_PB15MFP_TM0_EXT (0x0dUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for TM0_EXT */
\r
590 #define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN (0x0eUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for USB_VBUS_EN*/
\r
593 #define SYS_GPC_MFPL_PC0MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO */
\r
594 #define SYS_GPC_MFPL_PC0MFP_EBI_AD0 (0x02UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_AD0 */
\r
595 #define SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for QSPI0_MOSI0 */
\r
596 #define SYS_GPC_MFPL_PC0MFP_SC1_CLK (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SC1_CLK */
\r
597 #define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK (0x06UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2S0_LRCK */
\r
598 #define SYS_GPC_MFPL_PC0MFP_SPI1_SS (0x07UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SPI1_SS */
\r
599 #define SYS_GPC_MFPL_PC0MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_RXD */
\r
600 #define SYS_GPC_MFPL_PC0MFP_I2C0_SDA (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2C0_SDA */
\r
601 #define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 (0x0cUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EPWM1_CH5 */
\r
602 #define SYS_GPC_MFPL_PC0MFP_ACMP1_O (0x0eUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for ACMP1_O */
\r
605 #define SYS_GPC_MFPL_PC1MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO */
\r
606 #define SYS_GPC_MFPL_PC1MFP_EBI_AD1 (0x02UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD1 */
\r
607 #define SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for QSPI0_MISO0 */
\r
608 #define SYS_GPC_MFPL_PC1MFP_SC1_DAT (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for SC1_DAT */
\r
609 #define SYS_GPC_MFPL_PC1MFP_I2S0_DO (0x06UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2S0_DO */
\r
610 #define SYS_GPC_MFPL_PC1MFP_SPI1_CLK (0x07UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for SPI1_CLK */
\r
611 #define SYS_GPC_MFPL_PC1MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_TXD */
\r
612 #define SYS_GPC_MFPL_PC1MFP_I2C0_SCL (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2C0_SCL */
\r
613 #define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 (0x0cUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EPWM1_CH4 */
\r
614 #define SYS_GPC_MFPL_PC1MFP_ACMP0_O (0x0eUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for ACMP0_O */
\r
617 #define SYS_GPC_MFPL_PC2MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO */
\r
618 #define SYS_GPC_MFPL_PC2MFP_EBI_AD2 (0x02UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD2 */
\r
619 #define SYS_GPC_MFPL_PC2MFP_QSPI0_CLK (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for QSPI0_CLK */
\r
620 #define SYS_GPC_MFPL_PC2MFP_SC1_RST (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SC1_RST */
\r
621 #define SYS_GPC_MFPL_PC2MFP_I2S0_DI (0x06UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2S0_DI */
\r
622 #define SYS_GPC_MFPL_PC2MFP_SPI1_MOSI (0x07UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI1_MOSI */
\r
623 #define SYS_GPC_MFPL_PC2MFP_UART2_nCTS (0x08UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART2_nCTS */
\r
624 #define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2C0_SMBSUS */
\r
625 #define SYS_GPC_MFPL_PC2MFP_UART3_RXD (0x0bUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART3_RXD */
\r
626 #define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 (0x0cUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EPWM1_CH3 */
\r
629 #define SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO */
\r
630 #define SYS_GPC_MFPL_PC3MFP_EBI_AD3 (0x02UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD3 */
\r
631 #define SYS_GPC_MFPL_PC3MFP_QSPI0_SS (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for QSPI0_SS */
\r
632 #define SYS_GPC_MFPL_PC3MFP_SC1_PWR (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SC1_PWR */
\r
633 #define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK (0x06UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2S0_MCLK */
\r
634 #define SYS_GPC_MFPL_PC3MFP_SPI1_MISO (0x07UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI1_MISO */
\r
635 #define SYS_GPC_MFPL_PC3MFP_UART2_nRTS (0x08UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART2_nRTS */
\r
636 #define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2C0_SMBAL */
\r
637 #define SYS_GPC_MFPL_PC3MFP_UART3_TXD (0x0bUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART3_TXD */
\r
638 #define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 (0x0cUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EPWM1_CH2 */
\r
641 #define SYS_GPC_MFPL_PC4MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO */
\r
642 #define SYS_GPC_MFPL_PC4MFP_EBI_AD4 (0x02UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD4 */
\r
643 #define SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 (0x04UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for QSPI0_MOSI1 */
\r
644 #define SYS_GPC_MFPL_PC4MFP_SC1_nCD (0x05UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SC1_nCD */
\r
645 #define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK (0x06UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2S0_BCLK */
\r
646 #define SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK (0x07UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SPI1_I2SMCLK*/
\r
647 #define SYS_GPC_MFPL_PC4MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART2_RXD */
\r
648 #define SYS_GPC_MFPL_PC4MFP_I2C1_SDA (0x09UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2C1_SDA */
\r
649 #define SYS_GPC_MFPL_PC4MFP_CAN0_RXD (0x0aUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for CAN0_RXD */
\r
650 #define SYS_GPC_MFPL_PC4MFP_UART4_RXD (0x0bUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART4_RXD */
\r
651 #define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 (0x0cUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EPWM1_CH1 */
\r
654 #define SYS_GPC_MFPL_PC5MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO */
\r
655 #define SYS_GPC_MFPL_PC5MFP_EBI_AD5 (0x02UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_AD5 */
\r
656 #define SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 (0x04UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for QSPI0_MISO1 */
\r
657 #define SYS_GPC_MFPL_PC5MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART2_TXD */
\r
658 #define SYS_GPC_MFPL_PC5MFP_I2C1_SCL (0x09UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for I2C1_SCL */
\r
659 #define SYS_GPC_MFPL_PC5MFP_CAN0_TXD (0x0aUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for CAN0_TXD */
\r
660 #define SYS_GPC_MFPL_PC5MFP_UART4_TXD (0x0bUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART4_TXD */
\r
661 #define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 (0x0cUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EPWM1_CH0 */
\r
664 #define SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO */
\r
665 #define SYS_GPC_MFPL_PC6MFP_EBI_AD8 (0x02UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD8 */
\r
666 #define SYS_GPC_MFPL_PC6MFP_SPI1_MOSI (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for SPI1_MOSI */
\r
667 #define SYS_GPC_MFPL_PC6MFP_UART4_RXD (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART4_RXD */
\r
668 #define SYS_GPC_MFPL_PC6MFP_SC2_RST (0x06UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for SC2_RST */
\r
669 #define SYS_GPC_MFPL_PC6MFP_UART0_nRTS (0x07UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART0_nRTS */
\r
670 #define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS (0x08UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for I2C1_SMBSUS */
\r
671 #define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 (0x0bUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EPWM1_CH3 */
\r
672 #define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 (0x0cUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for BPWM1_CH1 */
\r
673 #define SYS_GPC_MFPL_PC6MFP_TM1 (0x0eUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for TM1 */
\r
674 #define SYS_GPC_MFPL_PC6MFP_INT2 (0x0fUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for INT2 */
\r
677 #define SYS_GPC_MFPL_PC7MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO */
\r
678 #define SYS_GPC_MFPL_PC7MFP_EBI_AD9 (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD9 */
\r
679 #define SYS_GPC_MFPL_PC7MFP_SPI1_MISO (0x04UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for SPI1_MISO */
\r
680 #define SYS_GPC_MFPL_PC7MFP_UART4_TXD (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART4_TXD */
\r
681 #define SYS_GPC_MFPL_PC7MFP_SC2_PWR (0x06UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for SC2_PWR */
\r
682 #define SYS_GPC_MFPL_PC7MFP_UART0_nCTS (0x07UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART0_nCTS */
\r
683 #define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL (0x08UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for I2C1_SMBAL */
\r
684 #define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 (0x0bUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EPWM1_CH2 */
\r
685 #define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 (0x0cUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for BPWM1_CH0 */
\r
686 #define SYS_GPC_MFPL_PC7MFP_TM0 (0x0eUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for TM0 */
\r
687 #define SYS_GPC_MFPL_PC7MFP_INT3 (0x0fUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for INT3 */
\r
690 #define SYS_GPC_MFPH_PC8MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for GPIO */
\r
691 #define SYS_GPC_MFPH_PC8MFP_EBI_ADR16 (0x02UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for EBI_ADR16 */
\r
692 #define SYS_GPC_MFPH_PC8MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for I2C0_SDA */
\r
693 #define SYS_GPC_MFPH_PC8MFP_UART4_nCTS (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for UART4_nCTS */
\r
694 #define SYS_GPC_MFPH_PC8MFP_UART1_RXD (0x08UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for UART1_RXD */
\r
695 #define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 (0x0bUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for EPWM1_CH1 */
\r
696 #define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 (0x0cUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for BPWM1_CH4 */
\r
699 #define SYS_GPC_MFPH_PC9MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO */
\r
700 #define SYS_GPC_MFPH_PC9MFP_EBI_ADR7 (0x02UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EBI_ADR7 */
\r
701 #define SYS_GPC_MFPH_PC9MFP_SPI3_SS (0x06UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SPI3_SS */
\r
702 #define SYS_GPC_MFPH_PC9MFP_UART3_RXD (0x07UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for UART3_RXD */
\r
703 #define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 (0x0cUL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EPWM1_CH3 */
\r
706 #define SYS_GPC_MFPH_PC10MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for GPIO */
\r
707 #define SYS_GPC_MFPH_PC10MFP_EBI_ADR6 (0x02UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for EBI_ADR6 */
\r
708 #define SYS_GPC_MFPH_PC10MFP_SPI3_CLK (0x06UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for SPI3_CLK */
\r
709 #define SYS_GPC_MFPH_PC10MFP_UART3_TXD (0x07UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for UART3_TXD */
\r
710 #define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 (0x0bUL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for ECAP1_IC0 */
\r
711 #define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 (0x0cUL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for EPWM1_CH2 */
\r
714 #define SYS_GPC_MFPH_PC11MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for GPIO */
\r
715 #define SYS_GPC_MFPH_PC11MFP_EBI_ADR5 (0x02UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for EBI_ADR5 */
\r
716 #define SYS_GPC_MFPH_PC11MFP_UART0_RXD (0x03UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for UART0_RXD */
\r
717 #define SYS_GPC_MFPH_PC11MFP_I2C0_SDA (0x04UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for I2C0_SDA */
\r
718 #define SYS_GPC_MFPH_PC11MFP_SPI3_MOSI (0x06UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for SPI3_MOSI */
\r
719 #define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 (0x0bUL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for ECAP1_IC1 */
\r
720 #define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 (0x0cUL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for EPWM1_CH1 */
\r
721 #define SYS_GPC_MFPH_PC11MFP_ACMP1_O (0x0eUL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for ACMP1_O */
\r
724 #define SYS_GPC_MFPH_PC12MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for GPIO */
\r
725 #define SYS_GPC_MFPH_PC12MFP_EBI_ADR4 (0x02UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for EBI_ADR4 */
\r
726 #define SYS_GPC_MFPH_PC12MFP_UART0_TXD (0x03UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for UART0_TXD */
\r
727 #define SYS_GPC_MFPH_PC12MFP_I2C0_SCL (0x04UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for I2C0_SCL */
\r
728 #define SYS_GPC_MFPH_PC12MFP_SPI3_MISO (0x06UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for SPI3_MISO */
\r
729 #define SYS_GPC_MFPH_PC12MFP_SC0_nCD (0x09UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for SC0_nCD */
\r
730 #define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 (0x0bUL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for ECAP1_IC2 */
\r
731 #define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 (0x0cUL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for EPWM1_CH0 */
\r
732 #define SYS_GPC_MFPH_PC12MFP_ACMP0_O (0x0eUL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for ACMP0_O */
\r
735 #define SYS_GPC_MFPH_PC13MFP_GPIO (0x00UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for GPIO */
\r
736 #define SYS_GPC_MFPH_PC13MFP_EBI_ADR10 (0x02UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for EBI_ADR10 */
\r
737 #define SYS_GPC_MFPH_PC13MFP_SC2_nCD (0x03UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for SC2_nCD */
\r
738 #define SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for SPI2_I2SMCLK*/
\r
739 #define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 (0x06UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for USCI0_CTL0 */
\r
740 #define SYS_GPC_MFPH_PC13MFP_UART2_TXD (0x07UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for UART2_TXD */
\r
741 #define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 (0x09UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for BPWM0_CH4 */
\r
742 #define SYS_GPC_MFPH_PC13MFP_CLKO (0x0dUL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for CLKO */
\r
743 #define SYS_GPC_MFPH_PC13MFP_EADC0_ST (0x0eUL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for EADC0_ST */
\r
746 #define SYS_GPD_MFPL_PD0MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO */
\r
747 #define SYS_GPD_MFPL_PD0MFP_EBI_AD13 (0x02UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EBI_AD13 */
\r
748 #define SYS_GPD_MFPL_PD0MFP_USCI0_CLK (0x03UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for USCI0_CLK */
\r
749 #define SYS_GPD_MFPL_PD0MFP_SPI0_MOSI (0x04UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI0_MOSI */
\r
750 #define SYS_GPD_MFPL_PD0MFP_UART3_RXD (0x05UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for UART3_RXD */
\r
751 #define SYS_GPD_MFPL_PD0MFP_I2C2_SDA (0x06UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for I2C2_SDA */
\r
752 #define SYS_GPD_MFPL_PD0MFP_SC2_CLK (0x07UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SC2_CLK */
\r
753 #define SYS_GPD_MFPL_PD0MFP_TM2 (0x0eUL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for TM2 */
\r
756 #define SYS_GPD_MFPL_PD1MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO */
\r
757 #define SYS_GPD_MFPL_PD1MFP_EBI_AD12 (0x02UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_AD12 */
\r
758 #define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 (0x03UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for USCI0_DAT0 */
\r
759 #define SYS_GPD_MFPL_PD1MFP_SPI0_MISO (0x04UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SPI0_MISO */
\r
760 #define SYS_GPD_MFPL_PD1MFP_UART3_TXD (0x05UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for UART3_TXD */
\r
761 #define SYS_GPD_MFPL_PD1MFP_I2C2_SCL (0x06UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for I2C2_SCL */
\r
762 #define SYS_GPD_MFPL_PD1MFP_SC2_DAT (0x07UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SC2_DAT */
\r
765 #define SYS_GPD_MFPL_PD2MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO */
\r
766 #define SYS_GPD_MFPL_PD2MFP_EBI_AD11 (0x02UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_AD11 */
\r
767 #define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 (0x03UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for USCI0_DAT1 */
\r
768 #define SYS_GPD_MFPL_PD2MFP_SPI0_CLK (0x04UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for SPI0_CLK */
\r
769 #define SYS_GPD_MFPL_PD2MFP_UART3_nCTS (0x05UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for UART3_nCTS */
\r
770 #define SYS_GPD_MFPL_PD2MFP_SC2_RST (0x07UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for SC2_RST */
\r
771 #define SYS_GPD_MFPL_PD2MFP_UART0_RXD (0x09UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for UART0_RXD */
\r
774 #define SYS_GPD_MFPL_PD3MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO */
\r
775 #define SYS_GPD_MFPL_PD3MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_AD10 */
\r
776 #define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 (0x03UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for USCI0_CTL1 */
\r
777 #define SYS_GPD_MFPL_PD3MFP_SPI0_SS (0x04UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SPI0_SS */
\r
778 #define SYS_GPD_MFPL_PD3MFP_UART3_nRTS (0x05UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for UART3_nRTS */
\r
779 #define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 (0x06UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for USCI1_CTL0 */
\r
780 #define SYS_GPD_MFPL_PD3MFP_SC2_PWR (0x07UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SC2_PWR */
\r
781 #define SYS_GPD_MFPL_PD3MFP_SC1_nCD (0x08UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SC1_nCD */
\r
782 #define SYS_GPD_MFPL_PD3MFP_UART0_TXD (0x09UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for UART0_TXD */
\r
785 #define SYS_GPD_MFPL_PD4MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO */
\r
786 #define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 (0x03UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USCI0_CTL0 */
\r
787 #define SYS_GPD_MFPL_PD4MFP_I2C1_SDA (0x04UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for I2C1_SDA */
\r
788 #define SYS_GPD_MFPL_PD4MFP_SPI1_SS (0x05UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SPI1_SS */
\r
789 #define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 (0x06UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USCI1_CTL1 */
\r
790 #define SYS_GPD_MFPL_PD4MFP_SC1_CLK (0x08UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SC1_CLK */
\r
791 #define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST (0x0eUL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USB_VBUS_ST */
\r
794 #define SYS_GPD_MFPL_PD5MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO */
\r
795 #define SYS_GPD_MFPL_PD5MFP_I2C1_SCL (0x04UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for I2C1_SCL */
\r
796 #define SYS_GPD_MFPL_PD5MFP_SPI1_CLK (0x05UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SPI1_CLK */
\r
797 #define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 (0x06UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for USCI1_DAT0 */
\r
798 #define SYS_GPD_MFPL_PD5MFP_SC1_DAT (0x08UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SC1_DAT */
\r
801 #define SYS_GPD_MFPL_PD6MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO */
\r
802 #define SYS_GPD_MFPL_PD6MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART1_RXD */
\r
803 #define SYS_GPD_MFPL_PD6MFP_I2C0_SDA (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for I2C0_SDA */
\r
804 #define SYS_GPD_MFPL_PD6MFP_SPI1_MOSI (0x05UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SPI1_MOSI */
\r
805 #define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 (0x06UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for USCI1_DAT1 */
\r
806 #define SYS_GPD_MFPL_PD6MFP_SC1_RST (0x08UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SC1_RST */
\r
809 #define SYS_GPD_MFPL_PD7MFP_GPIO (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO */
\r
810 #define SYS_GPD_MFPL_PD7MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for UART1_TXD */
\r
811 #define SYS_GPD_MFPL_PD7MFP_I2C0_SCL (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for I2C0_SCL */
\r
812 #define SYS_GPD_MFPL_PD7MFP_SPI1_MISO (0x05UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SPI1_MISO */
\r
813 #define SYS_GPD_MFPL_PD7MFP_USCI1_CLK (0x06UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for USCI1_CLK */
\r
814 #define SYS_GPD_MFPL_PD7MFP_SC1_PWR (0x08UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SC1_PWR */
\r
817 #define SYS_GPD_MFPH_PD8MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO */
\r
818 #define SYS_GPD_MFPH_PD8MFP_EBI_AD6 (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_AD6 */
\r
819 #define SYS_GPD_MFPH_PD8MFP_I2C2_SDA (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for I2C2_SDA */
\r
820 #define SYS_GPD_MFPH_PD8MFP_UART2_nRTS (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for UART2_nRTS */
\r
823 #define SYS_GPD_MFPH_PD9MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO */
\r
824 #define SYS_GPD_MFPH_PD9MFP_EBI_AD7 (0x02UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EBI_AD7 */
\r
825 #define SYS_GPD_MFPH_PD9MFP_I2C2_SCL (0x03UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for I2C2_SCL */
\r
826 #define SYS_GPD_MFPH_PD9MFP_UART2_nCTS (0x04UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for UART2_nCTS */
\r
829 #define SYS_GPD_MFPH_PD10MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for GPIO */
\r
830 #define SYS_GPD_MFPH_PD10MFP_EBI_nCS2 (0x02UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for EBI_nCS2 */
\r
831 #define SYS_GPD_MFPH_PD10MFP_UART1_RXD (0x03UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for UART1_RXD */
\r
832 #define SYS_GPD_MFPH_PD10MFP_CAN0_RXD (0x04UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for CAN0_RXD */
\r
833 #define SYS_GPD_MFPH_PD10MFP_QEI0_B (0x0aUL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for QEI0_B */
\r
834 #define SYS_GPD_MFPH_PD10MFP_INT7 (0x0fUL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for INT7 */
\r
837 #define SYS_GPD_MFPH_PD11MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for GPIO */
\r
838 #define SYS_GPD_MFPH_PD11MFP_EBI_nCS1 (0x02UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for EBI_nCS1 */
\r
839 #define SYS_GPD_MFPH_PD11MFP_UART1_TXD (0x03UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for UART1_TXD */
\r
840 #define SYS_GPD_MFPH_PD11MFP_CAN0_TXD (0x04UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for CAN0_TXD */
\r
841 #define SYS_GPD_MFPH_PD11MFP_QEI0_A (0x0aUL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for QEI0_A */
\r
842 #define SYS_GPD_MFPH_PD11MFP_INT6 (0x0fUL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for INT6 */
\r
845 #define SYS_GPD_MFPH_PD12MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for GPIO */
\r
846 #define SYS_GPD_MFPH_PD12MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for EBI_nCS0 */
\r
847 #define SYS_GPD_MFPH_PD12MFP_UART2_RXD (0x07UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for UART2_RXD */
\r
848 #define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 (0x09UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for BPWM0_CH5 */
\r
849 #define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX (0x0aUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for QEI0_INDEX */
\r
850 #define SYS_GPD_MFPH_PD12MFP_CLKO (0x0dUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for CLKO */
\r
851 #define SYS_GPD_MFPH_PD12MFP_EADC0_ST (0x0eUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for EADC0_ST */
\r
852 #define SYS_GPD_MFPH_PD12MFP_INT5 (0x0fUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for INT5 */
\r
855 #define SYS_GPD_MFPH_PD13MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for GPIO */
\r
856 #define SYS_GPD_MFPH_PD13MFP_EBI_AD10 (0x02UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for EBI_AD10 */
\r
857 #define SYS_GPD_MFPH_PD13MFP_SD0_nCD (0x03UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for SD0_nCD */
\r
858 #define SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for SPI0_I2SMCLK*/
\r
859 #define SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for SPI1_I2SMCLK*/
\r
860 #define SYS_GPD_MFPH_PD13MFP_SC2_nCD (0x07UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for SC2_nCD */
\r
863 #define SYS_GPD_MFPH_PD14MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for GPIO */
\r
864 #define SYS_GPD_MFPH_PD14MFP_EBI_nCS0 (0x02UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for EBI_nCS0 */
\r
865 #define SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK (0x03UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for SPI3_I2SMCLK*/
\r
866 #define SYS_GPD_MFPH_PD14MFP_SC1_nCD (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for SC1_nCD */
\r
867 #define SYS_GPD_MFPH_PD14MFP_USCI0_CTL0 (0x05UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for USCI0_CTL0 */
\r
868 #define SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK (0x06UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for SPI0_I2SMCLK*/
\r
869 #define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 (0x0bUL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for EPWM0_CH4 */
\r
872 #define SYS_GPE_MFPL_PE0MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO */
\r
873 #define SYS_GPE_MFPL_PE0MFP_EBI_AD11 (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for EBI_AD11 */
\r
874 #define SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0 (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for QSPI0_MOSI0 */
\r
875 #define SYS_GPE_MFPL_PE0MFP_SC2_CLK (0x04UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SC2_CLK */
\r
876 #define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK (0x05UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2S0_MCLK */
\r
877 #define SYS_GPE_MFPL_PE0MFP_SPI1_MOSI (0x06UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SPI1_MOSI */
\r
878 #define SYS_GPE_MFPL_PE0MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for UART3_RXD */
\r
879 #define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2C1_SDA */
\r
880 #define SYS_GPE_MFPL_PE0MFP_UART4_nRTS (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for UART4_nRTS */
\r
883 #define SYS_GPE_MFPL_PE1MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO */
\r
884 #define SYS_GPE_MFPL_PE1MFP_EBI_AD10 (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for EBI_AD10 */
\r
885 #define SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0 (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for QSPI0_MISO0 */
\r
886 #define SYS_GPE_MFPL_PE1MFP_SC2_DAT (0x04UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SC2_DAT */
\r
887 #define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK (0x05UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for I2S0_BCLK */
\r
888 #define SYS_GPE_MFPL_PE1MFP_SPI1_MISO (0x06UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SPI1_MISO */
\r
889 #define SYS_GPE_MFPL_PE1MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART3_TXD */
\r
890 #define SYS_GPE_MFPL_PE1MFP_I2C1_SCL (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for I2C1_SCL */
\r
891 #define SYS_GPE_MFPL_PE1MFP_UART4_nCTS (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART4_nCTS */
\r
894 #define SYS_GPE_MFPL_PE2MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO */
\r
895 #define SYS_GPE_MFPL_PE2MFP_EBI_ALE (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for EBI_ALE */
\r
896 #define SYS_GPE_MFPL_PE2MFP_SD0_DAT0 (0x03UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SD0_DAT0 */
\r
897 #define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SPI3_MOSI */
\r
898 #define SYS_GPE_MFPL_PE2MFP_SC0_CLK (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SC0_CLK */
\r
899 #define SYS_GPE_MFPL_PE2MFP_USCI0_CLK (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for USCI0_CLK */
\r
900 #define SYS_GPE_MFPL_PE2MFP_QEI0_B (0x0bUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for QEI0_B */
\r
901 #define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 (0x0cUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for EPWM0_CH5 */
\r
902 #define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 (0x0dUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for BPWM0_CH0 */
\r
905 #define SYS_GPE_MFPL_PE3MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO */
\r
906 #define SYS_GPE_MFPL_PE3MFP_EBI_MCLK (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for EBI_MCLK */
\r
907 #define SYS_GPE_MFPL_PE3MFP_SD0_DAT1 (0x03UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SD0_DAT1 */
\r
908 #define SYS_GPE_MFPL_PE3MFP_SPI3_MISO (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI3_MISO */
\r
909 #define SYS_GPE_MFPL_PE3MFP_SC0_DAT (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SC0_DAT */
\r
910 #define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for USCI0_DAT0 */
\r
911 #define SYS_GPE_MFPL_PE3MFP_QEI0_A (0x0bUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for QEI0_A */
\r
912 #define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 (0x0cUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for EPWM0_CH4 */
\r
913 #define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 (0x0dUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for BPWM0_CH1 */
\r
916 #define SYS_GPE_MFPL_PE4MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO */
\r
917 #define SYS_GPE_MFPL_PE4MFP_EBI_nWR (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EBI_nWR */
\r
918 #define SYS_GPE_MFPL_PE4MFP_SD0_DAT2 (0x03UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SD0_DAT2 */
\r
919 #define SYS_GPE_MFPL_PE4MFP_SPI3_CLK (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SPI3_CLK */
\r
920 #define SYS_GPE_MFPL_PE4MFP_SC0_RST (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SC0_RST */
\r
921 #define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for USCI0_DAT1 */
\r
922 #define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX (0x0bUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for QEI0_INDEX */
\r
923 #define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 (0x0cUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EPWM0_CH3 */
\r
924 #define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 (0x0dUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for BPWM0_CH2 */
\r
927 #define SYS_GPE_MFPL_PE5MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO */
\r
928 #define SYS_GPE_MFPL_PE5MFP_EBI_nRD (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EBI_nRD */
\r
929 #define SYS_GPE_MFPL_PE5MFP_SD0_DAT3 (0x03UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SD0_DAT3 */
\r
930 #define SYS_GPE_MFPL_PE5MFP_SPI3_SS (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SPI3_SS */
\r
931 #define SYS_GPE_MFPL_PE5MFP_SC0_PWR (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SC0_PWR */
\r
932 #define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for USCI0_CTL1 */
\r
933 #define SYS_GPE_MFPL_PE5MFP_QEI1_B (0x0bUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for QEI1_B */
\r
934 #define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 (0x0cUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EPWM0_CH2 */
\r
935 #define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 (0x0dUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for BPWM0_CH3 */
\r
938 #define SYS_GPE_MFPL_PE6MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO */
\r
939 #define SYS_GPE_MFPL_PE6MFP_SD0_CLK (0x03UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SD0_CLK */
\r
940 #define SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK (0x05UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SPI3_I2SMCLK*/
\r
941 #define SYS_GPE_MFPL_PE6MFP_SC0_nCD (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SC0_nCD */
\r
942 #define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for USCI0_CTL0 */
\r
943 #define SYS_GPE_MFPL_PE6MFP_UART5_RXD (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for UART5_RXD */
\r
944 #define SYS_GPE_MFPL_PE6MFP_QEI1_A (0x0bUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for QEI1_A */
\r
945 #define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 (0x0cUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for EPWM0_CH1 */
\r
946 #define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 (0x0dUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for BPWM0_CH4 */
\r
949 #define SYS_GPE_MFPL_PE7MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO */
\r
950 #define SYS_GPE_MFPL_PE7MFP_SD0_CMD (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for SD0_CMD */
\r
951 #define SYS_GPE_MFPL_PE7MFP_UART5_TXD (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for UART5_TXD */
\r
952 #define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX (0x0bUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for QEI1_INDEX */
\r
953 #define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 (0x0cUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for EPWM0_CH0 */
\r
954 #define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 (0x0dUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for BPWM0_CH5 */
\r
957 #define SYS_GPE_MFPH_PE8MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO */
\r
958 #define SYS_GPE_MFPH_PE8MFP_EBI_ADR10 (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EBI_ADR10 */
\r
959 #define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK (0x04UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for I2S0_BCLK */
\r
960 #define SYS_GPE_MFPH_PE8MFP_SPI2_CLK (0x05UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SPI2_CLK */
\r
961 #define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 (0x06UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for USCI1_CTL1 */
\r
962 #define SYS_GPE_MFPH_PE8MFP_UART2_TXD (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for UART2_TXD */
\r
963 #define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 (0x0aUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_CH0 */
\r
964 #define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 (0x0bUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_BRAKE0*/
\r
965 #define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 (0x0cUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ECAP0_IC0 */
\r
966 #define SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 (0x0eUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for TRACE_DATA3 */
\r
969 #define SYS_GPE_MFPH_PE9MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO */
\r
970 #define SYS_GPE_MFPH_PE9MFP_EBI_ADR11 (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EBI_ADR11 */
\r
971 #define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK (0x04UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for I2S0_MCLK */
\r
972 #define SYS_GPE_MFPH_PE9MFP_SPI2_MISO (0x05UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI2_MISO */
\r
973 #define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 (0x06UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for USCI1_CTL0 */
\r
974 #define SYS_GPE_MFPH_PE9MFP_UART2_RXD (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for UART2_RXD */
\r
975 #define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 (0x0aUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_CH1 */
\r
976 #define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 (0x0bUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_BRAKE1*/
\r
977 #define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 (0x0cUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ECAP0_IC1 */
\r
978 #define SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 (0x0eUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for TRACE_DATA2 */
\r
981 #define SYS_GPE_MFPH_PE10MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for GPIO */
\r
982 #define SYS_GPE_MFPH_PE10MFP_EBI_ADR12 (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for EBI_ADR12 */
\r
983 #define SYS_GPE_MFPH_PE10MFP_I2S0_DI (0x04UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for I2S0_DI */
\r
984 #define SYS_GPE_MFPH_PE10MFP_SPI2_MOSI (0x05UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for SPI2_MOSI */
\r
985 #define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 (0x06UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for USCI1_DAT0 */
\r
986 #define SYS_GPE_MFPH_PE10MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for UART3_TXD */
\r
987 #define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 (0x0aUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for EPWM0_CH2 */
\r
988 #define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 (0x0bUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for EPWM1_BRAKE0*/
\r
989 #define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 (0x0cUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for ECAP0_IC2 */
\r
990 #define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 (0x0eUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for TRACE_DATA1*/
\r
993 #define SYS_GPE_MFPH_PE11MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for GPIO */
\r
994 #define SYS_GPE_MFPH_PE11MFP_EBI_ADR13 (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EBI_ADR13 */
\r
995 #define SYS_GPE_MFPH_PE11MFP_I2S0_DO (0x04UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for I2S0_DO */
\r
996 #define SYS_GPE_MFPH_PE11MFP_SPI2_SS (0x05UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for SPI2_SS */
\r
997 #define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 (0x06UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for USCI1_DAT1 */
\r
998 #define SYS_GPE_MFPH_PE11MFP_UART3_RXD (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for UART3_RXD */
\r
999 #define SYS_GPE_MFPH_PE11MFP_UART1_nCTS (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for UART1_nCTS */
\r
1000 #define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 (0x0aUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EPWM0_CH3 */
\r
1001 #define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 (0x0bUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EPWM1_BRAKE1*/
\r
1002 #define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 (0x0dUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for ECAP1_IC2 */
\r
1003 #define SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 (0x0eUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for TRACE_DATA0*/
\r
1006 #define SYS_GPE_MFPH_PE12MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for GPIO */
\r
1007 #define SYS_GPE_MFPH_PE12MFP_EBI_ADR14 (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for EBI_ADR14 */
\r
1008 #define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK (0x04UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for I2S0_LRCK */
\r
1009 #define SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK (0x05UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for SPI2_I2SMCLK*/
\r
1010 #define SYS_GPE_MFPH_PE12MFP_USCI1_CLK (0x06UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for USCI1_CLK */
\r
1011 #define SYS_GPE_MFPH_PE12MFP_UART1_nRTS (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for UART1_nRTS */
\r
1012 #define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 (0x0aUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for EPWM0_CH4 */
\r
1013 #define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 (0x0dUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for ECAP1_IC1 */
\r
1014 #define SYS_GPE_MFPH_PE12MFP_TRACE_CLK (0x0eUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for TRACE_CLK */
\r
1017 #define SYS_GPE_MFPH_PE13MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for GPIO */
\r
1018 #define SYS_GPE_MFPH_PE13MFP_EBI_ADR15 (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for EBI_ADR15 */
\r
1019 #define SYS_GPE_MFPH_PE13MFP_I2C0_SCL (0x04UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for I2C0_SCL */
\r
1020 #define SYS_GPE_MFPH_PE13MFP_UART4_nRTS (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for UART4_nRTS */
\r
1021 #define SYS_GPE_MFPH_PE13MFP_UART1_TXD (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for UART1_TXD */
\r
1022 #define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 (0x0aUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for EPWM0_CH5 */
\r
1023 #define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 (0x0bUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for EPWM1_CH0 */
\r
1024 #define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 (0x0cUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for BPWM1_CH5 */
\r
1025 #define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 (0x0dUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for ECAP1_IC0 */
\r
1028 #define SYS_GPE_MFPH_PE14MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for GPIO */
\r
1029 #define SYS_GPE_MFPH_PE14MFP_EBI_AD8 (0x02UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for EBI_AD8 */
\r
1030 #define SYS_GPE_MFPH_PE14MFP_UART2_TXD (0x03UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for UART2_TXD */
\r
1031 #define SYS_GPE_MFPH_PE14MFP_CAN0_TXD (0x04UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for CAN0_TXD */
\r
1034 #define SYS_GPE_MFPH_PE15MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for GPIO */
\r
1035 #define SYS_GPE_MFPH_PE15MFP_EBI_AD9 (0x02UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for EBI_AD9 */
\r
1036 #define SYS_GPE_MFPH_PE15MFP_UART2_RXD (0x03UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for UART2_RXD */
\r
1037 #define SYS_GPE_MFPH_PE15MFP_CAN0_RXD (0x04UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for CAN0_RXD */
\r
1040 #define SYS_GPF_MFPL_PF0MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO */
\r
1041 #define SYS_GPF_MFPL_PF0MFP_UART1_TXD (0x02UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for UART1_TXD */
\r
1042 #define SYS_GPF_MFPL_PF0MFP_I2C1_SCL (0x03UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for I2C1_SCL */
\r
1043 #define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 (0x0cUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for BPWM1_CH0 */
\r
1044 #define SYS_GPF_MFPL_PF0MFP_ICE_DAT (0x0eUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for ICE_DAT */
\r
1047 #define SYS_GPF_MFPL_PF1MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO */
\r
1048 #define SYS_GPF_MFPL_PF1MFP_UART1_RXD (0x02UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for UART1_RXD */
\r
1049 #define SYS_GPF_MFPL_PF1MFP_I2C1_SDA (0x03UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for I2C1_SDA */
\r
1050 #define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 (0x0cUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for BPWM1_CH1 */
\r
1051 #define SYS_GPF_MFPL_PF1MFP_ICE_CLK (0x0eUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for ICE_CLK */
\r
1054 #define SYS_GPF_MFPL_PF2MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO */
\r
1055 #define SYS_GPF_MFPL_PF2MFP_EBI_nCS1 (0x02UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for EBI_nCS1 */
\r
1056 #define SYS_GPF_MFPL_PF2MFP_UART0_RXD (0x03UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for UART0_RXD */
\r
1057 #define SYS_GPF_MFPL_PF2MFP_I2C0_SDA (0x04UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for I2C0_SDA */
\r
1058 #define SYS_GPF_MFPL_PF2MFP_QSPI0_CLK (0x05UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for QSPI0_CLK */
\r
1059 #define SYS_GPF_MFPL_PF2MFP_XT1_OUT (0x0aUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for XT1_OUT */
\r
1060 #define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 (0x0bUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for BPWM1_CH1 */
\r
1063 #define SYS_GPF_MFPL_PF3MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO */
\r
1064 #define SYS_GPF_MFPL_PF3MFP_EBI_nCS0 (0x02UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for EBI_nCS0 */
\r
1065 #define SYS_GPF_MFPL_PF3MFP_UART0_TXD (0x03UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for UART0_TXD */
\r
1066 #define SYS_GPF_MFPL_PF3MFP_I2C0_SCL (0x04UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for I2C0_SCL */
\r
1067 #define SYS_GPF_MFPL_PF3MFP_XT1_IN (0x0aUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for XT1_IN */
\r
1068 #define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 (0x0bUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for BPWM1_CH0 */
\r
1071 #define SYS_GPF_MFPL_PF4MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO */
\r
1072 #define SYS_GPF_MFPL_PF4MFP_UART2_TXD (0x02UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for UART2_TXD */
\r
1073 #define SYS_GPF_MFPL_PF4MFP_UART2_nRTS (0x04UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for UART2_nRTS */
\r
1074 #define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 (0x08UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for BPWM0_CH5 */
\r
1075 #define SYS_GPF_MFPL_PF4MFP_X32_OUT (0x0aUL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for X32_OUT */
\r
1078 #define SYS_GPF_MFPL_PF5MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO */
\r
1079 #define SYS_GPF_MFPL_PF5MFP_UART2_RXD (0x02UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for UART2_RXD */
\r
1080 #define SYS_GPF_MFPL_PF5MFP_UART2_nCTS (0x04UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for UART2_nCTS */
\r
1081 #define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 (0x08UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for BPWM0_CH4 */
\r
1082 #define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT (0x09UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for EPWM0_SYNC_OUT*/
\r
1083 #define SYS_GPF_MFPL_PF5MFP_X32_IN (0x0aUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for X32_IN */
\r
1084 #define SYS_GPF_MFPL_PF5MFP_EADC0_ST (0x0bUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for EADC0_ST */
\r
1087 #define SYS_GPF_MFPL_PF6MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO */
\r
1088 #define SYS_GPF_MFPL_PF6MFP_EBI_ADR19 (0x02UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EBI_ADR19 */
\r
1089 #define SYS_GPF_MFPL_PF6MFP_SC0_CLK (0x03UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SC0_CLK */
\r
1090 #define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK (0x04UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for I2S0_LRCK */
\r
1091 #define SYS_GPF_MFPL_PF6MFP_SPI0_MOSI (0x05UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SPI0_MOSI */
\r
1092 #define SYS_GPF_MFPL_PF6MFP_UART4_RXD (0x06UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for UART4_RXD */
\r
1093 #define SYS_GPF_MFPL_PF6MFP_EBI_nCS0 (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EBI_nCS0 */
\r
1094 #define SYS_GPF_MFPL_PF6MFP_TAMPER0 (0x0aUL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for TAMPER0 */
\r
1097 #define SYS_GPF_MFPL_PF7MFP_GPIO (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO */
\r
1098 #define SYS_GPF_MFPL_PF7MFP_EBI_ADR18 (0x02UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for EBI_ADR18 */
\r
1099 #define SYS_GPF_MFPL_PF7MFP_SC0_DAT (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for SC0_DAT */
\r
1100 #define SYS_GPF_MFPL_PF7MFP_I2S0_DO (0x04UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for I2S0_DO */
\r
1101 #define SYS_GPF_MFPL_PF7MFP_SPI0_MISO (0x05UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for SPI0_MISO */
\r
1102 #define SYS_GPF_MFPL_PF7MFP_UART4_TXD (0x06UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for UART4_TXD */
\r
1103 #define SYS_GPF_MFPL_PF7MFP_TAMPER1 (0x0aUL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for TAMPER1 */
\r
1106 #define SYS_GPF_MFPH_PF8MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for GPIO */
\r
1107 #define SYS_GPF_MFPH_PF8MFP_EBI_ADR17 (0x02UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for EBI_ADR17 */
\r
1108 #define SYS_GPF_MFPH_PF8MFP_SC0_RST (0x03UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for SC0_RST */
\r
1109 #define SYS_GPF_MFPH_PF8MFP_I2S0_DI (0x04UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for I2S0_DI */
\r
1110 #define SYS_GPF_MFPH_PF8MFP_SPI0_CLK (0x05UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for SPI0_CLK */
\r
1111 #define SYS_GPF_MFPH_PF8MFP_TAMPER2 (0x0aUL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for TAMPER2 */
\r
1114 #define SYS_GPF_MFPH_PF9MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for GPIO */
\r
1115 #define SYS_GPF_MFPH_PF9MFP_EBI_ADR16 (0x02UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for EBI_ADR16 */
\r
1116 #define SYS_GPF_MFPH_PF9MFP_SC0_PWR (0x03UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for SC0_PWR */
\r
1117 #define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK (0x04UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for I2S0_MCLK */
\r
1118 #define SYS_GPF_MFPH_PF9MFP_SPI0_SS (0x05UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for SPI0_SS */
\r
1119 #define SYS_GPF_MFPH_PF9MFP_TAMPER3 (0x0aUL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for TAMPER3 */
\r
1122 #define SYS_GPF_MFPH_PF10MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for GPIO */
\r
1123 #define SYS_GPF_MFPH_PF10MFP_EBI_ADR15 (0x02UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for EBI_ADR15 */
\r
1124 #define SYS_GPF_MFPH_PF10MFP_SC0_nCD (0x03UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for SC0_nCD */
\r
1125 #define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK (0x04UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for I2S0_BCLK */
\r
1126 #define SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for SPI0_I2SMCLK*/
\r
1127 #define SYS_GPF_MFPH_PF10MFP_TAMPER4 (0x0aUL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for TAMPER4 */
\r
1130 #define SYS_GPF_MFPH_PF11MFP_GPIO (0x00UL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for GPIO */
\r
1131 #define SYS_GPF_MFPH_PF11MFP_EBI_ADR14 (0x02UL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for EBI_ADR14 */
\r
1132 #define SYS_GPF_MFPH_PF11MFP_SPI2_MOSI (0x03UL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for SPI2_MOSI */
\r
1133 #define SYS_GPF_MFPH_PF11MFP_TAMPER5 (0x0aUL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for TAMPER5 */
\r
1134 #define SYS_GPF_MFPH_PF11MFP_TM3 (0x0dUL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for TM3 */
\r
1137 #define SYS_GPG_MFPL_PG2MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for GPIO */
\r
1138 #define SYS_GPG_MFPL_PG2MFP_EBI_ADR11 (0x02UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for EBI_ADR11 */
\r
1139 #define SYS_GPG_MFPL_PG2MFP_SPI2_SS (0x03UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for SPI2_SS */
\r
1140 #define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL (0x04UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for I2C0_SMBAL */
\r
1141 #define SYS_GPG_MFPL_PG2MFP_I2C1_SCL (0x05UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for I2C1_SCL */
\r
1142 #define SYS_GPG_MFPL_PG2MFP_TM0 (0x0dUL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for TM0 */
\r
1145 #define SYS_GPG_MFPL_PG3MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for GPIO */
\r
1146 #define SYS_GPG_MFPL_PG3MFP_EBI_ADR12 (0x02UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for EBI_ADR12 */
\r
1147 #define SYS_GPG_MFPL_PG3MFP_SPI2_CLK (0x03UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for SPI2_CLK */
\r
1148 #define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS (0x04UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2C0_SMBSUS */
\r
1149 #define SYS_GPG_MFPL_PG3MFP_I2C1_SDA (0x05UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2C1_SDA */
\r
1150 #define SYS_GPG_MFPL_PG3MFP_TM1 (0x0dUL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for TM1 */
\r
1153 #define SYS_GPG_MFPL_PG4MFP_GPIO (0x00UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for GPIO */
\r
1154 #define SYS_GPG_MFPL_PG4MFP_EBI_ADR13 (0x02UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for EBI_ADR13 */
\r
1155 #define SYS_GPG_MFPL_PG4MFP_SPI2_MISO (0x03UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for SPI2_MISO */
\r
1156 #define SYS_GPG_MFPL_PG4MFP_TM2 (0x0dUL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for TM2 */
\r
1159 #define SYS_GPG_MFPH_PG9MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for GPIO */
\r
1160 #define SYS_GPG_MFPH_PG9MFP_EBI_AD0 (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for EBI_AD0 */
\r
1161 #define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 (0x0cUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for BPWM0_CH5 */
\r
1164 #define SYS_GPG_MFPH_PG10MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for GPIO */
\r
1165 #define SYS_GPG_MFPH_PG10MFP_EBI_AD1 (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for EBI_AD1 */
\r
1166 #define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 (0x0cUL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for BPWM0_CH4 */
\r
1169 #define SYS_GPG_MFPH_PG11MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for GPIO */
\r
1170 #define SYS_GPG_MFPH_PG11MFP_EBI_AD2 (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for EBI_AD2 */
\r
1171 #define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 (0x0cUL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for BPWM0_CH3 */
\r
1174 #define SYS_GPG_MFPH_PG12MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for GPIO */
\r
1175 #define SYS_GPG_MFPH_PG12MFP_EBI_AD3 (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for EBI_AD3 */
\r
1176 #define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 (0x0cUL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for BPWM0_CH2 */
\r
1179 #define SYS_GPG_MFPH_PG13MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for GPIO */
\r
1180 #define SYS_GPG_MFPH_PG13MFP_EBI_AD4 (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for EBI_AD4 */
\r
1181 #define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 (0x0cUL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for BPWM0_CH1 */
\r
1184 #define SYS_GPG_MFPH_PG14MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for GPIO */
\r
1185 #define SYS_GPG_MFPH_PG14MFP_EBI_AD5 (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for EBI_AD5 */
\r
1186 #define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 (0x0cUL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for BPWM0_CH0 */
\r
1189 #define SYS_GPG_MFPH_PG15MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for GPIO */
\r
1190 #define SYS_GPG_MFPH_PG15MFP_CLKO (0x0eUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for CLKO */
\r
1191 #define SYS_GPG_MFPH_PG15MFP_EADC0_ST (0x0fUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for EADC0_ST */
\r
1194 #define SYS_GPH_MFPL_PH4MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for GPIO */
\r
1195 #define SYS_GPH_MFPL_PH4MFP_EBI_ADR3 (0x02UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for EBI_ADR3 */
\r
1196 #define SYS_GPH_MFPL_PH4MFP_SPI1_MISO (0x03UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for SPI1_MISO */
\r
1199 #define SYS_GPH_MFPL_PH5MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for GPIO */
\r
1200 #define SYS_GPH_MFPL_PH5MFP_EBI_ADR2 (0x02UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for EBI_ADR2 */
\r
1201 #define SYS_GPH_MFPL_PH5MFP_SPI1_MOSI (0x03UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for SPI1_MOSI */
\r
1204 #define SYS_GPH_MFPL_PH6MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for GPIO */
\r
1205 #define SYS_GPH_MFPL_PH6MFP_EBI_ADR1 (0x02UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for EBI_ADR1 */
\r
1206 #define SYS_GPH_MFPL_PH6MFP_SPI1_CLK (0x03UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for SPI1_CLK */
\r
1209 #define SYS_GPH_MFPL_PH7MFP_GPIO (0x00UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for GPIO */
\r
1210 #define SYS_GPH_MFPL_PH7MFP_EBI_ADR0 (0x02UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for EBI_ADR0 */
\r
1211 #define SYS_GPH_MFPL_PH7MFP_SPI1_SS (0x03UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for SPI1_SS */
\r
1214 #define SYS_GPH_MFPH_PH8MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for GPIO */
\r
1215 #define SYS_GPH_MFPH_PH8MFP_EBI_AD12 (0x02UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for EBI_AD12 */
\r
1216 #define SYS_GPH_MFPH_PH8MFP_QSPI0_CLK (0x03UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for QSPI0_CLK */
\r
1217 #define SYS_GPH_MFPH_PH8MFP_SC2_PWR (0x04UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for SC2_PWR */
\r
1218 #define SYS_GPH_MFPH_PH8MFP_I2S0_DI (0x05UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for I2S0_DI */
\r
1219 #define SYS_GPH_MFPH_PH8MFP_SPI1_CLK (0x06UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for SPI1_CLK */
\r
1220 #define SYS_GPH_MFPH_PH8MFP_UART3_nRTS (0x07UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for UART3_nRTS */
\r
1221 #define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL (0x08UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for I2C1_SMBAL */
\r
1222 #define SYS_GPH_MFPH_PH8MFP_I2C2_SCL (0x09UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for I2C2_SCL */
\r
1223 #define SYS_GPH_MFPH_PH8MFP_UART1_TXD (0x0aUL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for UART1_TXD */
\r
1226 #define SYS_GPH_MFPH_PH9MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for GPIO */
\r
1227 #define SYS_GPH_MFPH_PH9MFP_EBI_AD13 (0x02UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for EBI_AD13 */
\r
1228 #define SYS_GPH_MFPH_PH9MFP_QSPI0_SS (0x03UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for QSPI0_SS */
\r
1229 #define SYS_GPH_MFPH_PH9MFP_SC2_RST (0x04UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for SC2_RST */
\r
1230 #define SYS_GPH_MFPH_PH9MFP_I2S0_DO (0x05UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for I2S0_DO */
\r
1231 #define SYS_GPH_MFPH_PH9MFP_SPI1_SS (0x06UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for SPI1_SS */
\r
1232 #define SYS_GPH_MFPH_PH9MFP_UART3_nCTS (0x07UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for UART3_nCTS */
\r
1233 #define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS (0x08UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for I2C1_SMBSUS */
\r
1234 #define SYS_GPH_MFPH_PH9MFP_I2C2_SDA (0x09UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for I2C2_SDA */
\r
1235 #define SYS_GPH_MFPH_PH9MFP_UART1_RXD (0x0aUL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for UART1_RXD */
\r
1238 #define SYS_GPH_MFPH_PH10MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for GPIO */
\r
1239 #define SYS_GPH_MFPH_PH10MFP_EBI_AD14 (0x02UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for EBI_AD14 */
\r
1240 #define SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 (0x03UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for QSPI0_MISO1*/
\r
1241 #define SYS_GPH_MFPH_PH10MFP_SC2_nCD (0x04UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for SC2_nCD */
\r
1242 #define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK (0x05UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for I2S0_LRCK */
\r
1243 #define SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK (0x06UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for SPI1_I2SMCLK*/
\r
1244 #define SYS_GPH_MFPH_PH10MFP_UART4_TXD (0x07UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for UART4_TXD */
\r
1245 #define SYS_GPH_MFPH_PH10MFP_UART0_TXD (0x08UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for UART0_TXD */
\r
1248 #define SYS_GPH_MFPH_PH11MFP_GPIO (0x00UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for GPIO */
\r
1249 #define SYS_GPH_MFPH_PH11MFP_EBI_AD15 (0x02UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for EBI_AD15 */
\r
1250 #define SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for QSPI0_MOSI1*/
\r
1251 #define SYS_GPH_MFPH_PH11MFP_UART4_RXD (0x07UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for UART4_RXD */
\r
1252 #define SYS_GPH_MFPH_PH11MFP_UART0_RXD (0x08UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for UART0_RXD */
\r
1253 #define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 (0x0bUL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for EPWM0_CH5 */
\r
1256 /*---------------------------------------------------------------------------------------------------------*/
\r
1257 /* Multi-Function setting constant definitions abbreviation. */
\r
1258 /*---------------------------------------------------------------------------------------------------------*/
\r
1260 #define ACMP0_N_PB3 SYS_GPB_MFPL_PB3MFP_ACMP0_N /*!< GPB_MFPL PB3 setting for ACMP0_N*/
\r
1261 #define ACMP0_O_PB7 SYS_GPB_MFPL_PB7MFP_ACMP0_O /*!< GPB_MFPL PB7 setting for ACMP0_O*/
\r
1262 #define ACMP0_O_PC1 SYS_GPC_MFPL_PC1MFP_ACMP0_O /*!< GPC_MFPL PC1 setting for ACMP0_O*/
\r
1263 #define ACMP0_O_PC12 SYS_GPC_MFPH_PC12MFP_ACMP0_O /*!< GPC_MFPH PC12 setting for ACMP0_O*/
\r
1264 #define ACMP0_P0_PA11 SYS_GPA_MFPH_PA11MFP_ACMP0_P0 /*!< GPA_MFPH PA11 setting for ACMP0_P0*/
\r
1265 #define ACMP0_P1_PB2 SYS_GPB_MFPL_PB2MFP_ACMP0_P1 /*!< GPB_MFPL PB2 setting for ACMP0_P1*/
\r
1266 #define ACMP0_P2_PB12 SYS_GPB_MFPH_PB12MFP_ACMP0_P2 /*!< GPB_MFPH PB12 setting for ACMP0_P2*/
\r
1267 #define ACMP0_P3_PB13 SYS_GPB_MFPH_PB13MFP_ACMP0_P3 /*!< GPB_MFPH PB13 setting for ACMP0_P3*/
\r
1268 #define ACMP0_WLAT_PA7 SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT /*!< GPA_MFPL PA7 setting for ACMP0_WLAT*/
\r
1269 #define ACMP1_N_PB5 SYS_GPB_MFPL_PB5MFP_ACMP1_N /*!< GPB_MFPL PB5 setting for ACMP1_N*/
\r
1270 #define ACMP1_O_PB6 SYS_GPB_MFPL_PB6MFP_ACMP1_O /*!< GPB_MFPL PB6 setting for ACMP1_O*/
\r
1271 #define ACMP1_O_PC11 SYS_GPC_MFPH_PC11MFP_ACMP1_O /*!< GPC_MFPH PC11 setting for ACMP1_O*/
\r
1272 #define ACMP1_O_PC0 SYS_GPC_MFPL_PC0MFP_ACMP1_O /*!< GPC_MFPL PC0 setting for ACMP1_O*/
\r
1273 #define ACMP1_P0_PA10 SYS_GPA_MFPH_PA10MFP_ACMP1_P0 /*!< GPA_MFPH PA10 setting for ACMP1_P0*/
\r
1274 #define ACMP1_P1_PB4 SYS_GPB_MFPL_PB4MFP_ACMP1_P1 /*!< GPB_MFPL PB4 setting for ACMP1_P1*/
\r
1275 #define ACMP1_P2_PB12 SYS_GPB_MFPH_PB12MFP_ACMP1_P2 /*!< GPB_MFPH PB12 setting for ACMP1_P2*/
\r
1276 #define ACMP1_P3_PB13 SYS_GPB_MFPH_PB13MFP_ACMP1_P3 /*!< GPB_MFPH PB13 setting for ACMP1_P3*/
\r
1277 #define ACMP1_WLAT_PA6 SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT /*!< GPA_MFPL PA6 setting for ACMP1_WLAT*/
\r
1278 #define BPWM0_CH0_PA0 SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 /*!< GPA_MFPL PA0 setting for BPWM0_CH0*/
\r
1279 #define BPWM0_CH0_PA11 SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 /*!< GPA_MFPH PA11 setting for BPWM0_CH0*/
\r
1280 #define BPWM0_CH0_PE2 SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 /*!< GPE_MFPL PE2 setting for BPWM0_CH0*/
\r
1281 #define BPWM0_CH0_PG14 SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 /*!< GPG_MFPH PG14 setting for BPWM0_CH0*/
\r
1282 #define BPWM0_CH1_PA1 SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 /*!< GPA_MFPL PA1 setting for BPWM0_CH1*/
\r
1283 #define BPWM0_CH1_PE3 SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 /*!< GPE_MFPL PE3 setting for BPWM0_CH1*/
\r
1284 #define BPWM0_CH1_PG13 SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 /*!< GPG_MFPH PG13 setting for BPWM0_CH1*/
\r
1285 #define BPWM0_CH1_PA10 SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 /*!< GPA_MFPH PA10 setting for BPWM0_CH1*/
\r
1286 #define BPWM0_CH2_PE4 SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 /*!< GPE_MFPL PE4 setting for BPWM0_CH2*/
\r
1287 #define BPWM0_CH2_PG12 SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 /*!< GPG_MFPH PG12 setting for BPWM0_CH2*/
\r
1288 #define BPWM0_CH2_PA2 SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 /*!< GPA_MFPL PA2 setting for BPWM0_CH2*/
\r
1289 #define BPWM0_CH2_PA9 SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 /*!< GPA_MFPH PA9 setting for BPWM0_CH2*/
\r
1290 #define BPWM0_CH3_PG11 SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 /*!< GPG_MFPH PG11 setting for BPWM0_CH3*/
\r
1291 #define BPWM0_CH3_PA3 SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 /*!< GPA_MFPL PA3 setting for BPWM0_CH3*/
\r
1292 #define BPWM0_CH3_PA8 SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 /*!< GPA_MFPH PA8 setting for BPWM0_CH3*/
\r
1293 #define BPWM0_CH3_PE5 SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 /*!< GPE_MFPL PE5 setting for BPWM0_CH3*/
\r
1294 #define BPWM0_CH4_PG10 SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 /*!< GPG_MFPH PG10 setting for BPWM0_CH4*/
\r
1295 #define BPWM0_CH4_PA4 SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 /*!< GPA_MFPL PA4 setting for BPWM0_CH4*/
\r
1296 #define BPWM0_CH4_PC13 SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 /*!< GPC_MFPH PC13 setting for BPWM0_CH4*/
\r
1297 #define BPWM0_CH4_PE6 SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 /*!< GPE_MFPL PE6 setting for BPWM0_CH4*/
\r
1298 #define BPWM0_CH4_PF5 SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 /*!< GPF_MFPL PF5 setting for BPWM0_CH4*/
\r
1299 #define BPWM0_CH5_PA5 SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 /*!< GPA_MFPL PA5 setting for BPWM0_CH5*/
\r
1300 #define BPWM0_CH5_PE7 SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 /*!< GPE_MFPL PE7 setting for BPWM0_CH5*/
\r
1301 #define BPWM0_CH5_PF4 SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 /*!< GPF_MFPL PF4 setting for BPWM0_CH5*/
\r
1302 #define BPWM0_CH5_PD12 SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 /*!< GPD_MFPH PD12 setting for BPWM0_CH5*/
\r
1303 #define BPWM0_CH5_PG9 SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 /*!< GPG_MFPH PG9 setting for BPWM0_CH5*/
\r
1304 #define BPWM1_CH0_PB11 SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 /*!< GPB_MFPH PB11 setting for BPWM1_CH0*/
\r
1305 #define BPWM1_CH0_PC7 SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 /*!< GPC_MFPL PC7 setting for BPWM1_CH0*/
\r
1306 #define BPWM1_CH0_PF0 SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 /*!< GPF_MFPL PF0 setting for BPWM1_CH0*/
\r
1307 #define BPWM1_CH0_PF3 SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 /*!< GPF_MFPL PF3 setting for BPWM1_CH0*/
\r
1308 #define BPWM1_CH1_PC6 SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 /*!< GPC_MFPL PC6 setting for BPWM1_CH1*/
\r
1309 #define BPWM1_CH1_PF1 SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 /*!< GPF_MFPL PF1 setting for BPWM1_CH1*/
\r
1310 #define BPWM1_CH1_PF2 SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 /*!< GPF_MFPL PF2 setting for BPWM1_CH1*/
\r
1311 #define BPWM1_CH1_PB10 SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 /*!< GPB_MFPH PB10 setting for BPWM1_CH1*/
\r
1312 #define BPWM1_CH2_PB9 SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 /*!< GPB_MFPH PB9 setting for BPWM1_CH2*/
\r
1313 #define BPWM1_CH2_PA7 SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 /*!< GPA_MFPL PA7 setting for BPWM1_CH2*/
\r
1314 #define BPWM1_CH2_PA12 SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 /*!< GPA_MFPH PA12 setting for BPWM1_CH2*/
\r
1315 #define BPWM1_CH3_PA6 SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 /*!< GPA_MFPL PA6 setting for BPWM1_CH3*/
\r
1316 #define BPWM1_CH3_PA13 SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 /*!< GPA_MFPH PA13 setting for BPWM1_CH3*/
\r
1317 #define BPWM1_CH3_PB8 SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 /*!< GPB_MFPH PB8 setting for BPWM1_CH3*/
\r
1318 #define BPWM1_CH4_PA14 SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 /*!< GPA_MFPH PA14 setting for BPWM1_CH4*/
\r
1319 #define BPWM1_CH4_PC8 SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 /*!< GPC_MFPH PC8 setting for BPWM1_CH4*/
\r
1320 #define BPWM1_CH4_PB7 SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 /*!< GPB_MFPL PB7 setting for BPWM1_CH4*/
\r
1321 #define BPWM1_CH5_PA15 SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 /*!< GPA_MFPH PA15 setting for BPWM1_CH5*/
\r
1322 #define BPWM1_CH5_PB6 SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 /*!< GPB_MFPL PB6 setting for BPWM1_CH5*/
\r
1323 #define BPWM1_CH5_PE13 SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 /*!< GPE_MFPH PE13 setting for BPWM1_CH5*/
\r
1324 #define CAN0_RXD_PA13 SYS_GPA_MFPH_PA13MFP_CAN0_RXD /*!< GPA_MFPH PA13 setting for CAN0_RXD*/
\r
1325 #define CAN0_RXD_PD10 SYS_GPD_MFPH_PD10MFP_CAN0_RXD /*!< GPD_MFPH PD10 setting for CAN0_RXD*/
\r
1326 #define CAN0_RXD_PA4 SYS_GPA_MFPL_PA4MFP_CAN0_RXD /*!< GPA_MFPL PA4 setting for CAN0_RXD*/
\r
1327 #define CAN0_RXD_PC4 SYS_GPC_MFPL_PC4MFP_CAN0_RXD /*!< GPC_MFPL PC4 setting for CAN0_RXD*/
\r
1328 #define CAN0_RXD_PB10 SYS_GPB_MFPH_PB10MFP_CAN0_RXD /*!< GPB_MFPH PB10 setting for CAN0_RXD*/
\r
1329 #define CAN0_RXD_PE15 SYS_GPE_MFPH_PE15MFP_CAN0_RXD /*!< GPE_MFPH PE15 setting for CAN0_RXD*/
\r
1330 #define CAN0_TXD_PD11 SYS_GPD_MFPH_PD11MFP_CAN0_TXD /*!< GPD_MFPH PD11 setting for CAN0_TXD*/
\r
1331 #define CAN0_TXD_PC5 SYS_GPC_MFPL_PC5MFP_CAN0_TXD /*!< GPC_MFPL PC5 setting for CAN0_TXD*/
\r
1332 #define CAN0_TXD_PB11 SYS_GPB_MFPH_PB11MFP_CAN0_TXD /*!< GPB_MFPH PB11 setting for CAN0_TXD*/
\r
1333 #define CAN0_TXD_PA12 SYS_GPA_MFPH_PA12MFP_CAN0_TXD /*!< GPA_MFPH PA12 setting for CAN0_TXD*/
\r
1334 #define CAN0_TXD_PE14 SYS_GPE_MFPH_PE14MFP_CAN0_TXD /*!< GPE_MFPH PE14 setting for CAN0_TXD*/
\r
1335 #define CAN0_TXD_PA5 SYS_GPA_MFPL_PA5MFP_CAN0_TXD /*!< GPA_MFPL PA5 setting for CAN0_TXD*/
\r
1336 #define CLKO_PC13 SYS_GPC_MFPH_PC13MFP_CLKO /*!< GPC_MFPH PC13 setting for CLKO*/
\r
1337 #define CLKO_PB14 SYS_GPB_MFPH_PB14MFP_CLKO /*!< GPB_MFPH PB14 setting for CLKO*/
\r
1338 #define CLKO_PD12 SYS_GPD_MFPH_PD12MFP_CLKO /*!< GPD_MFPH PD12 setting for CLKO*/
\r
1339 #define CLKO_PG15 SYS_GPG_MFPH_PG15MFP_CLKO /*!< GPG_MFPH PG15 setting for CLKO*/
\r
1340 #define DAC0_OUT_PB12 SYS_GPB_MFPH_PB12MFP_DAC0_OUT /*!< GPB_MFPH PB12 setting for DAC0_OUT*/
\r
1341 #define DAC0_ST_PA10 SYS_GPA_MFPH_PA10MFP_DAC0_ST /*!< GPA_MFPH PA10 setting for DAC0_ST*/
\r
1342 #define DAC0_ST_PA0 SYS_GPA_MFPL_PA0MFP_DAC0_ST /*!< GPA_MFPL PA0 setting for DAC0_ST*/
\r
1343 #define DAC1_OUT_PB13 SYS_GPB_MFPH_PB13MFP_DAC1_OUT /*!< GPB_MFPH PB13 setting for DAC1_OUT*/
\r
1344 #define DAC1_ST_PA1 SYS_GPA_MFPL_PA1MFP_DAC1_ST /*!< GPA_MFPL PA1 setting for DAC1_ST*/
\r
1345 #define DAC1_ST_PA11 SYS_GPA_MFPH_PA11MFP_DAC1_ST /*!< GPA_MFPH PA11 setting for DAC1_ST*/
\r
1346 #define EADC0_CH0_PB0 SYS_GPB_MFPL_PB0MFP_EADC0_CH0 /*!< GPB_MFPL PB0 setting for EADC0_CH0*/
\r
1347 #define EADC0_CH1_PB1 SYS_GPB_MFPL_PB1MFP_EADC0_CH1 /*!< GPB_MFPL PB1 setting for EADC0_CH1*/
\r
1348 #define EADC0_CH10_PB10 SYS_GPB_MFPH_PB10MFP_EADC0_CH10 /*!< GPB_MFPH PB10 setting for EADC0_CH10*/
\r
1349 #define EADC0_CH11_PB11 SYS_GPB_MFPH_PB11MFP_EADC0_CH11 /*!< GPB_MFPH PB11 setting for EADC0_CH11*/
\r
1350 #define EADC0_CH12_PB12 SYS_GPB_MFPH_PB12MFP_EADC0_CH12 /*!< GPB_MFPH PB12 setting for EADC0_CH12*/
\r
1351 #define EADC0_CH13_PB13 SYS_GPB_MFPH_PB13MFP_EADC0_CH13 /*!< GPB_MFPH PB13 setting for EADC0_CH13*/
\r
1352 #define EADC0_CH14_PB14 SYS_GPB_MFPH_PB14MFP_EADC0_CH14 /*!< GPB_MFPH PB14 setting for EADC0_CH14*/
\r
1353 #define EADC0_CH15_PB15 SYS_GPB_MFPH_PB15MFP_EADC0_CH15 /*!< GPB_MFPH PB15 setting for EADC0_CH15*/
\r
1354 #define EADC0_CH2_PB2 SYS_GPB_MFPL_PB2MFP_EADC0_CH2 /*!< GPB_MFPL PB2 setting for EADC0_CH2*/
\r
1355 #define EADC0_CH3_PB3 SYS_GPB_MFPL_PB3MFP_EADC0_CH3 /*!< GPB_MFPL PB3 setting for EADC0_CH3*/
\r
1356 #define EADC0_CH4_PB4 SYS_GPB_MFPL_PB4MFP_EADC0_CH4 /*!< GPB_MFPL PB4 setting for EADC0_CH4*/
\r
1357 #define EADC0_CH5_PB5 SYS_GPB_MFPL_PB5MFP_EADC0_CH5 /*!< GPB_MFPL PB5 setting for EADC0_CH5*/
\r
1358 #define EADC0_CH6_PB6 SYS_GPB_MFPL_PB6MFP_EADC0_CH6 /*!< GPB_MFPL PB6 setting for EADC0_CH6*/
\r
1359 #define EADC0_CH7_PB7 SYS_GPB_MFPL_PB7MFP_EADC0_CH7 /*!< GPB_MFPL PB7 setting for EADC0_CH7*/
\r
1360 #define EADC0_CH8_PB8 SYS_GPB_MFPH_PB8MFP_EADC0_CH8 /*!< GPB_MFPH PB8 setting for EADC0_CH8*/
\r
1361 #define EADC0_CH9_PB9 SYS_GPB_MFPH_PB9MFP_EADC0_CH9 /*!< GPB_MFPH PB9 setting for EADC0_CH9*/
\r
1362 #define EADC0_ST_PD12 SYS_GPD_MFPH_PD12MFP_EADC0_ST /*!< GPD_MFPH PD12 setting for EADC0_ST*/
\r
1363 #define EADC0_ST_PF5 SYS_GPF_MFPL_PF5MFP_EADC0_ST /*!< GPF_MFPL PF5 setting for EADC0_ST*/
\r
1364 #define EADC0_ST_PC13 SYS_GPC_MFPH_PC13MFP_EADC0_ST /*!< GPC_MFPH PC13 setting for EADC0_ST*/
\r
1365 #define EADC0_ST_PG15 SYS_GPG_MFPH_PG15MFP_EADC0_ST /*!< GPG_MFPH PG15 setting for EADC0_ST*/
\r
1366 #define EBI_AD0_PG9 SYS_GPG_MFPH_PG9MFP_EBI_AD0 /*!< GPG_MFPH PG9 setting for EBI_AD0*/
\r
1367 #define EBI_AD0_PC0 SYS_GPC_MFPL_PC0MFP_EBI_AD0 /*!< GPC_MFPL PC0 setting for EBI_AD0*/
\r
1368 #define EBI_AD1_PC1 SYS_GPC_MFPL_PC1MFP_EBI_AD1 /*!< GPC_MFPL PC1 setting for EBI_AD1*/
\r
1369 #define EBI_AD1_PG10 SYS_GPG_MFPH_PG10MFP_EBI_AD1 /*!< GPG_MFPH PG10 setting for EBI_AD1*/
\r
1370 #define EBI_AD10_PE1 SYS_GPE_MFPL_PE1MFP_EBI_AD10 /*!< GPE_MFPL PE1 setting for EBI_AD10*/
\r
1371 #define EBI_AD10_PD3 SYS_GPD_MFPL_PD3MFP_EBI_AD10 /*!< GPD_MFPL PD3 setting for EBI_AD10*/
\r
1372 #define EBI_AD10_PD13 SYS_GPD_MFPH_PD13MFP_EBI_AD10 /*!< GPD_MFPH PD13 setting for EBI_AD10*/
\r
1373 #define EBI_AD11_PE0 SYS_GPE_MFPL_PE0MFP_EBI_AD11 /*!< GPE_MFPL PE0 setting for EBI_AD11*/
\r
1374 #define EBI_AD11_PD2 SYS_GPD_MFPL_PD2MFP_EBI_AD11 /*!< GPD_MFPL PD2 setting for EBI_AD11*/
\r
1375 #define EBI_AD12_PD1 SYS_GPD_MFPL_PD1MFP_EBI_AD12 /*!< GPD_MFPL PD1 setting for EBI_AD12*/
\r
1376 #define EBI_AD12_PB15 SYS_GPB_MFPH_PB15MFP_EBI_AD12 /*!< GPB_MFPH PB15 setting for EBI_AD12*/
\r
1377 #define EBI_AD12_PH8 SYS_GPH_MFPH_PH8MFP_EBI_AD12 /*!< GPH_MFPH PH8 setting for EBI_AD12*/
\r
1378 #define EBI_AD13_PD0 SYS_GPD_MFPL_PD0MFP_EBI_AD13 /*!< GPD_MFPL PD0 setting for EBI_AD13*/
\r
1379 #define EBI_AD13_PB14 SYS_GPB_MFPH_PB14MFP_EBI_AD13 /*!< GPB_MFPH PB14 setting for EBI_AD13*/
\r
1380 #define EBI_AD13_PH9 SYS_GPH_MFPH_PH9MFP_EBI_AD13 /*!< GPH_MFPH PH9 setting for EBI_AD13*/
\r
1381 #define EBI_AD14_PB13 SYS_GPB_MFPH_PB13MFP_EBI_AD14 /*!< GPB_MFPH PB13 setting for EBI_AD14*/
\r
1382 #define EBI_AD14_PH10 SYS_GPH_MFPH_PH10MFP_EBI_AD14 /*!< GPH_MFPH PH10 setting for EBI_AD14*/
\r
1383 #define EBI_AD15_PB12 SYS_GPB_MFPH_PB12MFP_EBI_AD15 /*!< GPB_MFPH PB12 setting for EBI_AD15*/
\r
1384 #define EBI_AD15_PH11 SYS_GPH_MFPH_PH11MFP_EBI_AD15 /*!< GPH_MFPH PH11 setting for EBI_AD15*/
\r
1385 #define EBI_AD2_PG11 SYS_GPG_MFPH_PG11MFP_EBI_AD2 /*!< GPG_MFPH PG11 setting for EBI_AD2*/
\r
1386 #define EBI_AD2_PC2 SYS_GPC_MFPL_PC2MFP_EBI_AD2 /*!< GPC_MFPL PC2 setting for EBI_AD2*/
\r
1387 #define EBI_AD3_PC3 SYS_GPC_MFPL_PC3MFP_EBI_AD3 /*!< GPC_MFPL PC3 setting for EBI_AD3*/
\r
1388 #define EBI_AD3_PG12 SYS_GPG_MFPH_PG12MFP_EBI_AD3 /*!< GPG_MFPH PG12 setting for EBI_AD3*/
\r
1389 #define EBI_AD4_PG13 SYS_GPG_MFPH_PG13MFP_EBI_AD4 /*!< GPG_MFPH PG13 setting for EBI_AD4*/
\r
1390 #define EBI_AD4_PC4 SYS_GPC_MFPL_PC4MFP_EBI_AD4 /*!< GPC_MFPL PC4 setting for EBI_AD4*/
\r
1391 #define EBI_AD5_PG14 SYS_GPG_MFPH_PG14MFP_EBI_AD5 /*!< GPG_MFPH PG14 setting for EBI_AD5*/
\r
1392 #define EBI_AD5_PC5 SYS_GPC_MFPL_PC5MFP_EBI_AD5 /*!< GPC_MFPL PC5 setting for EBI_AD5*/
\r
1393 #define EBI_AD6_PD8 SYS_GPD_MFPH_PD8MFP_EBI_AD6 /*!< GPD_MFPH PD8 setting for EBI_AD6*/
\r
1394 #define EBI_AD6_PA6 SYS_GPA_MFPL_PA6MFP_EBI_AD6 /*!< GPA_MFPL PA6 setting for EBI_AD6*/
\r
1395 #define EBI_AD7_PA7 SYS_GPA_MFPL_PA7MFP_EBI_AD7 /*!< GPA_MFPL PA7 setting for EBI_AD7*/
\r
1396 #define EBI_AD7_PD9 SYS_GPD_MFPH_PD9MFP_EBI_AD7 /*!< GPD_MFPH PD9 setting for EBI_AD7*/
\r
1397 #define EBI_AD8_PC6 SYS_GPC_MFPL_PC6MFP_EBI_AD8 /*!< GPC_MFPL PC6 setting for EBI_AD8*/
\r
1398 #define EBI_AD8_PE14 SYS_GPE_MFPH_PE14MFP_EBI_AD8 /*!< GPE_MFPH PE14 setting for EBI_AD8*/
\r
1399 #define EBI_AD9_PE15 SYS_GPE_MFPH_PE15MFP_EBI_AD9 /*!< GPE_MFPH PE15 setting for EBI_AD9*/
\r
1400 #define EBI_AD9_PC7 SYS_GPC_MFPL_PC7MFP_EBI_AD9 /*!< GPC_MFPL PC7 setting for EBI_AD9*/
\r
1401 #define EBI_ADR0_PB5 SYS_GPB_MFPL_PB5MFP_EBI_ADR0 /*!< GPB_MFPL PB5 setting for EBI_ADR0*/
\r
1402 #define EBI_ADR0_PH7 SYS_GPH_MFPL_PH7MFP_EBI_ADR0 /*!< GPH_MFPL PH7 setting for EBI_ADR0*/
\r
1403 #define EBI_ADR1_PH6 SYS_GPH_MFPL_PH6MFP_EBI_ADR1 /*!< GPH_MFPL PH6 setting for EBI_ADR1*/
\r
1404 #define EBI_ADR1_PB4 SYS_GPB_MFPL_PB4MFP_EBI_ADR1 /*!< GPB_MFPL PB4 setting for EBI_ADR1*/
\r
1405 #define EBI_ADR10_PE8 SYS_GPE_MFPH_PE8MFP_EBI_ADR10 /*!< GPE_MFPH PE8 setting for EBI_ADR10*/
\r
1406 #define EBI_ADR10_PC13 SYS_GPC_MFPH_PC13MFP_EBI_ADR10 /*!< GPC_MFPH PC13 setting for EBI_ADR10*/
\r
1407 #define EBI_ADR11_PG2 SYS_GPG_MFPL_PG2MFP_EBI_ADR11 /*!< GPG_MFPL PG2 setting for EBI_ADR11*/
\r
1408 #define EBI_ADR11_PE9 SYS_GPE_MFPH_PE9MFP_EBI_ADR11 /*!< GPE_MFPH PE9 setting for EBI_ADR11*/
\r
1409 #define EBI_ADR12_PG3 SYS_GPG_MFPL_PG3MFP_EBI_ADR12 /*!< GPG_MFPL PG3 setting for EBI_ADR12*/
\r
1410 #define EBI_ADR12_PE10 SYS_GPE_MFPH_PE10MFP_EBI_ADR12 /*!< GPE_MFPH PE10 setting for EBI_ADR12*/
\r
1411 #define EBI_ADR13_PG4 SYS_GPG_MFPL_PG4MFP_EBI_ADR13 /*!< GPG_MFPL PG4 setting for EBI_ADR13*/
\r
1412 #define EBI_ADR13_PE11 SYS_GPE_MFPH_PE11MFP_EBI_ADR13 /*!< GPE_MFPH PE11 setting for EBI_ADR13*/
\r
1413 #define EBI_ADR14_PE12 SYS_GPE_MFPH_PE12MFP_EBI_ADR14 /*!< GPE_MFPH PE12 setting for EBI_ADR14*/
\r
1414 #define EBI_ADR14_PF11 SYS_GPF_MFPH_PF11MFP_EBI_ADR14 /*!< GPF_MFPH PF11 setting for EBI_ADR14*/
\r
1415 #define EBI_ADR15_PF10 SYS_GPF_MFPH_PF10MFP_EBI_ADR15 /*!< GPF_MFPH PF10 setting for EBI_ADR15*/
\r
1416 #define EBI_ADR15_PE13 SYS_GPE_MFPH_PE13MFP_EBI_ADR15 /*!< GPE_MFPH PE13 setting for EBI_ADR15*/
\r
1417 #define EBI_ADR16_PB11 SYS_GPB_MFPH_PB11MFP_EBI_ADR16 /*!< GPB_MFPH PB11 setting for EBI_ADR16*/
\r
1418 #define EBI_ADR16_PF9 SYS_GPF_MFPH_PF9MFP_EBI_ADR16 /*!< GPF_MFPH PF9 setting for EBI_ADR16*/
\r
1419 #define EBI_ADR16_PC8 SYS_GPC_MFPH_PC8MFP_EBI_ADR16 /*!< GPC_MFPH PC8 setting for EBI_ADR16*/
\r
1420 #define EBI_ADR17_PF8 SYS_GPF_MFPH_PF8MFP_EBI_ADR17 /*!< GPF_MFPH PF8 setting for EBI_ADR17*/
\r
1421 #define EBI_ADR17_PB10 SYS_GPB_MFPH_PB10MFP_EBI_ADR17 /*!< GPB_MFPH PB10 setting for EBI_ADR17*/
\r
1422 #define EBI_ADR18_PB9 SYS_GPB_MFPH_PB9MFP_EBI_ADR18 /*!< GPB_MFPH PB9 setting for EBI_ADR18*/
\r
1423 #define EBI_ADR18_PF7 SYS_GPF_MFPL_PF7MFP_EBI_ADR18 /*!< GPF_MFPL PF7 setting for EBI_ADR18*/
\r
1424 #define EBI_ADR19_PF6 SYS_GPF_MFPL_PF6MFP_EBI_ADR19 /*!< GPF_MFPL PF6 setting for EBI_ADR19*/
\r
1425 #define EBI_ADR19_PB8 SYS_GPB_MFPH_PB8MFP_EBI_ADR19 /*!< GPB_MFPH PB8 setting for EBI_ADR19*/
\r
1426 #define EBI_ADR2_PB3 SYS_GPB_MFPL_PB3MFP_EBI_ADR2 /*!< GPB_MFPL PB3 setting for EBI_ADR2*/
\r
1427 #define EBI_ADR2_PH5 SYS_GPH_MFPL_PH5MFP_EBI_ADR2 /*!< GPH_MFPL PH5 setting for EBI_ADR2*/
\r
1428 #define EBI_ADR3_PH4 SYS_GPH_MFPL_PH4MFP_EBI_ADR3 /*!< GPH_MFPL PH4 setting for EBI_ADR3*/
\r
1429 #define EBI_ADR3_PB2 SYS_GPB_MFPL_PB2MFP_EBI_ADR3 /*!< GPB_MFPL PB2 setting for EBI_ADR3*/
\r
1430 #define EBI_ADR4_PC12 SYS_GPC_MFPH_PC12MFP_EBI_ADR4 /*!< GPC_MFPH PC12 setting for EBI_ADR4*/
\r
1431 #define EBI_ADR5_PC11 SYS_GPC_MFPH_PC11MFP_EBI_ADR5 /*!< GPC_MFPH PC11 setting for EBI_ADR5*/
\r
1432 #define EBI_ADR6_PC10 SYS_GPC_MFPH_PC10MFP_EBI_ADR6 /*!< GPC_MFPH PC10 setting for EBI_ADR6*/
\r
1433 #define EBI_ADR7_PC9 SYS_GPC_MFPH_PC9MFP_EBI_ADR7 /*!< GPC_MFPH PC9 setting for EBI_ADR7*/
\r
1434 #define EBI_ADR8_PB1 SYS_GPB_MFPL_PB1MFP_EBI_ADR8 /*!< GPB_MFPL PB1 setting for EBI_ADR8*/
\r
1435 #define EBI_ADR9_PB0 SYS_GPB_MFPL_PB0MFP_EBI_ADR9 /*!< GPB_MFPL PB0 setting for EBI_ADR9*/
\r
1436 #define EBI_ALE_PA8 SYS_GPA_MFPH_PA8MFP_EBI_ALE /*!< GPA_MFPH PA8 setting for EBI_ALE*/
\r
1437 #define EBI_ALE_PE2 SYS_GPE_MFPL_PE2MFP_EBI_ALE /*!< GPE_MFPL PE2 setting for EBI_ALE*/
\r
1438 #define EBI_MCLK_PE3 SYS_GPE_MFPL_PE3MFP_EBI_MCLK /*!< GPE_MFPL PE3 setting for EBI_MCLK*/
\r
1439 #define EBI_MCLK_PA9 SYS_GPA_MFPH_PA9MFP_EBI_MCLK /*!< GPA_MFPH PA9 setting for EBI_MCLK*/
\r
1440 #define EBI_nCS0_PB7 SYS_GPB_MFPL_PB7MFP_EBI_nCS0 /*!< GPB_MFPL PB7 setting for EBI_nCS0*/
\r
1441 #define EBI_nCS0_PF6 SYS_GPF_MFPL_PF6MFP_EBI_nCS0 /*!< GPF_MFPL PF6 setting for EBI_nCS0*/
\r
1442 #define EBI_nCS0_PD12 SYS_GPD_MFPH_PD12MFP_EBI_nCS0 /*!< GPD_MFPH PD12 setting for EBI_nCS0*/
\r
1443 #define EBI_nCS0_PD14 SYS_GPD_MFPH_PD14MFP_EBI_nCS0 /*!< GPD_MFPH PD14 setting for EBI_nCS0*/
\r
1444 #define EBI_nCS0_PF3 SYS_GPF_MFPL_PF3MFP_EBI_nCS0 /*!< GPF_MFPL PF3 setting for EBI_nCS0*/
\r
1445 #define EBI_nCS1_PF2 SYS_GPF_MFPL_PF2MFP_EBI_nCS1 /*!< GPF_MFPL PF2 setting for EBI_nCS1*/
\r
1446 #define EBI_nCS1_PD11 SYS_GPD_MFPH_PD11MFP_EBI_nCS1 /*!< GPD_MFPH PD11 setting for EBI_nCS1*/
\r
1447 #define EBI_nCS1_PB6 SYS_GPB_MFPL_PB6MFP_EBI_nCS1 /*!< GPB_MFPL PB6 setting for EBI_nCS1*/
\r
1448 #define EBI_nCS2_PD10 SYS_GPD_MFPH_PD10MFP_EBI_nCS2 /*!< GPD_MFPH PD10 setting for EBI_nCS2*/
\r
1449 #define EBI_nRD_PA11 SYS_GPA_MFPH_PA11MFP_EBI_nRD /*!< GPA_MFPH PA11 setting for EBI_nRD*/
\r
1450 #define EBI_nRD_PE5 SYS_GPE_MFPL_PE5MFP_EBI_nRD /*!< GPE_MFPL PE5 setting for EBI_nRD*/
\r
1451 #define EBI_nWR_PA10 SYS_GPA_MFPH_PA10MFP_EBI_nWR /*!< GPA_MFPH PA10 setting for EBI_nWR*/
\r
1452 #define EBI_nWR_PE4 SYS_GPE_MFPL_PE4MFP_EBI_nWR /*!< GPE_MFPL PE4 setting for EBI_nWR*/
\r
1453 #define EBI_nWRH_PB6 SYS_GPB_MFPL_PB6MFP_EBI_nWRH /*!< GPB_MFPL PB6 setting for EBI_nWRH*/
\r
1454 #define EBI_nWRL_PB7 SYS_GPB_MFPL_PB7MFP_EBI_nWRL /*!< GPB_MFPL PB7 setting for EBI_nWRL*/
\r
1455 #define ECAP0_IC0_PA10 SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 /*!< GPA_MFPH PA10 setting for ECAP0_IC0*/
\r
1456 #define ECAP0_IC0_PE8 SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 /*!< GPE_MFPH PE8 setting for ECAP0_IC0*/
\r
1457 #define ECAP0_IC1_PE9 SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 /*!< GPE_MFPH PE9 setting for ECAP0_IC1*/
\r
1458 #define ECAP0_IC1_PA9 SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 /*!< GPA_MFPH PA9 setting for ECAP0_IC1*/
\r
1459 #define ECAP0_IC2_PA8 SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 /*!< GPA_MFPH PA8 setting for ECAP0_IC2*/
\r
1460 #define ECAP0_IC2_PE10 SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 /*!< GPE_MFPH PE10 setting for ECAP0_IC2*/
\r
1461 #define ECAP1_IC0_PC10 SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 /*!< GPC_MFPH PC10 setting for ECAP1_IC0*/
\r
1462 #define ECAP1_IC0_PE13 SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 /*!< GPE_MFPH PE13 setting for ECAP1_IC0*/
\r
1463 #define ECAP1_IC1_PE12 SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 /*!< GPE_MFPH PE12 setting for ECAP1_IC1*/
\r
1464 #define ECAP1_IC1_PC11 SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 /*!< GPC_MFPH PC11 setting for ECAP1_IC1*/
\r
1465 #define ECAP1_IC2_PE11 SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 /*!< GPE_MFPH PE11 setting for ECAP1_IC2*/
\r
1466 #define ECAP1_IC2_PC12 SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 /*!< GPC_MFPH PC12 setting for ECAP1_IC2*/
\r
1467 #define I2C0_SCL_PB5 SYS_GPB_MFPL_PB5MFP_I2C0_SCL /*!< GPB_MFPL PB5 setting for I2C0_SCL*/
\r
1468 #define I2C0_SCL_PC1 SYS_GPC_MFPL_PC1MFP_I2C0_SCL /*!< GPC_MFPL PC1 setting for I2C0_SCL*/
\r
1469 #define I2C0_SCL_PF3 SYS_GPF_MFPL_PF3MFP_I2C0_SCL /*!< GPF_MFPL PF3 setting for I2C0_SCL*/
\r
1470 #define I2C0_SCL_PE13 SYS_GPE_MFPH_PE13MFP_I2C0_SCL /*!< GPE_MFPH PE13 setting for I2C0_SCL*/
\r
1471 #define I2C0_SCL_PD7 SYS_GPD_MFPL_PD7MFP_I2C0_SCL /*!< GPD_MFPL PD7 setting for I2C0_SCL*/
\r
1472 #define I2C0_SCL_PA5 SYS_GPA_MFPL_PA5MFP_I2C0_SCL /*!< GPA_MFPL PA5 setting for I2C0_SCL*/
\r
1473 #define I2C0_SCL_PC12 SYS_GPC_MFPH_PC12MFP_I2C0_SCL /*!< GPC_MFPH PC12 setting for I2C0_SCL*/
\r
1474 #define I2C0_SDA_PB4 SYS_GPB_MFPL_PB4MFP_I2C0_SDA /*!< GPB_MFPL PB4 setting for I2C0_SDA*/
\r
1475 #define I2C0_SDA_PC8 SYS_GPC_MFPH_PC8MFP_I2C0_SDA /*!< GPC_MFPH PC8 setting for I2C0_SDA*/
\r
1476 #define I2C0_SDA_PC0 SYS_GPC_MFPL_PC0MFP_I2C0_SDA /*!< GPC_MFPL PC0 setting for I2C0_SDA*/
\r
1477 #define I2C0_SDA_PD6 SYS_GPD_MFPL_PD6MFP_I2C0_SDA /*!< GPD_MFPL PD6 setting for I2C0_SDA*/
\r
1478 #define I2C0_SDA_PC11 SYS_GPC_MFPH_PC11MFP_I2C0_SDA /*!< GPC_MFPH PC11 setting for I2C0_SDA*/
\r
1479 #define I2C0_SDA_PA4 SYS_GPA_MFPL_PA4MFP_I2C0_SDA /*!< GPA_MFPL PA4 setting for I2C0_SDA*/
\r
1480 #define I2C0_SDA_PF2 SYS_GPF_MFPL_PF2MFP_I2C0_SDA /*!< GPF_MFPL PF2 setting for I2C0_SDA*/
\r
1481 #define I2C0_SMBAL_PG2 SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL /*!< GPG_MFPL PG2 setting for I2C0_SMBAL*/
\r
1482 #define I2C0_SMBAL_PC3 SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL /*!< GPC_MFPL PC3 setting for I2C0_SMBAL*/
\r
1483 #define I2C0_SMBSUS_PC2 SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS /*!< GPC_MFPL PC2 setting for I2C0_SMBSUS*/
\r
1484 #define I2C0_SMBSUS_PG3 SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS /*!< GPG_MFPL PG3 setting for I2C0_SMBSUS*/
\r
1485 #define I2C1_SCL_PA3 SYS_GPA_MFPL_PA3MFP_I2C1_SCL /*!< GPA_MFPL PA3 setting for I2C1_SCL*/
\r
1486 #define I2C1_SCL_PG2 SYS_GPG_MFPL_PG2MFP_I2C1_SCL /*!< GPG_MFPL PG2 setting for I2C1_SCL*/
\r
1487 #define I2C1_SCL_PB1 SYS_GPB_MFPL_PB1MFP_I2C1_SCL /*!< GPB_MFPL PB1 setting for I2C1_SCL*/
\r
1488 #define I2C1_SCL_PB11 SYS_GPB_MFPH_PB11MFP_I2C1_SCL /*!< GPB_MFPH PB11 setting for I2C1_SCL*/
\r
1489 #define I2C1_SCL_PD5 SYS_GPD_MFPL_PD5MFP_I2C1_SCL /*!< GPD_MFPL PD5 setting for I2C1_SCL*/
\r
1490 #define I2C1_SCL_PA12 SYS_GPA_MFPH_PA12MFP_I2C1_SCL /*!< GPA_MFPH PA12 setting for I2C1_SCL*/
\r
1491 #define I2C1_SCL_PC5 SYS_GPC_MFPL_PC5MFP_I2C1_SCL /*!< GPC_MFPL PC5 setting for I2C1_SCL*/
\r
1492 #define I2C1_SCL_PA7 SYS_GPA_MFPL_PA7MFP_I2C1_SCL /*!< GPA_MFPL PA7 setting for I2C1_SCL*/
\r
1493 #define I2C1_SCL_PF0 SYS_GPF_MFPL_PF0MFP_I2C1_SCL /*!< GPF_MFPL PF0 setting for I2C1_SCL*/
\r
1494 #define I2C1_SCL_PE1 SYS_GPE_MFPL_PE1MFP_I2C1_SCL /*!< GPE_MFPL PE1 setting for I2C1_SCL*/
\r
1495 #define I2C1_SDA_PB0 SYS_GPB_MFPL_PB0MFP_I2C1_SDA /*!< GPB_MFPL PB0 setting for I2C1_SDA*/
\r
1496 #define I2C1_SDA_PA6 SYS_GPA_MFPL_PA6MFP_I2C1_SDA /*!< GPA_MFPL PA6 setting for I2C1_SDA*/
\r
1497 #define I2C1_SDA_PA13 SYS_GPA_MFPH_PA13MFP_I2C1_SDA /*!< GPA_MFPH PA13 setting for I2C1_SDA*/
\r
1498 #define I2C1_SDA_PG3 SYS_GPG_MFPL_PG3MFP_I2C1_SDA /*!< GPG_MFPL PG3 setting for I2C1_SDA*/
\r
1499 #define I2C1_SDA_PE0 SYS_GPE_MFPL_PE0MFP_I2C1_SDA /*!< GPE_MFPL PE0 setting for I2C1_SDA*/
\r
1500 #define I2C1_SDA_PC4 SYS_GPC_MFPL_PC4MFP_I2C1_SDA /*!< GPC_MFPL PC4 setting for I2C1_SDA*/
\r
1501 #define I2C1_SDA_PA2 SYS_GPA_MFPL_PA2MFP_I2C1_SDA /*!< GPA_MFPL PA2 setting for I2C1_SDA*/
\r
1502 #define I2C1_SDA_PB10 SYS_GPB_MFPH_PB10MFP_I2C1_SDA /*!< GPB_MFPH PB10 setting for I2C1_SDA*/
\r
1503 #define I2C1_SDA_PF1 SYS_GPF_MFPL_PF1MFP_I2C1_SDA /*!< GPF_MFPL PF1 setting for I2C1_SDA*/
\r
1504 #define I2C1_SDA_PD4 SYS_GPD_MFPL_PD4MFP_I2C1_SDA /*!< GPD_MFPL PD4 setting for I2C1_SDA*/
\r
1505 #define I2C1_SMBAL_PB9 SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL /*!< GPB_MFPH PB9 setting for I2C1_SMBAL*/
\r
1506 #define I2C1_SMBAL_PC7 SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL /*!< GPC_MFPL PC7 setting for I2C1_SMBAL*/
\r
1507 #define I2C1_SMBAL_PH8 SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL /*!< GPH_MFPH PH8 setting for I2C1_SMBAL*/
\r
1508 #define I2C1_SMBSUS_PH9 SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS /*!< GPH_MFPH PH9 setting for I2C1_SMBSUS*/
\r
1509 #define I2C1_SMBSUS_PC6 SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS /*!< GPC_MFPL PC6 setting for I2C1_SMBSUS*/
\r
1510 #define I2C1_SMBSUS_PB8 SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS /*!< GPB_MFPH PB8 setting for I2C1_SMBSUS*/
\r
1511 #define I2C2_SCL_PB13 SYS_GPB_MFPH_PB13MFP_I2C2_SCL /*!< GPB_MFPH PB13 setting for I2C2_SCL*/
\r
1512 #define I2C2_SCL_PA11 SYS_GPA_MFPH_PA11MFP_I2C2_SCL /*!< GPA_MFPH PA11 setting for I2C2_SCL*/
\r
1513 #define I2C2_SCL_PH8 SYS_GPH_MFPH_PH8MFP_I2C2_SCL /*!< GPH_MFPH PH8 setting for I2C2_SCL*/
\r
1514 #define I2C2_SCL_PD9 SYS_GPD_MFPH_PD9MFP_I2C2_SCL /*!< GPD_MFPH PD9 setting for I2C2_SCL*/
\r
1515 #define I2C2_SCL_PD1 SYS_GPD_MFPL_PD1MFP_I2C2_SCL /*!< GPD_MFPL PD1 setting for I2C2_SCL*/
\r
1516 #define I2C2_SCL_PA14 SYS_GPA_MFPH_PA14MFP_I2C2_SCL /*!< GPA_MFPH PA14 setting for I2C2_SCL*/
\r
1517 #define I2C2_SCL_PA1 SYS_GPA_MFPL_PA1MFP_I2C2_SCL /*!< GPA_MFPL PA1 setting for I2C2_SCL*/
\r
1518 #define I2C2_SDA_PA0 SYS_GPA_MFPL_PA0MFP_I2C2_SDA /*!< GPA_MFPL PA0 setting for I2C2_SDA*/
\r
1519 #define I2C2_SDA_PB12 SYS_GPB_MFPH_PB12MFP_I2C2_SDA /*!< GPB_MFPH PB12 setting for I2C2_SDA*/
\r
1520 #define I2C2_SDA_PA10 SYS_GPA_MFPH_PA10MFP_I2C2_SDA /*!< GPA_MFPH PA10 setting for I2C2_SDA*/
\r
1521 #define I2C2_SDA_PA15 SYS_GPA_MFPH_PA15MFP_I2C2_SDA /*!< GPA_MFPH PA15 setting for I2C2_SDA*/
\r
1522 #define I2C2_SDA_PH9 SYS_GPH_MFPH_PH9MFP_I2C2_SDA /*!< GPH_MFPH PH9 setting for I2C2_SDA*/
\r
1523 #define I2C2_SDA_PD8 SYS_GPD_MFPH_PD8MFP_I2C2_SDA /*!< GPD_MFPH PD8 setting for I2C2_SDA*/
\r
1524 #define I2C2_SDA_PD0 SYS_GPD_MFPL_PD0MFP_I2C2_SDA /*!< GPD_MFPL PD0 setting for I2C2_SDA*/
\r
1525 #define I2C2_SMBAL_PB15 SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL /*!< GPB_MFPH PB15 setting for I2C2_SMBAL*/
\r
1526 #define I2C2_SMBSUS_PB14 SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS /*!< GPB_MFPH PB14 setting for I2C2_SMBSUS*/
\r
1527 #define I2S0_BCLK_PA12 SYS_GPA_MFPH_PA12MFP_I2S0_BCLK /*!< GPA_MFPH PA12 setting for I2S0_BCLK*/
\r
1528 #define I2S0_BCLK_PB5 SYS_GPB_MFPL_PB5MFP_I2S0_BCLK /*!< GPB_MFPL PB5 setting for I2S0_BCLK*/
\r
1529 #define I2S0_BCLK_PE8 SYS_GPE_MFPH_PE8MFP_I2S0_BCLK /*!< GPE_MFPH PE8 setting for I2S0_BCLK*/
\r
1530 #define I2S0_BCLK_PE1 SYS_GPE_MFPL_PE1MFP_I2S0_BCLK /*!< GPE_MFPL PE1 setting for I2S0_BCLK*/
\r
1531 #define I2S0_BCLK_PF10 SYS_GPF_MFPH_PF10MFP_I2S0_BCLK /*!< GPF_MFPH PF10 setting for I2S0_BCLK*/
\r
1532 #define I2S0_BCLK_PC4 SYS_GPC_MFPL_PC4MFP_I2S0_BCLK /*!< GPC_MFPL PC4 setting for I2S0_BCLK*/
\r
1533 #define I2S0_DI_PF8 SYS_GPF_MFPH_PF8MFP_I2S0_DI /*!< GPF_MFPH PF8 setting for I2S0_DI*/
\r
1534 #define I2S0_DI_PB3 SYS_GPB_MFPL_PB3MFP_I2S0_DI /*!< GPB_MFPL PB3 setting for I2S0_DI*/
\r
1535 #define I2S0_DI_PE10 SYS_GPE_MFPH_PE10MFP_I2S0_DI /*!< GPE_MFPH PE10 setting for I2S0_DI*/
\r
1536 #define I2S0_DI_PA14 SYS_GPA_MFPH_PA14MFP_I2S0_DI /*!< GPA_MFPH PA14 setting for I2S0_DI*/
\r
1537 #define I2S0_DI_PH8 SYS_GPH_MFPH_PH8MFP_I2S0_DI /*!< GPH_MFPH PH8 setting for I2S0_DI*/
\r
1538 #define I2S0_DI_PC2 SYS_GPC_MFPL_PC2MFP_I2S0_DI /*!< GPC_MFPL PC2 setting for I2S0_DI*/
\r
1539 #define I2S0_DO_PB2 SYS_GPB_MFPL_PB2MFP_I2S0_DO /*!< GPB_MFPL PB2 setting for I2S0_DO*/
\r
1540 #define I2S0_DO_PH9 SYS_GPH_MFPH_PH9MFP_I2S0_DO /*!< GPH_MFPH PH9 setting for I2S0_DO*/
\r
1541 #define I2S0_DO_PF7 SYS_GPF_MFPL_PF7MFP_I2S0_DO /*!< GPF_MFPL PF7 setting for I2S0_DO*/
\r
1542 #define I2S0_DO_PE11 SYS_GPE_MFPH_PE11MFP_I2S0_DO /*!< GPE_MFPH PE11 setting for I2S0_DO*/
\r
1543 #define I2S0_DO_PC1 SYS_GPC_MFPL_PC1MFP_I2S0_DO /*!< GPC_MFPL PC1 setting for I2S0_DO*/
\r
1544 #define I2S0_DO_PA15 SYS_GPA_MFPH_PA15MFP_I2S0_DO /*!< GPA_MFPH PA15 setting for I2S0_DO*/
\r
1545 #define I2S0_LRCK_PF6 SYS_GPF_MFPL_PF6MFP_I2S0_LRCK /*!< GPF_MFPL PF6 setting for I2S0_LRCK*/
\r
1546 #define I2S0_LRCK_PE12 SYS_GPE_MFPH_PE12MFP_I2S0_LRCK /*!< GPE_MFPH PE12 setting for I2S0_LRCK*/
\r
1547 #define I2S0_LRCK_PC0 SYS_GPC_MFPL_PC0MFP_I2S0_LRCK /*!< GPC_MFPL PC0 setting for I2S0_LRCK*/
\r
1548 #define I2S0_LRCK_PH10 SYS_GPH_MFPH_PH10MFP_I2S0_LRCK /*!< GPH_MFPH PH10 setting for I2S0_LRCK*/
\r
1549 #define I2S0_LRCK_PB1 SYS_GPB_MFPL_PB1MFP_I2S0_LRCK /*!< GPB_MFPL PB1 setting for I2S0_LRCK*/
\r
1550 #define I2S0_MCLK_PE9 SYS_GPE_MFPH_PE9MFP_I2S0_MCLK /*!< GPE_MFPH PE9 setting for I2S0_MCLK*/
\r
1551 #define I2S0_MCLK_PB4 SYS_GPB_MFPL_PB4MFP_I2S0_MCLK /*!< GPB_MFPL PB4 setting for I2S0_MCLK*/
\r
1552 #define I2S0_MCLK_PC3 SYS_GPC_MFPL_PC3MFP_I2S0_MCLK /*!< GPC_MFPL PC3 setting for I2S0_MCLK*/
\r
1553 #define I2S0_MCLK_PE0 SYS_GPE_MFPL_PE0MFP_I2S0_MCLK /*!< GPE_MFPL PE0 setting for I2S0_MCLK*/
\r
1554 #define I2S0_MCLK_PA13 SYS_GPA_MFPH_PA13MFP_I2S0_MCLK /*!< GPA_MFPH PA13 setting for I2S0_MCLK*/
\r
1555 #define I2S0_MCLK_PF9 SYS_GPF_MFPH_PF9MFP_I2S0_MCLK /*!< GPF_MFPH PF9 setting for I2S0_MCLK*/
\r
1556 #define ICE_CLK_PF1 SYS_GPF_MFPL_PF1MFP_ICE_CLK /*!< GPF_MFPL PF1 setting for ICE_CLK*/
\r
1557 #define ICE_DAT_PF0 SYS_GPF_MFPL_PF0MFP_ICE_DAT /*!< GPF_MFPL PF0 setting for ICE_DAT*/
\r
1558 #define INT0_PB5 SYS_GPB_MFPL_PB5MFP_INT0 /*!< GPB_MFPL PB5 setting for INT0*/
\r
1559 #define INT0_PA6 SYS_GPA_MFPL_PA6MFP_INT0 /*!< GPA_MFPL PA6 setting for INT0*/
\r
1560 #define INT1_PB4 SYS_GPB_MFPL_PB4MFP_INT1 /*!< GPB_MFPL PB4 setting for INT1*/
\r
1561 #define INT1_PA7 SYS_GPA_MFPL_PA7MFP_INT1 /*!< GPA_MFPL PA7 setting for INT1*/
\r
1562 #define INT2_PB3 SYS_GPB_MFPL_PB3MFP_INT2 /*!< GPB_MFPL PB3 setting for INT2*/
\r
1563 #define INT2_PC6 SYS_GPC_MFPL_PC6MFP_INT2 /*!< GPC_MFPL PC6 setting for INT2*/
\r
1564 #define INT3_PC7 SYS_GPC_MFPL_PC7MFP_INT3 /*!< GPC_MFPL PC7 setting for INT3*/
\r
1565 #define INT3_PB2 SYS_GPB_MFPL_PB2MFP_INT3 /*!< GPB_MFPL PB2 setting for INT3*/
\r
1566 #define INT4_PB6 SYS_GPB_MFPL_PB6MFP_INT4 /*!< GPB_MFPL PB6 setting for INT4*/
\r
1567 #define INT4_PA8 SYS_GPA_MFPH_PA8MFP_INT4 /*!< GPA_MFPH PA8 setting for INT4*/
\r
1568 #define INT5_PB7 SYS_GPB_MFPL_PB7MFP_INT5 /*!< GPB_MFPL PB7 setting for INT5*/
\r
1569 #define INT5_PD12 SYS_GPD_MFPH_PD12MFP_INT5 /*!< GPD_MFPH PD12 setting for INT5*/
\r
1570 #define INT6_PD11 SYS_GPD_MFPH_PD11MFP_INT6 /*!< GPD_MFPH PD11 setting for INT6*/
\r
1571 #define INT6_PB8 SYS_GPB_MFPH_PB8MFP_INT6 /*!< GPB_MFPH PB8 setting for INT6*/
\r
1572 #define INT7_PB9 SYS_GPB_MFPH_PB9MFP_INT7 /*!< GPB_MFPH PB9 setting for INT7*/
\r
1573 #define INT7_PD10 SYS_GPD_MFPH_PD10MFP_INT7 /*!< GPD_MFPH PD10 setting for INT7*/
\r
1574 #define EPWM0_BRAKE0_PE8 SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 /*!< GPE_MFPH PE8 setting for EPWM0_BRAKE0*/
\r
1575 #define EPWM0_BRAKE0_PB1 SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 /*!< GPB_MFPL PB1 setting for EPWM0_BRAKE0*/
\r
1576 #define EPWM0_BRAKE1_PB0 SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 /*!< GPB_MFPL PB0 setting for EPWM0_BRAKE1*/
\r
1577 #define EPWM0_BRAKE1_PE9 SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 /*!< GPE_MFPH PE9 setting for EPWM0_BRAKE1*/
\r
1578 #define EPWM0_CH0_PA5 SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 /*!< GPA_MFPL PA5 setting for EPWM0_CH0*/
\r
1579 #define EPWM0_CH0_PE7 SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 /*!< GPE_MFPL PE7 setting for EPWM0_CH0*/
\r
1580 #define EPWM0_CH0_PE8 SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 /*!< GPE_MFPH PE8 setting for EPWM0_CH0*/
\r
1581 #define EPWM0_CH0_PB5 SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 /*!< GPB_MFPL PB5 setting for EPWM0_CH0*/
\r
1582 #define EPWM0_CH1_PA4 SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 /*!< GPA_MFPL PA4 setting for EPWM0_CH1*/
\r
1583 #define EPWM0_CH1_PB4 SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 /*!< GPB_MFPL PB4 setting for EPWM0_CH1*/
\r
1584 #define EPWM0_CH1_PE9 SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 /*!< GPE_MFPH PE9 setting for EPWM0_CH1*/
\r
1585 #define EPWM0_CH1_PE6 SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 /*!< GPE_MFPL PE6 setting for EPWM0_CH1*/
\r
1586 #define EPWM0_CH2_PE5 SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 /*!< GPE_MFPL PE5 setting for EPWM0_CH2*/
\r
1587 #define EPWM0_CH2_PB3 SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 /*!< GPB_MFPL PB3 setting for EPWM0_CH2*/
\r
1588 #define EPWM0_CH2_PE10 SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 /*!< GPE_MFPH PE10 setting for EPWM0_CH2*/
\r
1589 #define EPWM0_CH2_PA3 SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 /*!< GPA_MFPL PA3 setting for EPWM0_CH2*/
\r
1590 #define EPWM0_CH3_PA2 SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 /*!< GPA_MFPL PA2 setting for EPWM0_CH3*/
\r
1591 #define EPWM0_CH3_PE11 SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 /*!< GPE_MFPH PE11 setting for EPWM0_CH3*/
\r
1592 #define EPWM0_CH3_PE4 SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 /*!< GPE_MFPL PE4 setting for EPWM0_CH3*/
\r
1593 #define EPWM0_CH3_PB2 SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 /*!< GPB_MFPL PB2 setting for EPWM0_CH3*/
\r
1594 #define EPWM0_CH4_PD14 SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 /*!< GPD_MFPH PD14 setting for EPWM0_CH4*/
\r
1595 #define EPWM0_CH4_PB1 SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 /*!< GPB_MFPL PB1 setting for EPWM0_CH4*/
\r
1596 #define EPWM0_CH4_PE3 SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 /*!< GPE_MFPL PE3 setting for EPWM0_CH4*/
\r
1597 #define EPWM0_CH4_PA1 SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 /*!< GPA_MFPL PA1 setting for EPWM0_CH4*/
\r
1598 #define EPWM0_CH4_PE12 SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 /*!< GPE_MFPH PE12 setting for EPWM0_CH4*/
\r
1599 #define EPWM0_CH5_PB0 SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 /*!< GPB_MFPL PB0 setting for EPWM0_CH5*/
\r
1600 #define EPWM0_CH5_PE2 SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 /*!< GPE_MFPL PE2 setting for EPWM0_CH5*/
\r
1601 #define EPWM0_CH5_PA0 SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 /*!< GPA_MFPL PA0 setting for EPWM0_CH5*/
\r
1602 #define EPWM0_CH5_PE13 SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 /*!< GPE_MFPH PE13 setting for EPWM0_CH5*/
\r
1603 #define EPWM0_CH5_PH11 SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 /*!< GPH_MFPH PH11 setting for EPWM0_CH5*/
\r
1604 #define EPWM0_SYNC_IN_PA15 SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN /*!< GPA_MFPH PA15 setting for EPWM0_SYNC_IN*/
\r
1605 #define EPWM0_SYNC_OUT_PF5 SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT /*!< GPF_MFPL PF5 setting for EPWM0_SYNC_OUT*/
\r
1606 #define EPWM0_SYNC_OUT_PA11 SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT /*!< GPA_MFPH PA11 setting for EPWM0_SYNC_OUT*/
\r
1607 #define EPWM1_BRAKE0_PB7 SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 /*!< GPB_MFPL PB7 setting for EPWM1_BRAKE0*/
\r
1608 #define EPWM1_BRAKE0_PE10 SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 /*!< GPE_MFPH PE10 setting for EPWM1_BRAKE0*/
\r
1609 #define EPWM1_BRAKE1_PB6 SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 /*!< GPB_MFPL PB6 setting for EPWM1_BRAKE1*/
\r
1610 #define EPWM1_BRAKE1_PE11 SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 /*!< GPE_MFPH PE11 setting for EPWM1_BRAKE1*/
\r
1611 #define EPWM1_CH0_PC5 SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 /*!< GPC_MFPL PC5 setting for EPWM1_CH0*/
\r
1612 #define EPWM1_CH0_PE13 SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 /*!< GPE_MFPH PE13 setting for EPWM1_CH0*/
\r
1613 #define EPWM1_CH0_PC12 SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 /*!< GPC_MFPH PC12 setting for EPWM1_CH0*/
\r
1614 #define EPWM1_CH0_PB15 SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 /*!< GPB_MFPH PB15 setting for EPWM1_CH0*/
\r
1615 #define EPWM1_CH1_PB14 SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 /*!< GPB_MFPH PB14 setting for EPWM1_CH1*/
\r
1616 #define EPWM1_CH1_PC11 SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 /*!< GPC_MFPH PC11 setting for EPWM1_CH1*/
\r
1617 #define EPWM1_CH1_PC4 SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 /*!< GPC_MFPL PC4 setting for EPWM1_CH1*/
\r
1618 #define EPWM1_CH1_PC8 SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 /*!< GPC_MFPH PC8 setting for EPWM1_CH1*/
\r
1619 #define EPWM1_CH2_PC7 SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 /*!< GPC_MFPL PC7 setting for EPWM1_CH2*/
\r
1620 #define EPWM1_CH2_PC10 SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 /*!< GPC_MFPH PC10 setting for EPWM1_CH2*/
\r
1621 #define EPWM1_CH2_PC3 SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 /*!< GPC_MFPL PC3 setting for EPWM1_CH2*/
\r
1622 #define EPWM1_CH2_PB13 SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 /*!< GPB_MFPH PB13 setting for EPWM1_CH2*/
\r
1623 #define EPWM1_CH3_PB12 SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 /*!< GPB_MFPH PB12 setting for EPWM1_CH3*/
\r
1624 #define EPWM1_CH3_PC6 SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 /*!< GPC_MFPL PC6 setting for EPWM1_CH3*/
\r
1625 #define EPWM1_CH3_PC9 SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 /*!< GPC_MFPH PC9 setting for EPWM1_CH3*/
\r
1626 #define EPWM1_CH3_PC2 SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 /*!< GPC_MFPL PC2 setting for EPWM1_CH3*/
\r
1627 #define EPWM1_CH4_PB7 SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 /*!< GPB_MFPL PB7 setting for EPWM1_CH4*/
\r
1628 #define EPWM1_CH4_PB1 SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 /*!< GPB_MFPL PB1 setting for EPWM1_CH4*/
\r
1629 #define EPWM1_CH4_PC1 SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 /*!< GPC_MFPL PC1 setting for EPWM1_CH4*/
\r
1630 #define EPWM1_CH4_PA7 SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 /*!< GPA_MFPL PA7 setting for EPWM1_CH4*/
\r
1631 #define EPWM1_CH5_PA6 SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 /*!< GPA_MFPL PA6 setting for EPWM1_CH5*/
\r
1632 #define EPWM1_CH5_PC0 SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 /*!< GPC_MFPL PC0 setting for EPWM1_CH5*/
\r
1633 #define EPWM1_CH5_PB6 SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 /*!< GPB_MFPL PB6 setting for EPWM1_CH5*/
\r
1634 #define EPWM1_CH5_PB0 SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 /*!< GPB_MFPL PB0 setting for EPWM1_CH5*/
\r
1635 #define QEI0_A_PE3 SYS_GPE_MFPL_PE3MFP_QEI0_A /*!< GPE_MFPL PE3 setting for QEI0_A*/
\r
1636 #define QEI0_A_PA4 SYS_GPA_MFPL_PA4MFP_QEI0_A /*!< GPA_MFPL PA4 setting for QEI0_A*/
\r
1637 #define QEI0_A_PD11 SYS_GPD_MFPH_PD11MFP_QEI0_A /*!< GPD_MFPH PD11 setting for QEI0_A*/
\r
1638 #define QEI0_B_PD10 SYS_GPD_MFPH_PD10MFP_QEI0_B /*!< GPD_MFPH PD10 setting for QEI0_B*/
\r
1639 #define QEI0_B_PA3 SYS_GPA_MFPL_PA3MFP_QEI0_B /*!< GPA_MFPL PA3 setting for QEI0_B*/
\r
1640 #define QEI0_B_PE2 SYS_GPE_MFPL_PE2MFP_QEI0_B /*!< GPE_MFPL PE2 setting for QEI0_B*/
\r
1641 #define QEI0_INDEX_PE4 SYS_GPE_MFPL_PE4MFP_QEI0_INDEX /*!< GPE_MFPL PE4 setting for QEI0_INDEX*/
\r
1642 #define QEI0_INDEX_PA5 SYS_GPA_MFPL_PA5MFP_QEI0_INDEX /*!< GPA_MFPL PA5 setting for QEI0_INDEX*/
\r
1643 #define QEI0_INDEX_PD12 SYS_GPD_MFPH_PD12MFP_QEI0_INDEX /*!< GPD_MFPH PD12 setting for QEI0_INDEX*/
\r
1644 #define QEI1_A_PE6 SYS_GPE_MFPL_PE6MFP_QEI1_A /*!< GPE_MFPL PE6 setting for QEI1_A*/
\r
1645 #define QEI1_A_PA13 SYS_GPA_MFPH_PA13MFP_QEI1_A /*!< GPA_MFPH PA13 setting for QEI1_A*/
\r
1646 #define QEI1_A_PA9 SYS_GPA_MFPH_PA9MFP_QEI1_A /*!< GPA_MFPH PA9 setting for QEI1_A*/
\r
1647 #define QEI1_B_PA14 SYS_GPA_MFPH_PA14MFP_QEI1_B /*!< GPA_MFPH PA14 setting for QEI1_B*/
\r
1648 #define QEI1_B_PA8 SYS_GPA_MFPH_PA8MFP_QEI1_B /*!< GPA_MFPH PA8 setting for QEI1_B*/
\r
1649 #define QEI1_B_PE5 SYS_GPE_MFPL_PE5MFP_QEI1_B /*!< GPE_MFPL PE5 setting for QEI1_B*/
\r
1650 #define QEI1_INDEX_PE7 SYS_GPE_MFPL_PE7MFP_QEI1_INDEX /*!< GPE_MFPL PE7 setting for QEI1_INDEX*/
\r
1651 #define QEI1_INDEX_PA10 SYS_GPA_MFPH_PA10MFP_QEI1_INDEX /*!< GPA_MFPH PA10 setting for QEI1_INDEX*/
\r
1652 #define QEI1_INDEX_PA12 SYS_GPA_MFPH_PA12MFP_QEI1_INDEX /*!< GPA_MFPH PA12 setting for QEI1_INDEX*/
\r
1653 #define SC0_CLK_PF6 SYS_GPF_MFPL_PF6MFP_SC0_CLK /*!< GPF_MFPL PF6 setting for SC0_CLK*/
\r
1654 #define SC0_CLK_PE2 SYS_GPE_MFPL_PE2MFP_SC0_CLK /*!< GPE_MFPL PE2 setting for SC0_CLK*/
\r
1655 #define SC0_CLK_PA0 SYS_GPA_MFPL_PA0MFP_SC0_CLK /*!< GPA_MFPL PA0 setting for SC0_CLK*/
\r
1656 #define SC0_CLK_PB5 SYS_GPB_MFPL_PB5MFP_SC0_CLK /*!< GPB_MFPL PB5 setting for SC0_CLK*/
\r
1657 #define SC0_DAT_PE3 SYS_GPE_MFPL_PE3MFP_SC0_DAT /*!< GPE_MFPL PE3 setting for SC0_DAT*/
\r
1658 #define SC0_DAT_PB4 SYS_GPB_MFPL_PB4MFP_SC0_DAT /*!< GPB_MFPL PB4 setting for SC0_DAT*/
\r
1659 #define SC0_DAT_PA1 SYS_GPA_MFPL_PA1MFP_SC0_DAT /*!< GPA_MFPL PA1 setting for SC0_DAT*/
\r
1660 #define SC0_DAT_PF7 SYS_GPF_MFPL_PF7MFP_SC0_DAT /*!< GPF_MFPL PF7 setting for SC0_DAT*/
\r
1661 #define SC0_PWR_PE5 SYS_GPE_MFPL_PE5MFP_SC0_PWR /*!< GPE_MFPL PE5 setting for SC0_PWR*/
\r
1662 #define SC0_PWR_PA3 SYS_GPA_MFPL_PA3MFP_SC0_PWR /*!< GPA_MFPL PA3 setting for SC0_PWR*/
\r
1663 #define SC0_PWR_PB2 SYS_GPB_MFPL_PB2MFP_SC0_PWR /*!< GPB_MFPL PB2 setting for SC0_PWR*/
\r
1664 #define SC0_PWR_PF9 SYS_GPF_MFPH_PF9MFP_SC0_PWR /*!< GPF_MFPH PF9 setting for SC0_PWR*/
\r
1665 #define SC0_RST_PF8 SYS_GPF_MFPH_PF8MFP_SC0_RST /*!< GPF_MFPH PF8 setting for SC0_RST*/
\r
1666 #define SC0_RST_PE4 SYS_GPE_MFPL_PE4MFP_SC0_RST /*!< GPE_MFPL PE4 setting for SC0_RST*/
\r
1667 #define SC0_RST_PA2 SYS_GPA_MFPL_PA2MFP_SC0_RST /*!< GPA_MFPL PA2 setting for SC0_RST*/
\r
1668 #define SC0_RST_PB3 SYS_GPB_MFPL_PB3MFP_SC0_RST /*!< GPB_MFPL PB3 setting for SC0_RST*/
\r
1669 #define SC0_nCD_PE6 SYS_GPE_MFPL_PE6MFP_SC0_nCD /*!< GPE_MFPL PE6 setting for SC0_nCD*/
\r
1670 #define SC0_nCD_PF10 SYS_GPF_MFPH_PF10MFP_SC0_nCD /*!< GPF_MFPH PF10 setting for SC0_nCD*/
\r
1671 #define SC0_nCD_PA4 SYS_GPA_MFPL_PA4MFP_SC0_nCD /*!< GPA_MFPL PA4 setting for SC0_nCD*/
\r
1672 #define SC0_nCD_PC12 SYS_GPC_MFPH_PC12MFP_SC0_nCD /*!< GPC_MFPH PC12 setting for SC0_nCD*/
\r
1673 #define SC1_CLK_PC0 SYS_GPC_MFPL_PC0MFP_SC1_CLK /*!< GPC_MFPL PC0 setting for SC1_CLK*/
\r
1674 #define SC1_CLK_PB12 SYS_GPB_MFPH_PB12MFP_SC1_CLK /*!< GPB_MFPH PB12 setting for SC1_CLK*/
\r
1675 #define SC1_CLK_PD4 SYS_GPD_MFPL_PD4MFP_SC1_CLK /*!< GPD_MFPL PD4 setting for SC1_CLK*/
\r
1676 #define SC1_DAT_PD5 SYS_GPD_MFPL_PD5MFP_SC1_DAT /*!< GPD_MFPL PD5 setting for SC1_DAT*/
\r
1677 #define SC1_DAT_PB13 SYS_GPB_MFPH_PB13MFP_SC1_DAT /*!< GPB_MFPH PB13 setting for SC1_DAT*/
\r
1678 #define SC1_DAT_PC1 SYS_GPC_MFPL_PC1MFP_SC1_DAT /*!< GPC_MFPL PC1 setting for SC1_DAT*/
\r
1679 #define SC1_PWR_PB15 SYS_GPB_MFPH_PB15MFP_SC1_PWR /*!< GPB_MFPH PB15 setting for SC1_PWR*/
\r
1680 #define SC1_PWR_PC3 SYS_GPC_MFPL_PC3MFP_SC1_PWR /*!< GPC_MFPL PC3 setting for SC1_PWR*/
\r
1681 #define SC1_PWR_PD7 SYS_GPD_MFPL_PD7MFP_SC1_PWR /*!< GPD_MFPL PD7 setting for SC1_PWR*/
\r
1682 #define SC1_RST_PD6 SYS_GPD_MFPL_PD6MFP_SC1_RST /*!< GPD_MFPL PD6 setting for SC1_RST*/
\r
1683 #define SC1_RST_PB14 SYS_GPB_MFPH_PB14MFP_SC1_RST /*!< GPB_MFPH PB14 setting for SC1_RST*/
\r
1684 #define SC1_RST_PC2 SYS_GPC_MFPL_PC2MFP_SC1_RST /*!< GPC_MFPL PC2 setting for SC1_RST*/
\r
1685 #define SC1_nCD_PD3 SYS_GPD_MFPL_PD3MFP_SC1_nCD /*!< GPD_MFPL PD3 setting for SC1_nCD*/
\r
1686 #define SC1_nCD_PC4 SYS_GPC_MFPL_PC4MFP_SC1_nCD /*!< GPC_MFPL PC4 setting for SC1_nCD*/
\r
1687 #define SC1_nCD_PD14 SYS_GPD_MFPH_PD14MFP_SC1_nCD /*!< GPD_MFPH PD14 setting for SC1_nCD*/
\r
1688 #define SC2_CLK_PD0 SYS_GPD_MFPL_PD0MFP_SC2_CLK /*!< GPD_MFPL PD0 setting for SC2_CLK*/
\r
1689 #define SC2_CLK_PA15 SYS_GPA_MFPH_PA15MFP_SC2_CLK /*!< GPA_MFPH PA15 setting for SC2_CLK*/
\r
1690 #define SC2_CLK_PE0 SYS_GPE_MFPL_PE0MFP_SC2_CLK /*!< GPE_MFPL PE0 setting for SC2_CLK*/
\r
1691 #define SC2_CLK_PA8 SYS_GPA_MFPH_PA8MFP_SC2_CLK /*!< GPA_MFPH PA8 setting for SC2_CLK*/
\r
1692 #define SC2_CLK_PA6 SYS_GPA_MFPL_PA6MFP_SC2_CLK /*!< GPA_MFPL PA6 setting for SC2_CLK*/
\r
1693 #define SC2_DAT_PE1 SYS_GPE_MFPL_PE1MFP_SC2_DAT /*!< GPE_MFPL PE1 setting for SC2_DAT*/
\r
1694 #define SC2_DAT_PD1 SYS_GPD_MFPL_PD1MFP_SC2_DAT /*!< GPD_MFPL PD1 setting for SC2_DAT*/
\r
1695 #define SC2_DAT_PA9 SYS_GPA_MFPH_PA9MFP_SC2_DAT /*!< GPA_MFPH PA9 setting for SC2_DAT*/
\r
1696 #define SC2_DAT_PA14 SYS_GPA_MFPH_PA14MFP_SC2_DAT /*!< GPA_MFPH PA14 setting for SC2_DAT*/
\r
1697 #define SC2_DAT_PA7 SYS_GPA_MFPL_PA7MFP_SC2_DAT /*!< GPA_MFPL PA7 setting for SC2_DAT*/
\r
1698 #define SC2_PWR_PD3 SYS_GPD_MFPL_PD3MFP_SC2_PWR /*!< GPD_MFPL PD3 setting for SC2_PWR*/
\r
1699 #define SC2_PWR_PA11 SYS_GPA_MFPH_PA11MFP_SC2_PWR /*!< GPA_MFPH PA11 setting for SC2_PWR*/
\r
1700 #define SC2_PWR_PA12 SYS_GPA_MFPH_PA12MFP_SC2_PWR /*!< GPA_MFPH PA12 setting for SC2_PWR*/
\r
1701 #define SC2_PWR_PH8 SYS_GPH_MFPH_PH8MFP_SC2_PWR /*!< GPH_MFPH PH8 setting for SC2_PWR*/
\r
1702 #define SC2_PWR_PC7 SYS_GPC_MFPL_PC7MFP_SC2_PWR /*!< GPC_MFPL PC7 setting for SC2_PWR*/
\r
1703 #define SC2_RST_PD2 SYS_GPD_MFPL_PD2MFP_SC2_RST /*!< GPD_MFPL PD2 setting for SC2_RST*/
\r
1704 #define SC2_RST_PC6 SYS_GPC_MFPL_PC6MFP_SC2_RST /*!< GPC_MFPL PC6 setting for SC2_RST*/
\r
1705 #define SC2_RST_PH9 SYS_GPH_MFPH_PH9MFP_SC2_RST /*!< GPH_MFPH PH9 setting for SC2_RST*/
\r
1706 #define SC2_RST_PA10 SYS_GPA_MFPH_PA10MFP_SC2_RST /*!< GPA_MFPH PA10 setting for SC2_RST*/
\r
1707 #define SC2_RST_PA13 SYS_GPA_MFPH_PA13MFP_SC2_RST /*!< GPA_MFPH PA13 setting for SC2_RST*/
\r
1708 #define SC2_nCD_PH10 SYS_GPH_MFPH_PH10MFP_SC2_nCD /*!< GPH_MFPH PH10 setting for SC2_nCD*/
\r
1709 #define SC2_nCD_PA5 SYS_GPA_MFPL_PA5MFP_SC2_nCD /*!< GPA_MFPL PA5 setting for SC2_nCD*/
\r
1710 #define SC2_nCD_PC13 SYS_GPC_MFPH_PC13MFP_SC2_nCD /*!< GPC_MFPH PC13 setting for SC2_nCD*/
\r
1711 #define SC2_nCD_PD13 SYS_GPD_MFPH_PD13MFP_SC2_nCD /*!< GPD_MFPH PD13 setting for SC2_nCD*/
\r
1712 #define SD0_CLK_PE6 SYS_GPE_MFPL_PE6MFP_SD0_CLK /*!< GPE_MFPL PE6 setting for SD0_CLK*/
\r
1713 #define SD0_CLK_PB1 SYS_GPB_MFPL_PB1MFP_SD0_CLK /*!< GPB_MFPL PB1 setting for SD0_CLK*/
\r
1714 #define SD0_CMD_PB0 SYS_GPB_MFPL_PB0MFP_SD0_CMD /*!< GPB_MFPL PB0 setting for SD0_CMD*/
\r
1715 #define SD0_CMD_PE7 SYS_GPE_MFPL_PE7MFP_SD0_CMD /*!< GPE_MFPL PE7 setting for SD0_CMD*/
\r
1716 #define SD0_DAT0_PB2 SYS_GPB_MFPL_PB2MFP_SD0_DAT0 /*!< GPB_MFPL PB2 setting for SD0_DAT0*/
\r
1717 #define SD0_DAT0_PE2 SYS_GPE_MFPL_PE2MFP_SD0_DAT0 /*!< GPE_MFPL PE2 setting for SD0_DAT0*/
\r
1718 #define SD0_DAT1_PE3 SYS_GPE_MFPL_PE3MFP_SD0_DAT1 /*!< GPE_MFPL PE3 setting for SD0_DAT1*/
\r
1719 #define SD0_DAT1_PB3 SYS_GPB_MFPL_PB3MFP_SD0_DAT1 /*!< GPB_MFPL PB3 setting for SD0_DAT1*/
\r
1720 #define SD0_DAT2_PB4 SYS_GPB_MFPL_PB4MFP_SD0_DAT2 /*!< GPB_MFPL PB4 setting for SD0_DAT2*/
\r
1721 #define SD0_DAT2_PE4 SYS_GPE_MFPL_PE4MFP_SD0_DAT2 /*!< GPE_MFPL PE4 setting for SD0_DAT2*/
\r
1722 #define SD0_DAT3_PE5 SYS_GPE_MFPL_PE5MFP_SD0_DAT3 /*!< GPE_MFPL PE5 setting for SD0_DAT3*/
\r
1723 #define SD0_DAT3_PB5 SYS_GPB_MFPL_PB5MFP_SD0_DAT3 /*!< GPB_MFPL PB5 setting for SD0_DAT3*/
\r
1724 #define SD0_nCD_PB12 SYS_GPB_MFPH_PB12MFP_SD0_nCD /*!< GPB_MFPH PB12 setting for SD0_nCD*/
\r
1725 #define SD0_nCD_PD13 SYS_GPD_MFPH_PD13MFP_SD0_nCD /*!< GPD_MFPH PD13 setting for SD0_nCD*/
\r
1726 #define QSPI0_CLK_PF2 SYS_GPF_MFPL_PF2MFP_QSPI0_CLK /*!< GPF_MFPL PF2 setting for QSPI0_CLK*/
\r
1727 #define QSPI0_CLK_PH8 SYS_GPH_MFPH_PH8MFP_QSPI0_CLK /*!< GPH_MFPH PH8 setting for QSPI0_CLK*/
\r
1728 #define QSPI0_CLK_PA2 SYS_GPA_MFPL_PA2MFP_QSPI0_CLK /*!< GPA_MFPL PA2 setting for QSPI0_CLK*/
\r
1729 #define QSPI0_CLK_PC2 SYS_GPC_MFPL_PC2MFP_QSPI0_CLK /*!< GPC_MFPL PC2 setting for QSPI0_CLK*/
\r
1730 #define QSPI0_MISO0_PC1 SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 /*!< GPC_MFPL PC1 setting for QSPI0_MISO0*/
\r
1731 #define QSPI0_MISO0_PE1 SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0 /*!< GPE_MFPL PE1 setting for QSPI0_MISO0*/
\r
1732 #define QSPI0_MISO0_PA1 SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0 /*!< GPA_MFPL PA1 setting for QSPI0_MISO0*/
\r
1733 #define QSPI0_MISO1_PC5 SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 /*!< GPC_MFPL PC5 setting for QSPI0_MISO1*/
\r
1734 #define QSPI0_MISO1_PH10 SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 /*!< GPH_MFPH PH10 setting for QSPI0_MISO1*/
\r
1735 #define QSPI0_MISO1_PA5 SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1 /*!< GPA_MFPL PA5 setting for QSPI0_MISO1*/
\r
1736 #define QSPI0_MOSI0_PC0 SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 /*!< GPC_MFPL PC0 setting for QSPI0_MOSI0*/
\r
1737 #define QSPI0_MOSI0_PE0 SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0 /*!< GPE_MFPL PE0 setting for QSPI0_MOSI0*/
\r
1738 #define QSPI0_MOSI0_PA0 SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0 /*!< GPA_MFPL PA0 setting for QSPI0_MOSI0*/
\r
1739 #define QSPI0_MOSI1_PA4 SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1 /*!< GPA_MFPL PA4 setting for QSPI0_MOSI1*/
\r
1740 #define QSPI0_MOSI1_PH11 SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 /*!< GPH_MFPH PH11 setting for QSPI0_MOSI1*/
\r
1741 #define QSPI0_MOSI1_PC4 SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 /*!< GPC_MFPL PC4 setting for QSPI0_MOSI1*/
\r
1742 #define QSPI0_SS_PH9 SYS_GPH_MFPH_PH9MFP_QSPI0_SS /*!< GPH_MFPH PH9 setting for QSPI0_SS*/
\r
1743 #define QSPI0_SS_PA3 SYS_GPA_MFPL_PA3MFP_QSPI0_SS /*!< GPA_MFPL PA3 setting for QSPI0_SS*/
\r
1744 #define QSPI0_SS_PC3 SYS_GPC_MFPL_PC3MFP_QSPI0_SS /*!< GPC_MFPL PC3 setting for QSPI0_SS*/
\r
1745 #define SPI0_CLK_PD2 SYS_GPD_MFPL_PD2MFP_SPI0_CLK /*!< GPD_MFPL PD2 setting for SPI0_CLK*/
\r
1746 #define SPI0_CLK_PF8 SYS_GPF_MFPH_PF8MFP_SPI0_CLK /*!< GPF_MFPH PF8 setting for SPI0_CLK*/
\r
1747 #define SPI0_CLK_PA2 SYS_GPA_MFPL_PA2MFP_SPI0_CLK /*!< GPA_MFPL PA2 setting for SPI0_CLK*/
\r
1748 #define SPI0_CLK_PB14 SYS_GPB_MFPH_PB14MFP_SPI0_CLK /*!< GPB_MFPH PB14 setting for SPI0_CLK*/
\r
1749 #define SPI0_I2SMCLK_PD13 SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK /*!< GPD_MFPH PD13 setting for SPI0_I2SMCLK*/
\r
1750 #define SPI0_I2SMCLK_PA4 SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK /*!< GPA_MFPL PA4 setting for SPI0_I2SMCLK*/
\r
1751 #define SPI0_I2SMCLK_PB11 SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK /*!< GPB_MFPH PB11 setting for SPI0_I2SMCLK*/
\r
1752 #define SPI0_I2SMCLK_PB0 SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK /*!< GPB_MFPL PB0 setting for SPI0_I2SMCLK*/
\r
1753 #define SPI0_I2SMCLK_PD14 SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK /*!< GPD_MFPH PD14 setting for SPI0_I2SMCLK*/
\r
1754 #define SPI0_I2SMCLK_PF10 SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK /*!< GPF_MFPH PF10 setting for SPI0_I2SMCLK*/
\r
1755 #define SPI0_MISO_PF7 SYS_GPF_MFPL_PF7MFP_SPI0_MISO /*!< GPF_MFPL PF7 setting for SPI0_MISO*/
\r
1756 #define SPI0_MISO_PB13 SYS_GPB_MFPH_PB13MFP_SPI0_MISO /*!< GPB_MFPH PB13 setting for SPI0_MISO*/
\r
1757 #define SPI0_MISO_PA1 SYS_GPA_MFPL_PA1MFP_SPI0_MISO /*!< GPA_MFPL PA1 setting for SPI0_MISO*/
\r
1758 #define SPI0_MISO_PD1 SYS_GPD_MFPL_PD1MFP_SPI0_MISO /*!< GPD_MFPL PD1 setting for SPI0_MISO*/
\r
1759 #define SPI0_MOSI_PA0 SYS_GPA_MFPL_PA0MFP_SPI0_MOSI /*!< GPA_MFPL PA0 setting for SPI0_MOSI*/
\r
1760 #define SPI0_MOSI_PB12 SYS_GPB_MFPH_PB12MFP_SPI0_MOSI /*!< GPB_MFPH PB12 setting for SPI0_MOSI*/
\r
1761 #define SPI0_MOSI_PD0 SYS_GPD_MFPL_PD0MFP_SPI0_MOSI /*!< GPD_MFPL PD0 setting for SPI0_MOSI*/
\r
1762 #define SPI0_MOSI_PF6 SYS_GPF_MFPL_PF6MFP_SPI0_MOSI /*!< GPF_MFPL PF6 setting for SPI0_MOSI*/
\r
1763 #define SPI0_SS_PB15 SYS_GPB_MFPH_PB15MFP_SPI0_SS /*!< GPB_MFPH PB15 setting for SPI0_SS*/
\r
1764 #define SPI0_SS_PA3 SYS_GPA_MFPL_PA3MFP_SPI0_SS /*!< GPA_MFPL PA3 setting for SPI0_SS*/
\r
1765 #define SPI0_SS_PD3 SYS_GPD_MFPL_PD3MFP_SPI0_SS /*!< GPD_MFPL PD3 setting for SPI0_SS*/
\r
1766 #define SPI0_SS_PF9 SYS_GPF_MFPH_PF9MFP_SPI0_SS /*!< GPF_MFPH PF9 setting for SPI0_SS*/
\r
1767 #define SPI1_CLK_PB3 SYS_GPB_MFPL_PB3MFP_SPI1_CLK /*!< GPB_MFPL PB3 setting for SPI1_CLK*/
\r
1768 #define SPI1_CLK_PH6 SYS_GPH_MFPL_PH6MFP_SPI1_CLK /*!< GPH_MFPL PH6 setting for SPI1_CLK*/
\r
1769 #define SPI1_CLK_PH8 SYS_GPH_MFPH_PH8MFP_SPI1_CLK /*!< GPH_MFPH PH8 setting for SPI1_CLK*/
\r
1770 #define SPI1_CLK_PC1 SYS_GPC_MFPL_PC1MFP_SPI1_CLK /*!< GPC_MFPL PC1 setting for SPI1_CLK*/
\r
1771 #define SPI1_CLK_PD5 SYS_GPD_MFPL_PD5MFP_SPI1_CLK /*!< GPD_MFPL PD5 setting for SPI1_CLK*/
\r
1772 #define SPI1_CLK_PA7 SYS_GPA_MFPL_PA7MFP_SPI1_CLK /*!< GPA_MFPL PA7 setting for SPI1_CLK*/
\r
1773 #define SPI1_I2SMCLK_PB1 SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK /*!< GPB_MFPL PB1 setting for SPI1_I2SMCLK*/
\r
1774 #define SPI1_I2SMCLK_PH10 SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK /*!< GPH_MFPH PH10 setting for SPI1_I2SMCLK*/
\r
1775 #define SPI1_I2SMCLK_PC4 SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK /*!< GPC_MFPL PC4 setting for SPI1_I2SMCLK*/
\r
1776 #define SPI1_I2SMCLK_PD13 SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK /*!< GPD_MFPH PD13 setting for SPI1_I2SMCLK*/
\r
1777 #define SPI1_I2SMCLK_PA5 SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK /*!< GPA_MFPL PA5 setting for SPI1_I2SMCLK*/
\r
1778 #define SPI1_MISO_PD7 SYS_GPD_MFPL_PD7MFP_SPI1_MISO /*!< GPD_MFPL PD7 setting for SPI1_MISO*/
\r
1779 #define SPI1_MISO_PC7 SYS_GPC_MFPL_PC7MFP_SPI1_MISO /*!< GPC_MFPL PC7 setting for SPI1_MISO*/
\r
1780 #define SPI1_MISO_PB5 SYS_GPB_MFPL_PB5MFP_SPI1_MISO /*!< GPB_MFPL PB5 setting for SPI1_MISO*/
\r
1781 #define SPI1_MISO_PE1 SYS_GPE_MFPL_PE1MFP_SPI1_MISO /*!< GPE_MFPL PE1 setting for SPI1_MISO*/
\r
1782 #define SPI1_MISO_PH4 SYS_GPH_MFPL_PH4MFP_SPI1_MISO /*!< GPH_MFPL PH4 setting for SPI1_MISO*/
\r
1783 #define SPI1_MISO_PC3 SYS_GPC_MFPL_PC3MFP_SPI1_MISO /*!< GPC_MFPL PC3 setting for SPI1_MISO*/
\r
1784 #define SPI1_MOSI_PD6 SYS_GPD_MFPL_PD6MFP_SPI1_MOSI /*!< GPD_MFPL PD6 setting for SPI1_MOSI*/
\r
1785 #define SPI1_MOSI_PE0 SYS_GPE_MFPL_PE0MFP_SPI1_MOSI /*!< GPE_MFPL PE0 setting for SPI1_MOSI*/
\r
1786 #define SPI1_MOSI_PB4 SYS_GPB_MFPL_PB4MFP_SPI1_MOSI /*!< GPB_MFPL PB4 setting for SPI1_MOSI*/
\r
1787 #define SPI1_MOSI_PC6 SYS_GPC_MFPL_PC6MFP_SPI1_MOSI /*!< GPC_MFPL PC6 setting for SPI1_MOSI*/
\r
1788 #define SPI1_MOSI_PC2 SYS_GPC_MFPL_PC2MFP_SPI1_MOSI /*!< GPC_MFPL PC2 setting for SPI1_MOSI*/
\r
1789 #define SPI1_MOSI_PH5 SYS_GPH_MFPL_PH5MFP_SPI1_MOSI /*!< GPH_MFPL PH5 setting for SPI1_MOSI*/
\r
1790 #define SPI1_SS_PB2 SYS_GPB_MFPL_PB2MFP_SPI1_SS /*!< GPB_MFPL PB2 setting for SPI1_SS*/
\r
1791 #define SPI1_SS_PH9 SYS_GPH_MFPH_PH9MFP_SPI1_SS /*!< GPH_MFPH PH9 setting for SPI1_SS*/
\r
1792 #define SPI1_SS_PD4 SYS_GPD_MFPL_PD4MFP_SPI1_SS /*!< GPD_MFPL PD4 setting for SPI1_SS*/
\r
1793 #define SPI1_SS_PC0 SYS_GPC_MFPL_PC0MFP_SPI1_SS /*!< GPC_MFPL PC0 setting for SPI1_SS*/
\r
1794 #define SPI1_SS_PA6 SYS_GPA_MFPL_PA6MFP_SPI1_SS /*!< GPA_MFPL PA6 setting for SPI1_SS*/
\r
1795 #define SPI1_SS_PH7 SYS_GPH_MFPL_PH7MFP_SPI1_SS /*!< GPH_MFPL PH7 setting for SPI1_SS*/
\r
1796 #define SPI2_CLK_PE8 SYS_GPE_MFPH_PE8MFP_SPI2_CLK /*!< GPE_MFPH PE8 setting for SPI2_CLK*/
\r
1797 #define SPI2_CLK_PG3 SYS_GPG_MFPL_PG3MFP_SPI2_CLK /*!< GPG_MFPL PG3 setting for SPI2_CLK*/
\r
1798 #define SPI2_CLK_PA10 SYS_GPA_MFPH_PA10MFP_SPI2_CLK /*!< GPA_MFPH PA10 setting for SPI2_CLK*/
\r
1799 #define SPI2_CLK_PA13 SYS_GPA_MFPH_PA13MFP_SPI2_CLK /*!< GPA_MFPH PA13 setting for SPI2_CLK*/
\r
1800 #define SPI2_I2SMCLK_PC13 SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK /*!< GPC_MFPH PC13 setting for SPI2_I2SMCLK*/
\r
1801 #define SPI2_I2SMCLK_PE12 SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK /*!< GPE_MFPH PE12 setting for SPI2_I2SMCLK*/
\r
1802 #define SPI2_MISO_PG4 SYS_GPG_MFPL_PG4MFP_SPI2_MISO /*!< GPG_MFPL PG4 setting for SPI2_MISO*/
\r
1803 #define SPI2_MISO_PA9 SYS_GPA_MFPH_PA9MFP_SPI2_MISO /*!< GPA_MFPH PA9 setting for SPI2_MISO*/
\r
1804 #define SPI2_MISO_PA14 SYS_GPA_MFPH_PA14MFP_SPI2_MISO /*!< GPA_MFPH PA14 setting for SPI2_MISO*/
\r
1805 #define SPI2_MISO_PE9 SYS_GPE_MFPH_PE9MFP_SPI2_MISO /*!< GPE_MFPH PE9 setting for SPI2_MISO*/
\r
1806 #define SPI2_MOSI_PE10 SYS_GPE_MFPH_PE10MFP_SPI2_MOSI /*!< GPE_MFPH PE10 setting for SPI2_MOSI*/
\r
1807 #define SPI2_MOSI_PA15 SYS_GPA_MFPH_PA15MFP_SPI2_MOSI /*!< GPA_MFPH PA15 setting for SPI2_MOSI*/
\r
1808 #define SPI2_MOSI_PA8 SYS_GPA_MFPH_PA8MFP_SPI2_MOSI /*!< GPA_MFPH PA8 setting for SPI2_MOSI*/
\r
1809 #define SPI2_MOSI_PF11 SYS_GPF_MFPH_PF11MFP_SPI2_MOSI /*!< GPF_MFPH PF11 setting for SPI2_MOSI*/
\r
1810 #define SPI2_SS_PG2 SYS_GPG_MFPL_PG2MFP_SPI2_SS /*!< GPG_MFPL PG2 setting for SPI2_SS*/
\r
1811 #define SPI2_SS_PE11 SYS_GPE_MFPH_PE11MFP_SPI2_SS /*!< GPE_MFPH PE11 setting for SPI2_SS*/
\r
1812 #define SPI2_SS_PA11 SYS_GPA_MFPH_PA11MFP_SPI2_SS /*!< GPA_MFPH PA11 setting for SPI2_SS*/
\r
1813 #define SPI2_SS_PA12 SYS_GPA_MFPH_PA12MFP_SPI2_SS /*!< GPA_MFPH PA12 setting for SPI2_SS*/
\r
1814 #define SPI3_CLK_PB11 SYS_GPB_MFPH_PB11MFP_SPI3_CLK /*!< GPB_MFPH PB11 setting for SPI3_CLK*/
\r
1815 #define SPI3_CLK_PE4 SYS_GPE_MFPL_PE4MFP_SPI3_CLK /*!< GPE_MFPL PE4 setting for SPI3_CLK*/
\r
1816 #define SPI3_CLK_PC10 SYS_GPC_MFPH_PC10MFP_SPI3_CLK /*!< GPC_MFPH PC10 setting for SPI3_CLK*/
\r
1817 #define SPI3_I2SMCLK_PE6 SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK /*!< GPE_MFPL PE6 setting for SPI3_I2SMCLK*/
\r
1818 #define SPI3_I2SMCLK_PB1 SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK /*!< GPB_MFPL PB1 setting for SPI3_I2SMCLK*/
\r
1819 #define SPI3_I2SMCLK_PD14 SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK /*!< GPD_MFPH PD14 setting for SPI3_I2SMCLK*/
\r
1820 #define SPI3_MISO_PC12 SYS_GPC_MFPH_PC12MFP_SPI3_MISO /*!< GPC_MFPH PC12 setting for SPI3_MISO*/
\r
1821 #define SPI3_MISO_PB9 SYS_GPB_MFPH_PB9MFP_SPI3_MISO /*!< GPB_MFPH PB9 setting for SPI3_MISO*/
\r
1822 #define SPI3_MISO_PE3 SYS_GPE_MFPL_PE3MFP_SPI3_MISO /*!< GPE_MFPL PE3 setting for SPI3_MISO*/
\r
1823 #define SPI3_MOSI_PB8 SYS_GPB_MFPH_PB8MFP_SPI3_MOSI /*!< GPB_MFPH PB8 setting for SPI3_MOSI*/
\r
1824 #define SPI3_MOSI_PE2 SYS_GPE_MFPL_PE2MFP_SPI3_MOSI /*!< GPE_MFPL PE2 setting for SPI3_MOSI*/
\r
1825 #define SPI3_MOSI_PC11 SYS_GPC_MFPH_PC11MFP_SPI3_MOSI /*!< GPC_MFPH PC11 setting for SPI3_MOSI*/
\r
1826 #define SPI3_SS_PE5 SYS_GPE_MFPL_PE5MFP_SPI3_SS /*!< GPE_MFPL PE5 setting for SPI3_SS*/
\r
1827 #define SPI3_SS_PB10 SYS_GPB_MFPH_PB10MFP_SPI3_SS /*!< GPB_MFPH PB10 setting for SPI3_SS*/
\r
1828 #define SPI3_SS_PC9 SYS_GPC_MFPH_PC9MFP_SPI3_SS /*!< GPC_MFPH PC9 setting for SPI3_SS*/
\r
1829 #define TAMPER0_PF6 SYS_GPF_MFPL_PF6MFP_TAMPER0 /*!< GPF_MFPL PF6 setting for TAMPER0*/
\r
1830 #define TAMPER1_PF7 SYS_GPF_MFPL_PF7MFP_TAMPER1 /*!< GPF_MFPL PF7 setting for TAMPER1*/
\r
1831 #define TAMPER2_PF8 SYS_GPF_MFPH_PF8MFP_TAMPER2 /*!< GPF_MFPH PF8 setting for TAMPER2*/
\r
1832 #define TAMPER3_PF9 SYS_GPF_MFPH_PF9MFP_TAMPER3 /*!< GPF_MFPH PF9 setting for TAMPER3*/
\r
1833 #define TAMPER4_PF10 SYS_GPF_MFPH_PF10MFP_TAMPER4 /*!< GPF_MFPH PF10 setting for TAMPER4*/
\r
1834 #define TAMPER5_PF11 SYS_GPF_MFPH_PF11MFP_TAMPER5 /*!< GPF_MFPH PF11 setting for TAMPER5*/
\r
1835 #define TM0_PC7 SYS_GPC_MFPL_PC7MFP_TM0 /*!< GPC_MFPL PC7 setting for TM0*/
\r
1836 #define TM0_PB5 SYS_GPB_MFPL_PB5MFP_TM0 /*!< GPB_MFPL PB5 setting for TM0*/
\r
1837 #define TM0_PG2 SYS_GPG_MFPL_PG2MFP_TM0 /*!< GPG_MFPL PG2 setting for TM0*/
\r
1838 #define TM0_EXT_PA11 SYS_GPA_MFPH_PA11MFP_TM0_EXT /*!< GPA_MFPH PA11 setting for TM0_EXT*/
\r
1839 #define TM0_EXT_PB15 SYS_GPB_MFPH_PB15MFP_TM0_EXT /*!< GPB_MFPH PB15 setting for TM0_EXT*/
\r
1840 #define TM1_PG3 SYS_GPG_MFPL_PG3MFP_TM1 /*!< GPG_MFPL PG3 setting for TM1*/
\r
1841 #define TM1_PB4 SYS_GPB_MFPL_PB4MFP_TM1 /*!< GPB_MFPL PB4 setting for TM1*/
\r
1842 #define TM1_PC6 SYS_GPC_MFPL_PC6MFP_TM1 /*!< GPC_MFPL PC6 setting for TM1*/
\r
1843 #define TM1_EXT_PA10 SYS_GPA_MFPH_PA10MFP_TM1_EXT /*!< GPA_MFPH PA10 setting for TM1_EXT*/
\r
1844 #define TM1_EXT_PB14 SYS_GPB_MFPH_PB14MFP_TM1_EXT /*!< GPB_MFPH PB14 setting for TM1_EXT*/
\r
1845 #define TM2_PG4 SYS_GPG_MFPL_PG4MFP_TM2 /*!< GPG_MFPL PG4 setting for TM2*/
\r
1846 #define TM2_PD0 SYS_GPD_MFPL_PD0MFP_TM2 /*!< GPD_MFPL PD0 setting for TM2*/
\r
1847 #define TM2_PB3 SYS_GPB_MFPL_PB3MFP_TM2 /*!< GPB_MFPL PB3 setting for TM2*/
\r
1848 #define TM2_PA7 SYS_GPA_MFPL_PA7MFP_TM2 /*!< GPA_MFPL PA7 setting for TM2*/
\r
1849 #define TM2_EXT_PB13 SYS_GPB_MFPH_PB13MFP_TM2_EXT /*!< GPB_MFPH PB13 setting for TM2_EXT*/
\r
1850 #define TM2_EXT_PA9 SYS_GPA_MFPH_PA9MFP_TM2_EXT /*!< GPA_MFPH PA9 setting for TM2_EXT*/
\r
1851 #define TM3_PA6 SYS_GPA_MFPL_PA6MFP_TM3 /*!< GPA_MFPL PA6 setting for TM3*/
\r
1852 #define TM3_PF11 SYS_GPF_MFPH_PF11MFP_TM3 /*!< GPF_MFPH PF11 setting for TM3*/
\r
1853 #define TM3_PB2 SYS_GPB_MFPL_PB2MFP_TM3 /*!< GPB_MFPL PB2 setting for TM3*/
\r
1854 #define TM3_EXT_PA8 SYS_GPA_MFPH_PA8MFP_TM3_EXT /*!< GPA_MFPH PA8 setting for TM3_EXT*/
\r
1855 #define TM3_EXT_PB12 SYS_GPB_MFPH_PB12MFP_TM3_EXT /*!< GPB_MFPH PB12 setting for TM3_EXT*/
\r
1856 #define TRACE_CLK_PE12 SYS_GPE_MFPH_PE12MFP_TRACE_CLK /*!< GPE_MFPH PE12 setting for TRACE_CLK*/
\r
1857 #define TRACE_DATA0_PE11 SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 /*!< GPE_MFPH PE11 setting for TRACE_DATA0*/
\r
1858 #define TRACE_DATA1_PE10 SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 /*!< GPE_MFPH PE10 setting for TRACE_DATA1*/
\r
1859 #define TRACE_DATA2_PE9 SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 /*!< GPE_MFPH PE9 setting for TRACE_DATA2*/
\r
1860 #define TRACE_DATA3_PE8 SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 /*!< GPE_MFPH PE8 setting for TRACE_DATA3*/
\r
1861 #define UART0_RXD_PD2 SYS_GPD_MFPL_PD2MFP_UART0_RXD /*!< GPD_MFPL PD2 setting for UART0_RXD*/
\r
1862 #define UART0_RXD_PB8 SYS_GPB_MFPH_PB8MFP_UART0_RXD /*!< GPB_MFPH PB8 setting for UART0_RXD*/
\r
1863 #define UART0_RXD_PA0 SYS_GPA_MFPL_PA0MFP_UART0_RXD /*!< GPA_MFPL PA0 setting for UART0_RXD*/
\r
1864 #define UART0_RXD_PA6 SYS_GPA_MFPL_PA6MFP_UART0_RXD /*!< GPA_MFPL PA6 setting for UART0_RXD*/
\r
1865 #define UART0_RXD_PB12 SYS_GPB_MFPH_PB12MFP_UART0_RXD /*!< GPB_MFPH PB12 setting for UART0_RXD*/
\r
1866 #define UART0_RXD_PA15 SYS_GPA_MFPH_PA15MFP_UART0_RXD /*!< GPA_MFPH PA15 setting for UART0_RXD*/
\r
1867 #define UART0_RXD_PC11 SYS_GPC_MFPH_PC11MFP_UART0_RXD /*!< GPC_MFPH PC11 setting for UART0_RXD*/
\r
1868 #define UART0_RXD_PH11 SYS_GPH_MFPH_PH11MFP_UART0_RXD /*!< GPH_MFPH PH11 setting for UART0_RXD*/
\r
1869 #define UART0_RXD_PF2 SYS_GPF_MFPL_PF2MFP_UART0_RXD /*!< GPF_MFPL PF2 setting for UART0_RXD*/
\r
1870 #define UART0_TXD_PA7 SYS_GPA_MFPL_PA7MFP_UART0_TXD /*!< GPA_MFPL PA7 setting for UART0_TXD*/
\r
1871 #define UART0_TXD_PD3 SYS_GPD_MFPL_PD3MFP_UART0_TXD /*!< GPD_MFPL PD3 setting for UART0_TXD*/
\r
1872 #define UART0_TXD_PF3 SYS_GPF_MFPL_PF3MFP_UART0_TXD /*!< GPF_MFPL PF3 setting for UART0_TXD*/
\r
1873 #define UART0_TXD_PC12 SYS_GPC_MFPH_PC12MFP_UART0_TXD /*!< GPC_MFPH PC12 setting for UART0_TXD*/
\r
1874 #define UART0_TXD_PH10 SYS_GPH_MFPH_PH10MFP_UART0_TXD /*!< GPH_MFPH PH10 setting for UART0_TXD*/
\r
1875 #define UART0_TXD_PA1 SYS_GPA_MFPL_PA1MFP_UART0_TXD /*!< GPA_MFPL PA1 setting for UART0_TXD*/
\r
1876 #define UART0_TXD_PB9 SYS_GPB_MFPH_PB9MFP_UART0_TXD /*!< GPB_MFPH PB9 setting for UART0_TXD*/
\r
1877 #define UART0_TXD_PB13 SYS_GPB_MFPH_PB13MFP_UART0_TXD /*!< GPB_MFPH PB13 setting for UART0_TXD*/
\r
1878 #define UART0_TXD_PA14 SYS_GPA_MFPH_PA14MFP_UART0_TXD /*!< GPA_MFPH PA14 setting for UART0_TXD*/
\r
1879 #define UART0_nCTS_PA5 SYS_GPA_MFPL_PA5MFP_UART0_nCTS /*!< GPA_MFPL PA5 setting for UART0_nCTS*/
\r
1880 #define UART0_nCTS_PB11 SYS_GPB_MFPH_PB11MFP_UART0_nCTS /*!< GPB_MFPH PB11 setting for UART0_nCTS*/
\r
1881 #define UART0_nCTS_PB15 SYS_GPB_MFPH_PB15MFP_UART0_nCTS /*!< GPB_MFPH PB15 setting for UART0_nCTS*/
\r
1882 #define UART0_nCTS_PC7 SYS_GPC_MFPL_PC7MFP_UART0_nCTS /*!< GPC_MFPL PC7 setting for UART0_nCTS*/
\r
1883 #define UART0_nRTS_PB14 SYS_GPB_MFPH_PB14MFP_UART0_nRTS /*!< GPB_MFPH PB14 setting for UART0_nRTS*/
\r
1884 #define UART0_nRTS_PB10 SYS_GPB_MFPH_PB10MFP_UART0_nRTS /*!< GPB_MFPH PB10 setting for UART0_nRTS*/
\r
1885 #define UART0_nRTS_PC6 SYS_GPC_MFPL_PC6MFP_UART0_nRTS /*!< GPC_MFPL PC6 setting for UART0_nRTS*/
\r
1886 #define UART0_nRTS_PA4 SYS_GPA_MFPL_PA4MFP_UART0_nRTS /*!< GPA_MFPL PA4 setting for UART0_nRTS*/
\r
1887 #define UART1_RXD_PF1 SYS_GPF_MFPL_PF1MFP_UART1_RXD /*!< GPF_MFPL PF1 setting for UART1_RXD*/
\r
1888 #define UART1_RXD_PA8 SYS_GPA_MFPH_PA8MFP_UART1_RXD /*!< GPA_MFPH PA8 setting for UART1_RXD*/
\r
1889 #define UART1_RXD_PA2 SYS_GPA_MFPL_PA2MFP_UART1_RXD /*!< GPA_MFPL PA2 setting for UART1_RXD*/
\r
1890 #define UART1_RXD_PB2 SYS_GPB_MFPL_PB2MFP_UART1_RXD /*!< GPB_MFPL PB2 setting for UART1_RXD*/
\r
1891 #define UART1_RXD_PB6 SYS_GPB_MFPL_PB6MFP_UART1_RXD /*!< GPB_MFPL PB6 setting for UART1_RXD*/
\r
1892 #define UART1_RXD_PD6 SYS_GPD_MFPL_PD6MFP_UART1_RXD /*!< GPD_MFPL PD6 setting for UART1_RXD*/
\r
1893 #define UART1_RXD_PD10 SYS_GPD_MFPH_PD10MFP_UART1_RXD /*!< GPD_MFPH PD10 setting for UART1_RXD*/
\r
1894 #define UART1_RXD_PH9 SYS_GPH_MFPH_PH9MFP_UART1_RXD /*!< GPH_MFPH PH9 setting for UART1_RXD*/
\r
1895 #define UART1_RXD_PC8 SYS_GPC_MFPH_PC8MFP_UART1_RXD /*!< GPC_MFPH PC8 setting for UART1_RXD*/
\r
1896 #define UART1_TXD_PB3 SYS_GPB_MFPL_PB3MFP_UART1_TXD /*!< GPB_MFPL PB3 setting for UART1_TXD*/
\r
1897 #define UART1_TXD_PA3 SYS_GPA_MFPL_PA3MFP_UART1_TXD /*!< GPA_MFPL PA3 setting for UART1_TXD*/
\r
1898 #define UART1_TXD_PE13 SYS_GPE_MFPH_PE13MFP_UART1_TXD /*!< GPE_MFPH PE13 setting for UART1_TXD*/
\r
1899 #define UART1_TXD_PA9 SYS_GPA_MFPH_PA9MFP_UART1_TXD /*!< GPA_MFPH PA9 setting for UART1_TXD*/
\r
1900 #define UART1_TXD_PF0 SYS_GPF_MFPL_PF0MFP_UART1_TXD /*!< GPF_MFPL PF0 setting for UART1_TXD*/
\r
1901 #define UART1_TXD_PD11 SYS_GPD_MFPH_PD11MFP_UART1_TXD /*!< GPD_MFPH PD11 setting for UART1_TXD*/
\r
1902 #define UART1_TXD_PD7 SYS_GPD_MFPL_PD7MFP_UART1_TXD /*!< GPD_MFPL PD7 setting for UART1_TXD*/
\r
1903 #define UART1_TXD_PB7 SYS_GPB_MFPL_PB7MFP_UART1_TXD /*!< GPB_MFPL PB7 setting for UART1_TXD*/
\r
1904 #define UART1_TXD_PH8 SYS_GPH_MFPH_PH8MFP_UART1_TXD /*!< GPH_MFPH PH8 setting for UART1_TXD*/
\r
1905 #define UART1_nCTS_PE11 SYS_GPE_MFPH_PE11MFP_UART1_nCTS /*!< GPE_MFPH PE11 setting for UART1_nCTS*/
\r
1906 #define UART1_nCTS_PB9 SYS_GPB_MFPH_PB9MFP_UART1_nCTS /*!< GPB_MFPH PB9 setting for UART1_nCTS*/
\r
1907 #define UART1_nCTS_PA1 SYS_GPA_MFPL_PA1MFP_UART1_nCTS /*!< GPA_MFPL PA1 setting for UART1_nCTS*/
\r
1908 #define UART1_nRTS_PA0 SYS_GPA_MFPL_PA0MFP_UART1_nRTS /*!< GPA_MFPL PA0 setting for UART1_nRTS*/
\r
1909 #define UART1_nRTS_PE12 SYS_GPE_MFPH_PE12MFP_UART1_nRTS /*!< GPE_MFPH PE12 setting for UART1_nRTS*/
\r
1910 #define UART1_nRTS_PB8 SYS_GPB_MFPH_PB8MFP_UART1_nRTS /*!< GPB_MFPH PB8 setting for UART1_nRTS*/
\r
1911 #define UART2_RXD_PB0 SYS_GPB_MFPL_PB0MFP_UART2_RXD /*!< GPB_MFPL PB0 setting for UART2_RXD*/
\r
1912 #define UART2_RXD_PE15 SYS_GPE_MFPH_PE15MFP_UART2_RXD /*!< GPE_MFPH PE15 setting for UART2_RXD*/
\r
1913 #define UART2_RXD_PD12 SYS_GPD_MFPH_PD12MFP_UART2_RXD /*!< GPD_MFPH PD12 setting for UART2_RXD*/
\r
1914 #define UART2_RXD_PF5 SYS_GPF_MFPL_PF5MFP_UART2_RXD /*!< GPF_MFPL PF5 setting for UART2_RXD*/
\r
1915 #define UART2_RXD_PC0 SYS_GPC_MFPL_PC0MFP_UART2_RXD /*!< GPC_MFPL PC0 setting for UART2_RXD*/
\r
1916 #define UART2_RXD_PC4 SYS_GPC_MFPL_PC4MFP_UART2_RXD /*!< GPC_MFPL PC4 setting for UART2_RXD*/
\r
1917 #define UART2_RXD_PE9 SYS_GPE_MFPH_PE9MFP_UART2_RXD /*!< GPE_MFPH PE9 setting for UART2_RXD*/
\r
1918 #define UART2_TXD_PE8 SYS_GPE_MFPH_PE8MFP_UART2_TXD /*!< GPE_MFPH PE8 setting for UART2_TXD*/
\r
1919 #define UART2_TXD_PF4 SYS_GPF_MFPL_PF4MFP_UART2_TXD /*!< GPF_MFPL PF4 setting for UART2_TXD*/
\r
1920 #define UART2_TXD_PC13 SYS_GPC_MFPH_PC13MFP_UART2_TXD /*!< GPC_MFPH PC13 setting for UART2_TXD*/
\r
1921 #define UART2_TXD_PC1 SYS_GPC_MFPL_PC1MFP_UART2_TXD /*!< GPC_MFPL PC1 setting for UART2_TXD*/
\r
1922 #define UART2_TXD_PE14 SYS_GPE_MFPH_PE14MFP_UART2_TXD /*!< GPE_MFPH PE14 setting for UART2_TXD*/
\r
1923 #define UART2_TXD_PC5 SYS_GPC_MFPL_PC5MFP_UART2_TXD /*!< GPC_MFPL PC5 setting for UART2_TXD*/
\r
1924 #define UART2_TXD_PB1 SYS_GPB_MFPL_PB1MFP_UART2_TXD /*!< GPB_MFPL PB1 setting for UART2_TXD*/
\r
1925 #define UART2_nCTS_PF5 SYS_GPF_MFPL_PF5MFP_UART2_nCTS /*!< GPF_MFPL PF5 setting for UART2_nCTS*/
\r
1926 #define UART2_nCTS_PD9 SYS_GPD_MFPH_PD9MFP_UART2_nCTS /*!< GPD_MFPH PD9 setting for UART2_nCTS*/
\r
1927 #define UART2_nCTS_PC2 SYS_GPC_MFPL_PC2MFP_UART2_nCTS /*!< GPC_MFPL PC2 setting for UART2_nCTS*/
\r
1928 #define UART2_nRTS_PF4 SYS_GPF_MFPL_PF4MFP_UART2_nRTS /*!< GPF_MFPL PF4 setting for UART2_nRTS*/
\r
1929 #define UART2_nRTS_PD8 SYS_GPD_MFPH_PD8MFP_UART2_nRTS /*!< GPD_MFPH PD8 setting for UART2_nRTS*/
\r
1930 #define UART2_nRTS_PC3 SYS_GPC_MFPL_PC3MFP_UART2_nRTS /*!< GPC_MFPL PC3 setting for UART2_nRTS*/
\r
1931 #define UART3_RXD_PD0 SYS_GPD_MFPL_PD0MFP_UART3_RXD /*!< GPD_MFPL PD0 setting for UART3_RXD*/
\r
1932 #define UART3_RXD_PE11 SYS_GPE_MFPH_PE11MFP_UART3_RXD /*!< GPE_MFPH PE11 setting for UART3_RXD*/
\r
1933 #define UART3_RXD_PC9 SYS_GPC_MFPH_PC9MFP_UART3_RXD /*!< GPC_MFPH PC9 setting for UART3_RXD*/
\r
1934 #define UART3_RXD_PE0 SYS_GPE_MFPL_PE0MFP_UART3_RXD /*!< GPE_MFPL PE0 setting for UART3_RXD*/
\r
1935 #define UART3_RXD_PC2 SYS_GPC_MFPL_PC2MFP_UART3_RXD /*!< GPC_MFPL PC2 setting for UART3_RXD*/
\r
1936 #define UART3_RXD_PB14 SYS_GPB_MFPH_PB14MFP_UART3_RXD /*!< GPB_MFPH PB14 setting for UART3_RXD*/
\r
1937 #define UART3_TXD_PD1 SYS_GPD_MFPL_PD1MFP_UART3_TXD /*!< GPD_MFPL PD1 setting for UART3_TXD*/
\r
1938 #define UART3_TXD_PC10 SYS_GPC_MFPH_PC10MFP_UART3_TXD /*!< GPC_MFPH PC10 setting for UART3_TXD*/
\r
1939 #define UART3_TXD_PB15 SYS_GPB_MFPH_PB15MFP_UART3_TXD /*!< GPB_MFPH PB15 setting for UART3_TXD*/
\r
1940 #define UART3_TXD_PC3 SYS_GPC_MFPL_PC3MFP_UART3_TXD /*!< GPC_MFPL PC3 setting for UART3_TXD*/
\r
1941 #define UART3_TXD_PE1 SYS_GPE_MFPL_PE1MFP_UART3_TXD /*!< GPE_MFPL PE1 setting for UART3_TXD*/
\r
1942 #define UART3_TXD_PE10 SYS_GPE_MFPH_PE10MFP_UART3_TXD /*!< GPE_MFPH PE10 setting for UART3_TXD*/
\r
1943 #define UART3_nCTS_PB12 SYS_GPB_MFPH_PB12MFP_UART3_nCTS /*!< GPB_MFPH PB12 setting for UART3_nCTS*/
\r
1944 #define UART3_nCTS_PH9 SYS_GPH_MFPH_PH9MFP_UART3_nCTS /*!< GPH_MFPH PH9 setting for UART3_nCTS*/
\r
1945 #define UART3_nCTS_PD2 SYS_GPD_MFPL_PD2MFP_UART3_nCTS /*!< GPD_MFPL PD2 setting for UART3_nCTS*/
\r
1946 #define UART3_nRTS_PB13 SYS_GPB_MFPH_PB13MFP_UART3_nRTS /*!< GPB_MFPH PB13 setting for UART3_nRTS*/
\r
1947 #define UART3_nRTS_PH8 SYS_GPH_MFPH_PH8MFP_UART3_nRTS /*!< GPH_MFPH PH8 setting for UART3_nRTS*/
\r
1948 #define UART3_nRTS_PD3 SYS_GPD_MFPL_PD3MFP_UART3_nRTS /*!< GPD_MFPL PD3 setting for UART3_nRTS*/
\r
1949 #define UART4_RXD_PA13 SYS_GPA_MFPH_PA13MFP_UART4_RXD /*!< GPA_MFPH PA13 setting for UART4_RXD*/
\r
1950 #define UART4_RXD_PC6 SYS_GPC_MFPL_PC6MFP_UART4_RXD /*!< GPC_MFPL PC6 setting for UART4_RXD*/
\r
1951 #define UART4_RXD_PC4 SYS_GPC_MFPL_PC4MFP_UART4_RXD /*!< GPC_MFPL PC4 setting for UART4_RXD*/
\r
1952 #define UART4_RXD_PB10 SYS_GPB_MFPH_PB10MFP_UART4_RXD /*!< GPB_MFPH PB10 setting for UART4_RXD*/
\r
1953 #define UART4_RXD_PH11 SYS_GPH_MFPH_PH11MFP_UART4_RXD /*!< GPH_MFPH PH11 setting for UART4_RXD*/
\r
1954 #define UART4_RXD_PA2 SYS_GPA_MFPL_PA2MFP_UART4_RXD /*!< GPA_MFPL PA2 setting for UART4_RXD*/
\r
1955 #define UART4_RXD_PF6 SYS_GPF_MFPL_PF6MFP_UART4_RXD /*!< GPF_MFPL PF6 setting for UART4_RXD*/
\r
1956 #define UART4_TXD_PH10 SYS_GPH_MFPH_PH10MFP_UART4_TXD /*!< GPH_MFPH PH10 setting for UART4_TXD*/
\r
1957 #define UART4_TXD_PA3 SYS_GPA_MFPL_PA3MFP_UART4_TXD /*!< GPA_MFPL PA3 setting for UART4_TXD*/
\r
1958 #define UART4_TXD_PA12 SYS_GPA_MFPH_PA12MFP_UART4_TXD /*!< GPA_MFPH PA12 setting for UART4_TXD*/
\r
1959 #define UART4_TXD_PC7 SYS_GPC_MFPL_PC7MFP_UART4_TXD /*!< GPC_MFPL PC7 setting for UART4_TXD*/
\r
1960 #define UART4_TXD_PB11 SYS_GPB_MFPH_PB11MFP_UART4_TXD /*!< GPB_MFPH PB11 setting for UART4_TXD*/
\r
1961 #define UART4_TXD_PF7 SYS_GPF_MFPL_PF7MFP_UART4_TXD /*!< GPF_MFPL PF7 setting for UART4_TXD*/
\r
1962 #define UART4_TXD_PC5 SYS_GPC_MFPL_PC5MFP_UART4_TXD /*!< GPC_MFPL PC5 setting for UART4_TXD*/
\r
1963 #define UART4_nCTS_PE1 SYS_GPE_MFPL_PE1MFP_UART4_nCTS /*!< GPE_MFPL PE1 setting for UART4_nCTS*/
\r
1964 #define UART4_nCTS_PC8 SYS_GPC_MFPH_PC8MFP_UART4_nCTS /*!< GPC_MFPH PC8 setting for UART4_nCTS*/
\r
1965 #define UART4_nRTS_PE0 SYS_GPE_MFPL_PE0MFP_UART4_nRTS /*!< GPE_MFPL PE0 setting for UART4_nRTS*/
\r
1966 #define UART4_nRTS_PE13 SYS_GPE_MFPH_PE13MFP_UART4_nRTS /*!< GPE_MFPH PE13 setting for UART4_nRTS*/
\r
1967 #define UART5_RXD_PB4 SYS_GPB_MFPL_PB4MFP_UART5_RXD /*!< GPB_MFPL PB4 setting for UART5_RXD*/
\r
1968 #define UART5_RXD_PA4 SYS_GPA_MFPL_PA4MFP_UART5_RXD /*!< GPA_MFPL PA4 setting for UART5_RXD*/
\r
1969 #define UART5_RXD_PE6 SYS_GPE_MFPL_PE6MFP_UART5_RXD /*!< GPE_MFPL PE6 setting for UART5_RXD*/
\r
1970 #define UART5_TXD_PB5 SYS_GPB_MFPL_PB5MFP_UART5_TXD /*!< GPB_MFPL PB5 setting for UART5_TXD*/
\r
1971 #define UART5_TXD_PE7 SYS_GPE_MFPL_PE7MFP_UART5_TXD /*!< GPE_MFPL PE7 setting for UART5_TXD*/
\r
1972 #define UART5_TXD_PA5 SYS_GPA_MFPL_PA5MFP_UART5_TXD /*!< GPA_MFPL PA5 setting for UART5_TXD*/
\r
1973 #define UART5_nCTS_PB2 SYS_GPB_MFPL_PB2MFP_UART5_nCTS /*!< GPB_MFPL PB2 setting for UART5_nCTS*/
\r
1974 #define UART5_nRTS_PB3 SYS_GPB_MFPL_PB3MFP_UART5_nRTS /*!< GPB_MFPL PB3 setting for UART5_nRTS*/
\r
1975 #define USB_D_P_PA14 SYS_GPA_MFPH_PA14MFP_USB_D_P /*!< GPA_MFPH PA14 setting for USB_D_P*/
\r
1976 #define USB_D_N_PA13 SYS_GPA_MFPH_PA13MFP_USB_D_N /*!< GPA_MFPH PA13 setting for USB_D_N*/
\r
1977 #define USB_OTG_ID_PA15 SYS_GPA_MFPH_PA15MFP_USB_OTG_ID /*!< GPA_MFPH PA15 setting for USB_OTG_ID*/
\r
1978 #define USB_VBUS_PA12 SYS_GPA_MFPH_PA12MFP_USB_VBUS /*!< GPA_MFPH PA12 setting for USB_VBUS*/
\r
1979 #define USB_VBUS_EN_PB6 SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN /*!< GPB_MFPL PB6 setting for USB_VBUS_EN*/
\r
1980 #define USB_VBUS_EN_PB15 SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN /*!< GPB_MFPH PB15 setting for USB_VBUS_EN*/
\r
1981 #define USB_VBUS_ST_PB14 SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST /*!< GPB_MFPH PB14 setting for USB_VBUS_ST*/
\r
1982 #define USB_VBUS_ST_PB7 SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST /*!< GPB_MFPL PB7 setting for USB_VBUS_ST*/
\r
1983 #define USB_VBUS_ST_PD4 SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST /*!< GPD_MFPL PD4 setting for USB_VBUS_ST*/
\r
1984 #define USCI0_CLK_PD0 SYS_GPD_MFPL_PD0MFP_USCI0_CLK /*!< GPD_MFPL PD0 setting for USCI0_CLK*/
\r
1985 #define USCI0_CLK_PA11 SYS_GPA_MFPH_PA11MFP_USCI0_CLK /*!< GPA_MFPH PA11 setting for USCI0_CLK*/
\r
1986 #define USCI0_CLK_PE2 SYS_GPE_MFPL_PE2MFP_USCI0_CLK /*!< GPE_MFPL PE2 setting for USCI0_CLK*/
\r
1987 #define USCI0_CLK_PB12 SYS_GPB_MFPH_PB12MFP_USCI0_CLK /*!< GPB_MFPH PB12 setting for USCI0_CLK*/
\r
1988 #define USCI0_CTL0_PD4 SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 /*!< GPD_MFPL PD4 setting for USCI0_CTL0*/
\r
1989 #define USCI0_CTL0_PE6 SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 /*!< GPE_MFPL PE6 setting for USCI0_CTL0*/
\r
1990 #define USCI0_CTL0_PC13 SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 /*!< GPC_MFPH PC13 setting for USCI0_CTL0*/
\r
1991 #define USCI0_CTL0_PD14 SYS_GPD_MFPH_PD14MFP_USCI0_CTL0 /*!< GPD_MFPH PD14 setting for USCI0_CTL0*/
\r
1992 #define USCI0_CTL1_PD3 SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 /*!< GPD_MFPL PD3 setting for USCI0_CTL1*/
\r
1993 #define USCI0_CTL1_PE5 SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 /*!< GPE_MFPL PE5 setting for USCI0_CTL1*/
\r
1994 #define USCI0_CTL1_PB15 SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 /*!< GPB_MFPH PB15 setting for USCI0_CTL1*/
\r
1995 #define USCI0_CTL1_PA8 SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 /*!< GPA_MFPH PA8 setting for USCI0_CTL1*/
\r
1996 #define USCI0_DAT0_PE3 SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 /*!< GPE_MFPL PE3 setting for USCI0_DAT0*/
\r
1997 #define USCI0_DAT0_PB13 SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 /*!< GPB_MFPH PB13 setting for USCI0_DAT0*/
\r
1998 #define USCI0_DAT0_PD1 SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 /*!< GPD_MFPL PD1 setting for USCI0_DAT0*/
\r
1999 #define USCI0_DAT0_PA10 SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 /*!< GPA_MFPH PA10 setting for USCI0_DAT0*/
\r
2000 #define USCI0_DAT1_PE4 SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 /*!< GPE_MFPL PE4 setting for USCI0_DAT1*/
\r
2001 #define USCI0_DAT1_PD2 SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 /*!< GPD_MFPL PD2 setting for USCI0_DAT1*/
\r
2002 #define USCI0_DAT1_PB14 SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 /*!< GPB_MFPH PB14 setting for USCI0_DAT1*/
\r
2003 #define USCI0_DAT1_PA9 SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 /*!< GPA_MFPH PA9 setting for USCI0_DAT1*/
\r
2004 #define USCI1_CLK_PE12 SYS_GPE_MFPH_PE12MFP_USCI1_CLK /*!< GPE_MFPH PE12 setting for USCI1_CLK*/
\r
2005 #define USCI1_CLK_PD7 SYS_GPD_MFPL_PD7MFP_USCI1_CLK /*!< GPD_MFPL PD7 setting for USCI1_CLK*/
\r
2006 #define USCI1_CLK_PB8 SYS_GPB_MFPH_PB8MFP_USCI1_CLK /*!< GPB_MFPH PB8 setting for USCI1_CLK*/
\r
2007 #define USCI1_CLK_PB1 SYS_GPB_MFPL_PB1MFP_USCI1_CLK /*!< GPB_MFPL PB1 setting for USCI1_CLK*/
\r
2008 #define USCI1_CTL0_PB10 SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 /*!< GPB_MFPH PB10 setting for USCI1_CTL0*/
\r
2009 #define USCI1_CTL0_PB5 SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 /*!< GPB_MFPL PB5 setting for USCI1_CTL0*/
\r
2010 #define USCI1_CTL0_PE9 SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 /*!< GPE_MFPH PE9 setting for USCI1_CTL0*/
\r
2011 #define USCI1_CTL0_PD3 SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 /*!< GPD_MFPL PD3 setting for USCI1_CTL0*/
\r
2012 #define USCI1_CTL1_PD4 SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 /*!< GPD_MFPL PD4 setting for USCI1_CTL1*/
\r
2013 #define USCI1_CTL1_PE8 SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 /*!< GPE_MFPH PE8 setting for USCI1_CTL1*/
\r
2014 #define USCI1_CTL1_PB9 SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 /*!< GPB_MFPH PB9 setting for USCI1_CTL1*/
\r
2015 #define USCI1_CTL1_PB4 SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 /*!< GPB_MFPL PB4 setting for USCI1_CTL1*/
\r
2016 #define USCI1_DAT0_PB2 SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 /*!< GPB_MFPL PB2 setting for USCI1_DAT0*/
\r
2017 #define USCI1_DAT0_PB7 SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 /*!< GPB_MFPL PB7 setting for USCI1_DAT0*/
\r
2018 #define USCI1_DAT0_PE10 SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 /*!< GPE_MFPH PE10 setting for USCI1_DAT0*/
\r
2019 #define USCI1_DAT0_PD5 SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 /*!< GPD_MFPL PD5 setting for USCI1_DAT0*/
\r
2020 #define USCI1_DAT1_PD6 SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 /*!< GPD_MFPL PD6 setting for USCI1_DAT1*/
\r
2021 #define USCI1_DAT1_PB3 SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 /*!< GPB_MFPL PB3 setting for USCI1_DAT1*/
\r
2022 #define USCI1_DAT1_PE11 SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 /*!< GPE_MFPH PE11 setting for USCI1_DAT1*/
\r
2023 #define USCI1_DAT1_PB6 SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 /*!< GPB_MFPL PB6 setting for USCI1_DAT1*/
\r
2024 #define X32_IN_PF5 SYS_GPF_MFPL_PF5MFP_X32_IN /*!< GPF_MFPL PF5 setting for X32_IN*/
\r
2025 #define X32_OUT_PF4 SYS_GPF_MFPL_PF4MFP_X32_OUT /*!< GPF_MFPL PF4 setting for X32_OUT*/
\r
2026 #define XT1_IN_PF3 SYS_GPF_MFPL_PF3MFP_XT1_IN /*!< GPF_MFPL PF3 setting for XT1_IN*/
\r
2027 #define XT1_OUT_PF2 SYS_GPF_MFPL_PF2MFP_XT1_OUT /*!< GPF_MFPL PF2 setting for XT1_OUT*/
\r
2029 /*---------------------------------------------------------------------------------------------------------*/
\r
2030 /* Multi-Function setting mask constant definitions abbreviation. */
\r
2031 /*---------------------------------------------------------------------------------------------------------*/
\r
2034 #define ACMP0_N_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! ACMP0_N PB3 MFP Mask */
\r
2035 #define ACMP0_O_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! ACMP0_O PB7 MFP Mask */
\r
2036 #define ACMP0_O_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! ACMP0_O PC1 MFP Mask */
\r
2037 #define ACMP0_O_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! ACMP0_O PC12 MFP Mask */
\r
2038 #define ACMP0_P0_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! ACMP0_P0 PA11 MFP Mask */
\r
2039 #define ACMP0_P1_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! ACMP0_P1 PB2 MFP Mask */
\r
2040 #define ACMP0_P2_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! ACMP0_P2 PB12 MFP Mask */
\r
2041 #define ACMP0_P3_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! ACMP0_P3 PB13 MFP Mask */
\r
2042 #define ACMP0_WLAT_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! ACMP0_WLAT PA7 MFP Mask */
\r
2043 #define ACMP1_N_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! ACMP1_N PB5 MFP Mask */
\r
2044 #define ACMP1_O_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! ACMP1_O PB6 MFP Mask */
\r
2045 #define ACMP1_O_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! ACMP1_O PC11 MFP Mask */
\r
2046 #define ACMP1_O_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! ACMP1_O PC0 MFP Mask */
\r
2047 #define ACMP1_P0_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! ACMP1_P0 PA10 MFP Mask */
\r
2048 #define ACMP1_P1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! ACMP1_P1 PB4 MFP Mask */
\r
2049 #define ACMP1_P2_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! ACMP1_P2 PB12 MFP Mask */
\r
2050 #define ACMP1_P3_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! ACMP1_P3 PB13 MFP Mask */
\r
2051 #define ACMP1_WLAT_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! ACMP1_WLAT PA6 MFP Mask */
\r
2052 #define BPWM0_CH0_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! BPWM0_CH0 PA0 MFP Mask */
\r
2053 #define BPWM0_CH0_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! BPWM0_CH0 PA11 MFP Mask */
\r
2054 #define BPWM0_CH0_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! BPWM0_CH0 PE2 MFP Mask */
\r
2055 #define BPWM0_CH0_PG14_Msk SYS_GPG_MFPH_PG14MFP_Msk /*<! BPWM0_CH0 PG14 MFP Mask */
\r
2056 #define BPWM0_CH1_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! BPWM0_CH1 PA1 MFP Mask */
\r
2057 #define BPWM0_CH1_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! BPWM0_CH1 PE3 MFP Mask */
\r
2058 #define BPWM0_CH1_PG13_Msk SYS_GPG_MFPH_PG13MFP_Msk /*<! BPWM0_CH1 PG13 MFP Mask */
\r
2059 #define BPWM0_CH1_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! BPWM0_CH1 PA10 MFP Mask */
\r
2060 #define BPWM0_CH2_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! BPWM0_CH2 PE4 MFP Mask */
\r
2061 #define BPWM0_CH2_PG12_Msk SYS_GPG_MFPH_PG12MFP_Msk /*<! BPWM0_CH2 PG12 MFP Mask */
\r
2062 #define BPWM0_CH2_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! BPWM0_CH2 PA2 MFP Mask */
\r
2063 #define BPWM0_CH2_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! BPWM0_CH2 PA9 MFP Mask */
\r
2064 #define BPWM0_CH3_PG11_Msk SYS_GPG_MFPH_PG11MFP_Msk /*<! BPWM0_CH3 PG11 MFP Mask */
\r
2065 #define BPWM0_CH3_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! BPWM0_CH3 PA3 MFP Mask */
\r
2066 #define BPWM0_CH3_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! BPWM0_CH3 PA8 MFP Mask */
\r
2067 #define BPWM0_CH3_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! BPWM0_CH3 PE5 MFP Mask */
\r
2068 #define BPWM0_CH4_PG10_Msk SYS_GPG_MFPH_PG10MFP_Msk /*<! BPWM0_CH4 PG10 MFP Mask */
\r
2069 #define BPWM0_CH4_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! BPWM0_CH4 PA4 MFP Mask */
\r
2070 #define BPWM0_CH4_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! BPWM0_CH4 PC13 MFP Mask */
\r
2071 #define BPWM0_CH4_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! BPWM0_CH4 PE6 MFP Mask */
\r
2072 #define BPWM0_CH4_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! BPWM0_CH4 PF5 MFP Mask */
\r
2073 #define BPWM0_CH5_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! BPWM0_CH5 PA5 MFP Mask */
\r
2074 #define BPWM0_CH5_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! BPWM0_CH5 PE7 MFP Mask */
\r
2075 #define BPWM0_CH5_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! BPWM0_CH5 PF4 MFP Mask */
\r
2076 #define BPWM0_CH5_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! BPWM0_CH5 PD12 MFP Mask */
\r
2077 #define BPWM0_CH5_PG9_Msk SYS_GPG_MFPH_PG9MFP_Msk /*<! BPWM0_CH5 PG9 MFP Mask */
\r
2078 #define BPWM1_CH0_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! BPWM1_CH0 PB11 MFP Mask */
\r
2079 #define BPWM1_CH0_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! BPWM1_CH0 PC7 MFP Mask */
\r
2080 #define BPWM1_CH0_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! BPWM1_CH0 PF0 MFP Mask */
\r
2081 #define BPWM1_CH0_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! BPWM1_CH0 PF3 MFP Mask */
\r
2082 #define BPWM1_CH1_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! BPWM1_CH1 PC6 MFP Mask */
\r
2083 #define BPWM1_CH1_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! BPWM1_CH1 PF1 MFP Mask */
\r
2084 #define BPWM1_CH1_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! BPWM1_CH1 PF2 MFP Mask */
\r
2085 #define BPWM1_CH1_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! BPWM1_CH1 PB10 MFP Mask */
\r
2086 #define BPWM1_CH2_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! BPWM1_CH2 PB9 MFP Mask */
\r
2087 #define BPWM1_CH2_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! BPWM1_CH2 PA7 MFP Mask */
\r
2088 #define BPWM1_CH2_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! BPWM1_CH2 PA12 MFP Mask */
\r
2089 #define BPWM1_CH3_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! BPWM1_CH3 PA6 MFP Mask */
\r
2090 #define BPWM1_CH3_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! BPWM1_CH3 PA13 MFP Mask */
\r
2091 #define BPWM1_CH3_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! BPWM1_CH3 PB8 MFP Mask */
\r
2092 #define BPWM1_CH4_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! BPWM1_CH4 PA14 MFP Mask */
\r
2093 #define BPWM1_CH4_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! BPWM1_CH4 PC8 MFP Mask */
\r
2094 #define BPWM1_CH4_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! BPWM1_CH4 PB7 MFP Mask */
\r
2095 #define BPWM1_CH5_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! BPWM1_CH5 PA15 MFP Mask */
\r
2096 #define BPWM1_CH5_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! BPWM1_CH5 PB6 MFP Mask */
\r
2097 #define BPWM1_CH5_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! BPWM1_CH5 PE13 MFP Mask */
\r
2098 #define CAN0_RXD_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! CAN0_RXD PA13 MFP Mask */
\r
2099 #define CAN0_RXD_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! CAN0_RXD PD10 MFP Mask */
\r
2100 #define CAN0_RXD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! CAN0_RXD PA4 MFP Mask */
\r
2101 #define CAN0_RXD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! CAN0_RXD PC4 MFP Mask */
\r
2102 #define CAN0_RXD_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! CAN0_RXD PB10 MFP Mask */
\r
2103 #define CAN0_RXD_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! CAN0_RXD PE15 MFP Mask */
\r
2104 #define CAN0_TXD_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! CAN0_TXD PD11 MFP Mask */
\r
2105 #define CAN0_TXD_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! CAN0_TXD PC5 MFP Mask */
\r
2106 #define CAN0_TXD_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! CAN0_TXD PB11 MFP Mask */
\r
2107 #define CAN0_TXD_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! CAN0_TXD PA12 MFP Mask */
\r
2108 #define CAN0_TXD_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! CAN0_TXD PE14 MFP Mask */
\r
2109 #define CAN0_TXD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! CAN0_TXD PA5 MFP Mask */
\r
2110 #define CLKO_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! CLKO PC13 MFP Mask */
\r
2111 #define CLKO_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! CLKO PB14 MFP Mask */
\r
2112 #define CLKO_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! CLKO PD12 MFP Mask */
\r
2113 #define CLKO_PG15_Msk SYS_GPG_MFPH_PG15MFP_Msk /*<! CLKO PG15 MFP Mask */
\r
2114 #define DAC0_OUT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! DAC0_OUT PB12 MFP Mask */
\r
2115 #define DAC0_ST_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! DAC0_ST PA10 MFP Mask */
\r
2116 #define DAC0_ST_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! DAC0_ST PA0 MFP Mask */
\r
2117 #define DAC1_OUT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! DAC1_OUT PB13 MFP Mask */
\r
2118 #define DAC1_ST_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! DAC1_ST PA1 MFP Mask */
\r
2119 #define DAC1_ST_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! DAC1_ST PA11 MFP Mask */
\r
2120 #define EADC0_CH0_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EADC0_CH0 PB0 MFP Mask */
\r
2121 #define EADC0_CH1_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EADC0_CH1 PB1 MFP Mask */
\r
2122 #define EADC0_CH10_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! EADC0_CH10 PB10 MFP Mask */
\r
2123 #define EADC0_CH11_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! EADC0_CH11 PB11 MFP Mask */
\r
2124 #define EADC0_CH12_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! EADC0_CH12 PB12 MFP Mask */
\r
2125 #define EADC0_CH13_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! EADC0_CH13 PB13 MFP Mask */
\r
2126 #define EADC0_CH14_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EADC0_CH14 PB14 MFP Mask */
\r
2127 #define EADC0_CH15_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! EADC0_CH15 PB15 MFP Mask */
\r
2128 #define EADC0_CH2_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! EADC0_CH2 PB2 MFP Mask */
\r
2129 #define EADC0_CH3_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! EADC0_CH3 PB3 MFP Mask */
\r
2130 #define EADC0_CH4_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! EADC0_CH4 PB4 MFP Mask */
\r
2131 #define EADC0_CH5_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! EADC0_CH5 PB5 MFP Mask */
\r
2132 #define EADC0_CH6_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EADC0_CH6 PB6 MFP Mask */
\r
2133 #define EADC0_CH7_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EADC0_CH7 PB7 MFP Mask */
\r
2134 #define EADC0_CH8_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! EADC0_CH8 PB8 MFP Mask */
\r
2135 #define EADC0_CH9_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! EADC0_CH9 PB9 MFP Mask */
\r
2136 #define EADC0_ST_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! EADC0_ST PD12 MFP Mask */
\r
2137 #define EADC0_ST_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! EADC0_ST PF5 MFP Mask */
\r
2138 #define EADC0_ST_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! EADC0_ST PC13 MFP Mask */
\r
2139 #define EADC0_ST_PG15_Msk SYS_GPG_MFPH_PG15MFP_Msk /*<! EADC0_ST PG15 MFP Mask */
\r
2140 #define EBI_AD0_PG9_Msk SYS_GPG_MFPH_PG9MFP_Msk /*<! EBI_AD0 PG9 MFP Mask */
\r
2141 #define EBI_AD0_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! EBI_AD0 PC0 MFP Mask */
\r
2142 #define EBI_AD1_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! EBI_AD1 PC1 MFP Mask */
\r
2143 #define EBI_AD1_PG10_Msk SYS_GPG_MFPH_PG10MFP_Msk /*<! EBI_AD1 PG10 MFP Mask */
\r
2144 #define EBI_AD10_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! EBI_AD10 PE1 MFP Mask */
\r
2145 #define EBI_AD10_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! EBI_AD10 PD3 MFP Mask */
\r
2146 #define EBI_AD10_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! EBI_AD10 PD13 MFP Mask */
\r
2147 #define EBI_AD11_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! EBI_AD11 PE0 MFP Mask */
\r
2148 #define EBI_AD11_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! EBI_AD11 PD2 MFP Mask */
\r
2149 #define EBI_AD12_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! EBI_AD12 PD1 MFP Mask */
\r
2150 #define EBI_AD12_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! EBI_AD12 PB15 MFP Mask */
\r
2151 #define EBI_AD12_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! EBI_AD12 PH8 MFP Mask */
\r
2152 #define EBI_AD13_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! EBI_AD13 PD0 MFP Mask */
\r
2153 #define EBI_AD13_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EBI_AD13 PB14 MFP Mask */
\r
2154 #define EBI_AD13_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! EBI_AD13 PH9 MFP Mask */
\r
2155 #define EBI_AD14_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! EBI_AD14 PB13 MFP Mask */
\r
2156 #define EBI_AD14_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! EBI_AD14 PH10 MFP Mask */
\r
2157 #define EBI_AD15_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! EBI_AD15 PB12 MFP Mask */
\r
2158 #define EBI_AD15_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! EBI_AD15 PH11 MFP Mask */
\r
2159 #define EBI_AD2_PG11_Msk SYS_GPG_MFPH_PG11MFP_Msk /*<! EBI_AD2 PG11 MFP Mask */
\r
2160 #define EBI_AD2_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! EBI_AD2 PC2 MFP Mask */
\r
2161 #define EBI_AD3_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! EBI_AD3 PC3 MFP Mask */
\r
2162 #define EBI_AD3_PG12_Msk SYS_GPG_MFPH_PG12MFP_Msk /*<! EBI_AD3 PG12 MFP Mask */
\r
2163 #define EBI_AD4_PG13_Msk SYS_GPG_MFPH_PG13MFP_Msk /*<! EBI_AD4 PG13 MFP Mask */
\r
2164 #define EBI_AD4_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! EBI_AD4 PC4 MFP Mask */
\r
2165 #define EBI_AD5_PG14_Msk SYS_GPG_MFPH_PG14MFP_Msk /*<! EBI_AD5 PG14 MFP Mask */
\r
2166 #define EBI_AD5_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! EBI_AD5 PC5 MFP Mask */
\r
2167 #define EBI_AD6_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! EBI_AD6 PD8 MFP Mask */
\r
2168 #define EBI_AD6_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! EBI_AD6 PA6 MFP Mask */
\r
2169 #define EBI_AD7_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! EBI_AD7 PA7 MFP Mask */
\r
2170 #define EBI_AD7_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! EBI_AD7 PD9 MFP Mask */
\r
2171 #define EBI_AD8_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! EBI_AD8 PC6 MFP Mask */
\r
2172 #define EBI_AD8_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! EBI_AD8 PE14 MFP Mask */
\r
2173 #define EBI_AD9_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! EBI_AD9 PE15 MFP Mask */
\r
2174 #define EBI_AD9_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! EBI_AD9 PC7 MFP Mask */
\r
2175 #define EBI_ADR0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! EBI_ADR0 PB5 MFP Mask */
\r
2176 #define EBI_ADR0_PH7_Msk SYS_GPH_MFPL_PH7MFP_Msk /*<! EBI_ADR0 PH7 MFP Mask */
\r
2177 #define EBI_ADR1_PH6_Msk SYS_GPH_MFPL_PH6MFP_Msk /*<! EBI_ADR1 PH6 MFP Mask */
\r
2178 #define EBI_ADR1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! EBI_ADR1 PB4 MFP Mask */
\r
2179 #define EBI_ADR10_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! EBI_ADR10 PE8 MFP Mask */
\r
2180 #define EBI_ADR10_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! EBI_ADR10 PC13 MFP Mask */
\r
2181 #define EBI_ADR11_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! EBI_ADR11 PG2 MFP Mask */
\r
2182 #define EBI_ADR11_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! EBI_ADR11 PE9 MFP Mask */
\r
2183 #define EBI_ADR12_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! EBI_ADR12 PG3 MFP Mask */
\r
2184 #define EBI_ADR12_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! EBI_ADR12 PE10 MFP Mask */
\r
2185 #define EBI_ADR13_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! EBI_ADR13 PG4 MFP Mask */
\r
2186 #define EBI_ADR13_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! EBI_ADR13 PE11 MFP Mask */
\r
2187 #define EBI_ADR14_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! EBI_ADR14 PE12 MFP Mask */
\r
2188 #define EBI_ADR14_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! EBI_ADR14 PF11 MFP Mask */
\r
2189 #define EBI_ADR15_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! EBI_ADR15 PF10 MFP Mask */
\r
2190 #define EBI_ADR15_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! EBI_ADR15 PE13 MFP Mask */
\r
2191 #define EBI_ADR16_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! EBI_ADR16 PB11 MFP Mask */
\r
2192 #define EBI_ADR16_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! EBI_ADR16 PF9 MFP Mask */
\r
2193 #define EBI_ADR16_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! EBI_ADR16 PC8 MFP Mask */
\r
2194 #define EBI_ADR17_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! EBI_ADR17 PF8 MFP Mask */
\r
2195 #define EBI_ADR17_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! EBI_ADR17 PB10 MFP Mask */
\r
2196 #define EBI_ADR18_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! EBI_ADR18 PB9 MFP Mask */
\r
2197 #define EBI_ADR18_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! EBI_ADR18 PF7 MFP Mask */
\r
2198 #define EBI_ADR19_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! EBI_ADR19 PF6 MFP Mask */
\r
2199 #define EBI_ADR19_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! EBI_ADR19 PB8 MFP Mask */
\r
2200 #define EBI_ADR2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! EBI_ADR2 PB3 MFP Mask */
\r
2201 #define EBI_ADR2_PH5_Msk SYS_GPH_MFPL_PH5MFP_Msk /*<! EBI_ADR2 PH5 MFP Mask */
\r
2202 #define EBI_ADR3_PH4_Msk SYS_GPH_MFPL_PH4MFP_Msk /*<! EBI_ADR3 PH4 MFP Mask */
\r
2203 #define EBI_ADR3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! EBI_ADR3 PB2 MFP Mask */
\r
2204 #define EBI_ADR4_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! EBI_ADR4 PC12 MFP Mask */
\r
2205 #define EBI_ADR5_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! EBI_ADR5 PC11 MFP Mask */
\r
2206 #define EBI_ADR6_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! EBI_ADR6 PC10 MFP Mask */
\r
2207 #define EBI_ADR7_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! EBI_ADR7 PC9 MFP Mask */
\r
2208 #define EBI_ADR8_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EBI_ADR8 PB1 MFP Mask */
\r
2209 #define EBI_ADR9_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EBI_ADR9 PB0 MFP Mask */
\r
2210 #define EBI_ALE_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! EBI_ALE PA8 MFP Mask */
\r
2211 #define EBI_ALE_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! EBI_ALE PE2 MFP Mask */
\r
2212 #define EBI_MCLK_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! EBI_MCLK PE3 MFP Mask */
\r
2213 #define EBI_MCLK_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! EBI_MCLK PA9 MFP Mask */
\r
2214 #define EBI_nCS0_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EBI_nCS0 PB7 MFP Mask */
\r
2215 #define EBI_nCS0_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! EBI_nCS0 PF6 MFP Mask */
\r
2216 #define EBI_nCS0_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! EBI_nCS0 PD12 MFP Mask */
\r
2217 #define EBI_nCS0_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! EBI_nCS0 PD14 MFP Mask */
\r
2218 #define EBI_nCS0_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! EBI_nCS0 PF3 MFP Mask */
\r
2219 #define EBI_nCS1_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! EBI_nCS1 PF2 MFP Mask */
\r
2220 #define EBI_nCS1_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! EBI_nCS1 PD11 MFP Mask */
\r
2221 #define EBI_nCS1_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EBI_nCS1 PB6 MFP Mask */
\r
2222 #define EBI_nCS2_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! EBI_nCS2 PD10 MFP Mask */
\r
2223 #define EBI_nRD_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! EBI_nRD PA11 MFP Mask */
\r
2224 #define EBI_nRD_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! EBI_nRD PE5 MFP Mask */
\r
2225 #define EBI_nWR_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! EBI_nWR PA10 MFP Mask */
\r
2226 #define EBI_nWR_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! EBI_nWR PE4 MFP Mask */
\r
2227 #define EBI_nWRH_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EBI_nWRH PB6 MFP Mask */
\r
2228 #define EBI_nWRL_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EBI_nWRL PB7 MFP Mask */
\r
2229 #define ECAP0_IC0_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! ECAP0_IC0 PA10 MFP Mask */
\r
2230 #define ECAP0_IC0_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! ECAP0_IC0 PE8 MFP Mask */
\r
2231 #define ECAP0_IC1_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! ECAP0_IC1 PE9 MFP Mask */
\r
2232 #define ECAP0_IC1_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! ECAP0_IC1 PA9 MFP Mask */
\r
2233 #define ECAP0_IC2_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! ECAP0_IC2 PA8 MFP Mask */
\r
2234 #define ECAP0_IC2_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! ECAP0_IC2 PE10 MFP Mask */
\r
2235 #define ECAP1_IC0_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! ECAP1_IC0 PC10 MFP Mask */
\r
2236 #define ECAP1_IC0_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! ECAP1_IC0 PE13 MFP Mask */
\r
2237 #define ECAP1_IC1_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! ECAP1_IC1 PE12 MFP Mask */
\r
2238 #define ECAP1_IC1_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! ECAP1_IC1 PC11 MFP Mask */
\r
2239 #define ECAP1_IC2_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! ECAP1_IC2 PE11 MFP Mask */
\r
2240 #define ECAP1_IC2_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! ECAP1_IC2 PC12 MFP Mask */
\r
2241 #define I2C0_SCL_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! I2C0_SCL PB5 MFP Mask */
\r
2242 #define I2C0_SCL_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! I2C0_SCL PC1 MFP Mask */
\r
2243 #define I2C0_SCL_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! I2C0_SCL PF3 MFP Mask */
\r
2244 #define I2C0_SCL_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! I2C0_SCL PE13 MFP Mask */
\r
2245 #define I2C0_SCL_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! I2C0_SCL PD7 MFP Mask */
\r
2246 #define I2C0_SCL_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! I2C0_SCL PA5 MFP Mask */
\r
2247 #define I2C0_SCL_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! I2C0_SCL PC12 MFP Mask */
\r
2248 #define I2C0_SDA_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! I2C0_SDA PB4 MFP Mask */
\r
2249 #define I2C0_SDA_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! I2C0_SDA PC8 MFP Mask */
\r
2250 #define I2C0_SDA_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! I2C0_SDA PC0 MFP Mask */
\r
2251 #define I2C0_SDA_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! I2C0_SDA PD6 MFP Mask */
\r
2252 #define I2C0_SDA_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! I2C0_SDA PC11 MFP Mask */
\r
2253 #define I2C0_SDA_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! I2C0_SDA PA4 MFP Mask */
\r
2254 #define I2C0_SDA_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! I2C0_SDA PF2 MFP Mask */
\r
2255 #define I2C0_SMBAL_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! I2C0_SMBAL PG2 MFP Mask */
\r
2256 #define I2C0_SMBAL_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! I2C0_SMBAL PC3 MFP Mask */
\r
2257 #define I2C0_SMBSUS_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! I2C0_SMBSUS PC2 MFP Mask */
\r
2258 #define I2C0_SMBSUS_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! I2C0_SMBSUS PG3 MFP Mask */
\r
2259 #define I2C1_SCL_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! I2C1_SCL PA3 MFP Mask */
\r
2260 #define I2C1_SCL_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! I2C1_SCL PG2 MFP Mask */
\r
2261 #define I2C1_SCL_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! I2C1_SCL PB1 MFP Mask */
\r
2262 #define I2C1_SCL_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! I2C1_SCL PB11 MFP Mask */
\r
2263 #define I2C1_SCL_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! I2C1_SCL PD5 MFP Mask */
\r
2264 #define I2C1_SCL_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! I2C1_SCL PA12 MFP Mask */
\r
2265 #define I2C1_SCL_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! I2C1_SCL PC5 MFP Mask */
\r
2266 #define I2C1_SCL_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! I2C1_SCL PA7 MFP Mask */
\r
2267 #define I2C1_SCL_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! I2C1_SCL PF0 MFP Mask */
\r
2268 #define I2C1_SCL_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! I2C1_SCL PE1 MFP Mask */
\r
2269 #define I2C1_SDA_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! I2C1_SDA PB0 MFP Mask */
\r
2270 #define I2C1_SDA_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! I2C1_SDA PA6 MFP Mask */
\r
2271 #define I2C1_SDA_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! I2C1_SDA PA13 MFP Mask */
\r
2272 #define I2C1_SDA_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! I2C1_SDA PG3 MFP Mask */
\r
2273 #define I2C1_SDA_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! I2C1_SDA PE0 MFP Mask */
\r
2274 #define I2C1_SDA_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! I2C1_SDA PC4 MFP Mask */
\r
2275 #define I2C1_SDA_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! I2C1_SDA PA2 MFP Mask */
\r
2276 #define I2C1_SDA_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! I2C1_SDA PB10 MFP Mask */
\r
2277 #define I2C1_SDA_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! I2C1_SDA PF1 MFP Mask */
\r
2278 #define I2C1_SDA_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! I2C1_SDA PD4 MFP Mask */
\r
2279 #define I2C1_SMBAL_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! I2C1_SMBAL PB9 MFP Mask */
\r
2280 #define I2C1_SMBAL_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! I2C1_SMBAL PC7 MFP Mask */
\r
2281 #define I2C1_SMBAL_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! I2C1_SMBAL PH8 MFP Mask */
\r
2282 #define I2C1_SMBSUS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! I2C1_SMBSUS PH9 MFP Mask */
\r
2283 #define I2C1_SMBSUS_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! I2C1_SMBSUS PC6 MFP Mask */
\r
2284 #define I2C1_SMBSUS_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! I2C1_SMBSUS PB8 MFP Mask */
\r
2285 #define I2C2_SCL_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! I2C2_SCL PB13 MFP Mask */
\r
2286 #define I2C2_SCL_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! I2C2_SCL PA11 MFP Mask */
\r
2287 #define I2C2_SCL_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! I2C2_SCL PH8 MFP Mask */
\r
2288 #define I2C2_SCL_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! I2C2_SCL PD9 MFP Mask */
\r
2289 #define I2C2_SCL_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! I2C2_SCL PD1 MFP Mask */
\r
2290 #define I2C2_SCL_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! I2C2_SCL PA14 MFP Mask */
\r
2291 #define I2C2_SCL_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! I2C2_SCL PA1 MFP Mask */
\r
2292 #define I2C2_SDA_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! I2C2_SDA PA0 MFP Mask */
\r
2293 #define I2C2_SDA_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! I2C2_SDA PB12 MFP Mask */
\r
2294 #define I2C2_SDA_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! I2C2_SDA PA10 MFP Mask */
\r
2295 #define I2C2_SDA_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! I2C2_SDA PA15 MFP Mask */
\r
2296 #define I2C2_SDA_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! I2C2_SDA PH9 MFP Mask */
\r
2297 #define I2C2_SDA_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! I2C2_SDA PD8 MFP Mask */
\r
2298 #define I2C2_SDA_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! I2C2_SDA PD0 MFP Mask */
\r
2299 #define I2C2_SMBAL_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! I2C2_SMBAL PB15 MFP Mask */
\r
2300 #define I2C2_SMBSUS_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! I2C2_SMBSUS PB14 MFP Mask */
\r
2301 #define I2S0_BCLK_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! I2S0_BCLK PA12 MFP Mask */
\r
2302 #define I2S0_BCLK_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! I2S0_BCLK PB5 MFP Mask */
\r
2303 #define I2S0_BCLK_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! I2S0_BCLK PE8 MFP Mask */
\r
2304 #define I2S0_BCLK_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! I2S0_BCLK PE1 MFP Mask */
\r
2305 #define I2S0_BCLK_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! I2S0_BCLK PF10 MFP Mask */
\r
2306 #define I2S0_BCLK_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! I2S0_BCLK PC4 MFP Mask */
\r
2307 #define I2S0_DI_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! I2S0_DI PF8 MFP Mask */
\r
2308 #define I2S0_DI_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! I2S0_DI PB3 MFP Mask */
\r
2309 #define I2S0_DI_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! I2S0_DI PE10 MFP Mask */
\r
2310 #define I2S0_DI_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! I2S0_DI PA14 MFP Mask */
\r
2311 #define I2S0_DI_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! I2S0_DI PH8 MFP Mask */
\r
2312 #define I2S0_DI_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! I2S0_DI PC2 MFP Mask */
\r
2313 #define I2S0_DO_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! I2S0_DO PB2 MFP Mask */
\r
2314 #define I2S0_DO_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! I2S0_DO PH9 MFP Mask */
\r
2315 #define I2S0_DO_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! I2S0_DO PF7 MFP Mask */
\r
2316 #define I2S0_DO_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! I2S0_DO PE11 MFP Mask */
\r
2317 #define I2S0_DO_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! I2S0_DO PC1 MFP Mask */
\r
2318 #define I2S0_DO_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! I2S0_DO PA15 MFP Mask */
\r
2319 #define I2S0_LRCK_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! I2S0_LRCK PF6 MFP Mask */
\r
2320 #define I2S0_LRCK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! I2S0_LRCK PE12 MFP Mask */
\r
2321 #define I2S0_LRCK_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! I2S0_LRCK PC0 MFP Mask */
\r
2322 #define I2S0_LRCK_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! I2S0_LRCK PH10 MFP Mask */
\r
2323 #define I2S0_LRCK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! I2S0_LRCK PB1 MFP Mask */
\r
2324 #define I2S0_MCLK_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! I2S0_MCLK PE9 MFP Mask */
\r
2325 #define I2S0_MCLK_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! I2S0_MCLK PB4 MFP Mask */
\r
2326 #define I2S0_MCLK_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! I2S0_MCLK PC3 MFP Mask */
\r
2327 #define I2S0_MCLK_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! I2S0_MCLK PE0 MFP Mask */
\r
2328 #define I2S0_MCLK_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! I2S0_MCLK PA13 MFP Mask */
\r
2329 #define I2S0_MCLK_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! I2S0_MCLK PF9 MFP Mask */
\r
2330 #define ICE_CLK_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! ICE_CLK PF1 MFP Mask */
\r
2331 #define ICE_DAT_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! ICE_DAT PF0 MFP Mask */
\r
2332 #define INT0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! INT0 PB5 MFP Mask */
\r
2333 #define INT0_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! INT0 PA6 MFP Mask */
\r
2334 #define INT1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! INT1 PB4 MFP Mask */
\r
2335 #define INT1_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! INT1 PA7 MFP Mask */
\r
2336 #define INT2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! INT2 PB3 MFP Mask */
\r
2337 #define INT2_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! INT2 PC6 MFP Mask */
\r
2338 #define INT3_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! INT3 PC7 MFP Mask */
\r
2339 #define INT3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! INT3 PB2 MFP Mask */
\r
2340 #define INT4_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! INT4 PB6 MFP Mask */
\r
2341 #define INT4_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! INT4 PA8 MFP Mask */
\r
2342 #define INT5_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! INT5 PB7 MFP Mask */
\r
2343 #define INT5_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! INT5 PD12 MFP Mask */
\r
2344 #define INT6_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! INT6 PD11 MFP Mask */
\r
2345 #define INT6_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! INT6 PB8 MFP Mask */
\r
2346 #define INT7_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! INT7 PB9 MFP Mask */
\r
2347 #define INT7_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! INT7 PD10 MFP Mask */
\r
2348 #define EPWM0_BRAKE0_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! EPWM0_BRAKE0 PE8 MFP Mask */
\r
2349 #define EPWM0_BRAKE0_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EPWM0_BRAKE0 PB1 MFP Mask */
\r
2350 #define EPWM0_BRAKE1_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EPWM0_BRAKE1 PB0 MFP Mask */
\r
2351 #define EPWM0_BRAKE1_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! EPWM0_BRAKE1 PE9 MFP Mask */
\r
2352 #define EPWM0_CH0_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! EPWM0_CH0 PA5 MFP Mask */
\r
2353 #define EPWM0_CH0_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! EPWM0_CH0 PE7 MFP Mask */
\r
2354 #define EPWM0_CH0_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! EPWM0_CH0 PE8 MFP Mask */
\r
2355 #define EPWM0_CH0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! EPWM0_CH0 PB5 MFP Mask */
\r
2356 #define EPWM0_CH1_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! EPWM0_CH1 PA4 MFP Mask */
\r
2357 #define EPWM0_CH1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! EPWM0_CH1 PB4 MFP Mask */
\r
2358 #define EPWM0_CH1_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! EPWM0_CH1 PE9 MFP Mask */
\r
2359 #define EPWM0_CH1_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! EPWM0_CH1 PE6 MFP Mask */
\r
2360 #define EPWM0_CH2_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! EPWM0_CH2 PE5 MFP Mask */
\r
2361 #define EPWM0_CH2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! EPWM0_CH2 PB3 MFP Mask */
\r
2362 #define EPWM0_CH2_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! EPWM0_CH2 PE10 MFP Mask */
\r
2363 #define EPWM0_CH2_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! EPWM0_CH2 PA3 MFP Mask */
\r
2364 #define EPWM0_CH3_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! EPWM0_CH3 PA2 MFP Mask */
\r
2365 #define EPWM0_CH3_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! EPWM0_CH3 PE11 MFP Mask */
\r
2366 #define EPWM0_CH3_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! EPWM0_CH3 PE4 MFP Mask */
\r
2367 #define EPWM0_CH3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! EPWM0_CH3 PB2 MFP Mask */
\r
2368 #define EPWM0_CH4_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! EPWM0_CH4 PD14 MFP Mask */
\r
2369 #define EPWM0_CH4_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EPWM0_CH4 PB1 MFP Mask */
\r
2370 #define EPWM0_CH4_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! EPWM0_CH4 PE3 MFP Mask */
\r
2371 #define EPWM0_CH4_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! EPWM0_CH4 PA1 MFP Mask */
\r
2372 #define EPWM0_CH4_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! EPWM0_CH4 PE12 MFP Mask */
\r
2373 #define EPWM0_CH5_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EPWM0_CH5 PB0 MFP Mask */
\r
2374 #define EPWM0_CH5_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! EPWM0_CH5 PE2 MFP Mask */
\r
2375 #define EPWM0_CH5_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! EPWM0_CH5 PA0 MFP Mask */
\r
2376 #define EPWM0_CH5_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! EPWM0_CH5 PE13 MFP Mask */
\r
2377 #define EPWM0_CH5_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! EPWM0_CH5 PH11 MFP Mask */
\r
2378 #define EPWM0_SYNC_IN_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! EPWM0_SYNC_IN PA15 MFP Mask */
\r
2379 #define EPWM0_SYNC_OUT_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! EPWM0_SYNC_OUT PF5 MFP Mask */
\r
2380 #define EPWM0_SYNC_OUT_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! EPWM0_SYNC_OUT PA11 MFP Mask */
\r
2381 #define EPWM1_BRAKE0_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EPWM1_BRAKE0 PB7 MFP Mask */
\r
2382 #define EPWM1_BRAKE0_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! EPWM1_BRAKE0 PE10 MFP Mask */
\r
2383 #define EPWM1_BRAKE1_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EPWM1_BRAKE1 PB6 MFP Mask */
\r
2384 #define EPWM1_BRAKE1_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! EPWM1_BRAKE1 PE11 MFP Mask */
\r
2385 #define EPWM1_CH0_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! EPWM1_CH0 PC5 MFP Mask */
\r
2386 #define EPWM1_CH0_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! EPWM1_CH0 PE13 MFP Mask */
\r
2387 #define EPWM1_CH0_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! EPWM1_CH0 PC12 MFP Mask */
\r
2388 #define EPWM1_CH0_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! EPWM1_CH0 PB15 MFP Mask */
\r
2389 #define EPWM1_CH1_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EPWM1_CH1 PB14 MFP Mask */
\r
2390 #define EPWM1_CH1_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! EPWM1_CH1 PC11 MFP Mask */
\r
2391 #define EPWM1_CH1_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! EPWM1_CH1 PC4 MFP Mask */
\r
2392 #define EPWM1_CH1_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! EPWM1_CH1 PC8 MFP Mask */
\r
2393 #define EPWM1_CH2_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! EPWM1_CH2 PC7 MFP Mask */
\r
2394 #define EPWM1_CH2_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! EPWM1_CH2 PC10 MFP Mask */
\r
2395 #define EPWM1_CH2_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! EPWM1_CH2 PC3 MFP Mask */
\r
2396 #define EPWM1_CH2_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! EPWM1_CH2 PB13 MFP Mask */
\r
2397 #define EPWM1_CH3_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! EPWM1_CH3 PB12 MFP Mask */
\r
2398 #define EPWM1_CH3_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! EPWM1_CH3 PC6 MFP Mask */
\r
2399 #define EPWM1_CH3_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! EPWM1_CH3 PC9 MFP Mask */
\r
2400 #define EPWM1_CH3_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! EPWM1_CH3 PC2 MFP Mask */
\r
2401 #define EPWM1_CH4_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EPWM1_CH4 PB7 MFP Mask */
\r
2402 #define EPWM1_CH4_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EPWM1_CH4 PB1 MFP Mask */
\r
2403 #define EPWM1_CH4_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! EPWM1_CH4 PC1 MFP Mask */
\r
2404 #define EPWM1_CH4_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! EPWM1_CH4 PA7 MFP Mask */
\r
2405 #define EPWM1_CH5_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! EPWM1_CH5 PA6 MFP Mask */
\r
2406 #define EPWM1_CH5_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! EPWM1_CH5 PC0 MFP Mask */
\r
2407 #define EPWM1_CH5_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EPWM1_CH5 PB6 MFP Mask */
\r
2408 #define EPWM1_CH5_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EPWM1_CH5 PB0 MFP Mask */
\r
2409 #define QEI0_A_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! QEI0_A PE3 MFP Mask */
\r
2410 #define QEI0_A_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! QEI0_A PA4 MFP Mask */
\r
2411 #define QEI0_A_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! QEI0_A PD11 MFP Mask */
\r
2412 #define QEI0_B_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! QEI0_B PD10 MFP Mask */
\r
2413 #define QEI0_B_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! QEI0_B PA3 MFP Mask */
\r
2414 #define QEI0_B_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! QEI0_B PE2 MFP Mask */
\r
2415 #define QEI0_INDEX_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! QEI0_INDEX PE4 MFP Mask */
\r
2416 #define QEI0_INDEX_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! QEI0_INDEX PA5 MFP Mask */
\r
2417 #define QEI0_INDEX_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! QEI0_INDEX PD12 MFP Mask */
\r
2418 #define QEI1_A_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! QEI1_A PE6 MFP Mask */
\r
2419 #define QEI1_A_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! QEI1_A PA13 MFP Mask */
\r
2420 #define QEI1_A_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! QEI1_A PA9 MFP Mask */
\r
2421 #define QEI1_B_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! QEI1_B PA14 MFP Mask */
\r
2422 #define QEI1_B_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! QEI1_B PA8 MFP Mask */
\r
2423 #define QEI1_B_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! QEI1_B PE5 MFP Mask */
\r
2424 #define QEI1_INDEX_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! QEI1_INDEX PE7 MFP Mask */
\r
2425 #define QEI1_INDEX_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! QEI1_INDEX PA10 MFP Mask */
\r
2426 #define QEI1_INDEX_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! QEI1_INDEX PA12 MFP Mask */
\r
2427 #define SC0_CLK_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! SC0_CLK PF6 MFP Mask */
\r
2428 #define SC0_CLK_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SC0_CLK PE2 MFP Mask */
\r
2429 #define SC0_CLK_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! SC0_CLK PA0 MFP Mask */
\r
2430 #define SC0_CLK_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! SC0_CLK PB5 MFP Mask */
\r
2431 #define SC0_DAT_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SC0_DAT PE3 MFP Mask */
\r
2432 #define SC0_DAT_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! SC0_DAT PB4 MFP Mask */
\r
2433 #define SC0_DAT_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! SC0_DAT PA1 MFP Mask */
\r
2434 #define SC0_DAT_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! SC0_DAT PF7 MFP Mask */
\r
2435 #define SC0_PWR_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SC0_PWR PE5 MFP Mask */
\r
2436 #define SC0_PWR_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! SC0_PWR PA3 MFP Mask */
\r
2437 #define SC0_PWR_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! SC0_PWR PB2 MFP Mask */
\r
2438 #define SC0_PWR_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! SC0_PWR PF9 MFP Mask */
\r
2439 #define SC0_RST_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! SC0_RST PF8 MFP Mask */
\r
2440 #define SC0_RST_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SC0_RST PE4 MFP Mask */
\r
2441 #define SC0_RST_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! SC0_RST PA2 MFP Mask */
\r
2442 #define SC0_RST_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! SC0_RST PB3 MFP Mask */
\r
2443 #define SC0_nCD_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! SC0_nCD PE6 MFP Mask */
\r
2444 #define SC0_nCD_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! SC0_nCD PF10 MFP Mask */
\r
2445 #define SC0_nCD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! SC0_nCD PA4 MFP Mask */
\r
2446 #define SC0_nCD_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! SC0_nCD PC12 MFP Mask */
\r
2447 #define SC1_CLK_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! SC1_CLK PC0 MFP Mask */
\r
2448 #define SC1_CLK_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! SC1_CLK PB12 MFP Mask */
\r
2449 #define SC1_CLK_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! SC1_CLK PD4 MFP Mask */
\r
2450 #define SC1_DAT_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! SC1_DAT PD5 MFP Mask */
\r
2451 #define SC1_DAT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! SC1_DAT PB13 MFP Mask */
\r
2452 #define SC1_DAT_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! SC1_DAT PC1 MFP Mask */
\r
2453 #define SC1_PWR_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! SC1_PWR PB15 MFP Mask */
\r
2454 #define SC1_PWR_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! SC1_PWR PC3 MFP Mask */
\r
2455 #define SC1_PWR_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! SC1_PWR PD7 MFP Mask */
\r
2456 #define SC1_RST_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! SC1_RST PD6 MFP Mask */
\r
2457 #define SC1_RST_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! SC1_RST PB14 MFP Mask */
\r
2458 #define SC1_RST_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! SC1_RST PC2 MFP Mask */
\r
2459 #define SC1_nCD_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! SC1_nCD PD3 MFP Mask */
\r
2460 #define SC1_nCD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! SC1_nCD PC4 MFP Mask */
\r
2461 #define SC1_nCD_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! SC1_nCD PD14 MFP Mask */
\r
2462 #define SC2_CLK_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! SC2_CLK PD0 MFP Mask */
\r
2463 #define SC2_CLK_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! SC2_CLK PA15 MFP Mask */
\r
2464 #define SC2_CLK_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! SC2_CLK PE0 MFP Mask */
\r
2465 #define SC2_CLK_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! SC2_CLK PA8 MFP Mask */
\r
2466 #define SC2_CLK_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! SC2_CLK PA6 MFP Mask */
\r
2467 #define SC2_DAT_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! SC2_DAT PE1 MFP Mask */
\r
2468 #define SC2_DAT_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! SC2_DAT PD1 MFP Mask */
\r
2469 #define SC2_DAT_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! SC2_DAT PA9 MFP Mask */
\r
2470 #define SC2_DAT_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! SC2_DAT PA14 MFP Mask */
\r
2471 #define SC2_DAT_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! SC2_DAT PA7 MFP Mask */
\r
2472 #define SC2_PWR_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! SC2_PWR PD3 MFP Mask */
\r
2473 #define SC2_PWR_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! SC2_PWR PA11 MFP Mask */
\r
2474 #define SC2_PWR_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! SC2_PWR PA12 MFP Mask */
\r
2475 #define SC2_PWR_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! SC2_PWR PH8 MFP Mask */
\r
2476 #define SC2_PWR_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! SC2_PWR PC7 MFP Mask */
\r
2477 #define SC2_RST_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! SC2_RST PD2 MFP Mask */
\r
2478 #define SC2_RST_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! SC2_RST PC6 MFP Mask */
\r
2479 #define SC2_RST_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! SC2_RST PH9 MFP Mask */
\r
2480 #define SC2_RST_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! SC2_RST PA10 MFP Mask */
\r
2481 #define SC2_RST_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! SC2_RST PA13 MFP Mask */
\r
2482 #define SC2_nCD_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! SC2_nCD PH10 MFP Mask */
\r
2483 #define SC2_nCD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! SC2_nCD PA5 MFP Mask */
\r
2484 #define SC2_nCD_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! SC2_nCD PC13 MFP Mask */
\r
2485 #define SC2_nCD_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SC2_nCD PD13 MFP Mask */
\r
2486 #define SD0_CLK_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! SD0_CLK PE6 MFP Mask */
\r
2487 #define SD0_CLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! SD0_CLK PB1 MFP Mask */
\r
2488 #define SD0_CMD_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! SD0_CMD PB0 MFP Mask */
\r
2489 #define SD0_CMD_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! SD0_CMD PE7 MFP Mask */
\r
2490 #define SD0_DAT0_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! SD0_DAT0 PB2 MFP Mask */
\r
2491 #define SD0_DAT0_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SD0_DAT0 PE2 MFP Mask */
\r
2492 #define SD0_DAT1_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SD0_DAT1 PE3 MFP Mask */
\r
2493 #define SD0_DAT1_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! SD0_DAT1 PB3 MFP Mask */
\r
2494 #define SD0_DAT2_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! SD0_DAT2 PB4 MFP Mask */
\r
2495 #define SD0_DAT2_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SD0_DAT2 PE4 MFP Mask */
\r
2496 #define SD0_DAT3_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SD0_DAT3 PE5 MFP Mask */
\r
2497 #define SD0_DAT3_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! SD0_DAT3 PB5 MFP Mask */
\r
2498 #define SD0_nCD_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! SD0_nCD PB12 MFP Mask */
\r
2499 #define SD0_nCD_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SD0_nCD PD13 MFP Mask */
\r
2500 #define QSPI0_CLK_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! QSPI0_CLK PF2 MFP Mask */
\r
2501 #define QSPI0_CLK_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! QSPI0_CLK PH8 MFP Mask */
\r
2502 #define QSPI0_CLK_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! QSPI0_CLK PA2 MFP Mask */
\r
2503 #define QSPI0_CLK_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! QSPI0_CLK PC2 MFP Mask */
\r
2504 #define QSPI0_MISO0_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! QSPI0_MISO0 PC1 MFP Mask */
\r
2505 #define QSPI0_MISO0_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! QSPI0_MISO0 PE1 MFP Mask */
\r
2506 #define QSPI0_MISO0_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! QSPI0_MISO0 PA1 MFP Mask */
\r
2507 #define QSPI0_MISO1_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! QSPI0_MISO1 PC5 MFP Mask */
\r
2508 #define QSPI0_MISO1_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! QSPI0_MISO1 PH10 MFP Mask */
\r
2509 #define QSPI0_MISO1_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! QSPI0_MISO1 PA5 MFP Mask */
\r
2510 #define QSPI0_MOSI0_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! QSPI0_MOSI0 PC0 MFP Mask */
\r
2511 #define QSPI0_MOSI0_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! QSPI0_MOSI0 PE0 MFP Mask */
\r
2512 #define QSPI0_MOSI0_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! QSPI0_MOSI0 PA0 MFP Mask */
\r
2513 #define QSPI0_MOSI1_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! QSPI0_MOSI1 PA4 MFP Mask */
\r
2514 #define QSPI0_MOSI1_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! QSPI0_MOSI1 PH11 MFP Mask */
\r
2515 #define QSPI0_MOSI1_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! QSPI0_MOSI1 PC4 MFP Mask */
\r
2516 #define QSPI0_SS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! QSPI0_SS PH9 MFP Mask */
\r
2517 #define QSPI0_SS_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! QSPI0_SS PA3 MFP Mask */
\r
2518 #define QSPI0_SS_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! QSPI0_SS PC3 MFP Mask */
\r
2519 #define SPI0_CLK_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! SPI0_CLK PD2 MFP Mask */
\r
2520 #define SPI0_CLK_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! SPI0_CLK PF8 MFP Mask */
\r
2521 #define SPI0_CLK_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! SPI0_CLK PA2 MFP Mask */
\r
2522 #define SPI0_CLK_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! SPI0_CLK PB14 MFP Mask */
\r
2523 #define SPI0_I2SMCLK_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SPI0_I2SMCLK PD13 MFP Mask */
\r
2524 #define SPI0_I2SMCLK_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! SPI0_I2SMCLK PA4 MFP Mask */
\r
2525 #define SPI0_I2SMCLK_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! SPI0_I2SMCLK PB11 MFP Mask */
\r
2526 #define SPI0_I2SMCLK_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! SPI0_I2SMCLK PB0 MFP Mask */
\r
2527 #define SPI0_I2SMCLK_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! SPI0_I2SMCLK PD14 MFP Mask */
\r
2528 #define SPI0_I2SMCLK_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! SPI0_I2SMCLK PF10 MFP Mask */
\r
2529 #define SPI0_MISO_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! SPI0_MISO PF7 MFP Mask */
\r
2530 #define SPI0_MISO_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! SPI0_MISO PB13 MFP Mask */
\r
2531 #define SPI0_MISO_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! SPI0_MISO PA1 MFP Mask */
\r
2532 #define SPI0_MISO_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! SPI0_MISO PD1 MFP Mask */
\r
2533 #define SPI0_MOSI_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! SPI0_MOSI PA0 MFP Mask */
\r
2534 #define SPI0_MOSI_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! SPI0_MOSI PB12 MFP Mask */
\r
2535 #define SPI0_MOSI_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! SPI0_MOSI PD0 MFP Mask */
\r
2536 #define SPI0_MOSI_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! SPI0_MOSI PF6 MFP Mask */
\r
2537 #define SPI0_SS_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! SPI0_SS PB15 MFP Mask */
\r
2538 #define SPI0_SS_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! SPI0_SS PA3 MFP Mask */
\r
2539 #define SPI0_SS_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! SPI0_SS PD3 MFP Mask */
\r
2540 #define SPI0_SS_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! SPI0_SS PF9 MFP Mask */
\r
2541 #define SPI1_CLK_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! SPI1_CLK PB3 MFP Mask */
\r
2542 #define SPI1_CLK_PH6_Msk SYS_GPH_MFPL_PH6MFP_Msk /*<! SPI1_CLK PH6 MFP Mask */
\r
2543 #define SPI1_CLK_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! SPI1_CLK PH8 MFP Mask */
\r
2544 #define SPI1_CLK_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! SPI1_CLK PC1 MFP Mask */
\r
2545 #define SPI1_CLK_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! SPI1_CLK PD5 MFP Mask */
\r
2546 #define SPI1_CLK_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! SPI1_CLK PA7 MFP Mask */
\r
2547 #define SPI1_I2SMCLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! SPI1_I2SMCLK PB1 MFP Mask */
\r
2548 #define SPI1_I2SMCLK_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! SPI1_I2SMCLK PH10 MFP Mask */
\r
2549 #define SPI1_I2SMCLK_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! SPI1_I2SMCLK PC4 MFP Mask */
\r
2550 #define SPI1_I2SMCLK_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SPI1_I2SMCLK PD13 MFP Mask */
\r
2551 #define SPI1_I2SMCLK_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! SPI1_I2SMCLK PA5 MFP Mask */
\r
2552 #define SPI1_MISO_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! SPI1_MISO PD7 MFP Mask */
\r
2553 #define SPI1_MISO_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! SPI1_MISO PC7 MFP Mask */
\r
2554 #define SPI1_MISO_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! SPI1_MISO PB5 MFP Mask */
\r
2555 #define SPI1_MISO_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! SPI1_MISO PE1 MFP Mask */
\r
2556 #define SPI1_MISO_PH4_Msk SYS_GPH_MFPL_PH4MFP_Msk /*<! SPI1_MISO PH4 MFP Mask */
\r
2557 #define SPI1_MISO_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! SPI1_MISO PC3 MFP Mask */
\r
2558 #define SPI1_MOSI_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! SPI1_MOSI PD6 MFP Mask */
\r
2559 #define SPI1_MOSI_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! SPI1_MOSI PE0 MFP Mask */
\r
2560 #define SPI1_MOSI_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! SPI1_MOSI PB4 MFP Mask */
\r
2561 #define SPI1_MOSI_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! SPI1_MOSI PC6 MFP Mask */
\r
2562 #define SPI1_MOSI_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! SPI1_MOSI PC2 MFP Mask */
\r
2563 #define SPI1_MOSI_PH5_Msk SYS_GPH_MFPL_PH5MFP_Msk /*<! SPI1_MOSI PH5 MFP Mask */
\r
2564 #define SPI1_SS_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! SPI1_SS PB2 MFP Mask */
\r
2565 #define SPI1_SS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! SPI1_SS PH9 MFP Mask */
\r
2566 #define SPI1_SS_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! SPI1_SS PD4 MFP Mask */
\r
2567 #define SPI1_SS_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! SPI1_SS PC0 MFP Mask */
\r
2568 #define SPI1_SS_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! SPI1_SS PA6 MFP Mask */
\r
2569 #define SPI1_SS_PH7_Msk SYS_GPH_MFPL_PH7MFP_Msk /*<! SPI1_SS PH7 MFP Mask */
\r
2570 #define SPI2_CLK_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! SPI2_CLK PE8 MFP Mask */
\r
2571 #define SPI2_CLK_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! SPI2_CLK PG3 MFP Mask */
\r
2572 #define SPI2_CLK_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! SPI2_CLK PA10 MFP Mask */
\r
2573 #define SPI2_CLK_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! SPI2_CLK PA13 MFP Mask */
\r
2574 #define SPI2_I2SMCLK_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! SPI2_I2SMCLK PC13 MFP Mask */
\r
2575 #define SPI2_I2SMCLK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! SPI2_I2SMCLK PE12 MFP Mask */
\r
2576 #define SPI2_MISO_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! SPI2_MISO PG4 MFP Mask */
\r
2577 #define SPI2_MISO_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! SPI2_MISO PA9 MFP Mask */
\r
2578 #define SPI2_MISO_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! SPI2_MISO PA14 MFP Mask */
\r
2579 #define SPI2_MISO_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! SPI2_MISO PE9 MFP Mask */
\r
2580 #define SPI2_MOSI_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! SPI2_MOSI PE10 MFP Mask */
\r
2581 #define SPI2_MOSI_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! SPI2_MOSI PA15 MFP Mask */
\r
2582 #define SPI2_MOSI_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! SPI2_MOSI PA8 MFP Mask */
\r
2583 #define SPI2_MOSI_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! SPI2_MOSI PF11 MFP Mask */
\r
2584 #define SPI2_SS_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! SPI2_SS PG2 MFP Mask */
\r
2585 #define SPI2_SS_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! SPI2_SS PE11 MFP Mask */
\r
2586 #define SPI2_SS_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! SPI2_SS PA11 MFP Mask */
\r
2587 #define SPI2_SS_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! SPI2_SS PA12 MFP Mask */
\r
2588 #define SPI3_CLK_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! SPI3_CLK PB11 MFP Mask */
\r
2589 #define SPI3_CLK_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SPI3_CLK PE4 MFP Mask */
\r
2590 #define SPI3_CLK_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! SPI3_CLK PC10 MFP Mask */
\r
2591 #define SPI3_I2SMCLK_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! SPI3_I2SMCLK PE6 MFP Mask */
\r
2592 #define SPI3_I2SMCLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! SPI3_I2SMCLK PB1 MFP Mask */
\r
2593 #define SPI3_I2SMCLK_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! SPI3_I2SMCLK PD14 MFP Mask */
\r
2594 #define SPI3_MISO_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! SPI3_MISO PC12 MFP Mask */
\r
2595 #define SPI3_MISO_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! SPI3_MISO PB9 MFP Mask */
\r
2596 #define SPI3_MISO_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SPI3_MISO PE3 MFP Mask */
\r
2597 #define SPI3_MOSI_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! SPI3_MOSI PB8 MFP Mask */
\r
2598 #define SPI3_MOSI_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SPI3_MOSI PE2 MFP Mask */
\r
2599 #define SPI3_MOSI_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! SPI3_MOSI PC11 MFP Mask */
\r
2600 #define SPI3_SS_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SPI3_SS PE5 MFP Mask */
\r
2601 #define SPI3_SS_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! SPI3_SS PB10 MFP Mask */
\r
2602 #define SPI3_SS_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! SPI3_SS PC9 MFP Mask */
\r
2603 #define TAMPER0_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! TAMPER0 PF6 MFP Mask */
\r
2604 #define TAMPER1_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! TAMPER1 PF7 MFP Mask */
\r
2605 #define TAMPER2_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! TAMPER2 PF8 MFP Mask */
\r
2606 #define TAMPER3_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! TAMPER3 PF9 MFP Mask */
\r
2607 #define TAMPER4_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! TAMPER4 PF10 MFP Mask */
\r
2608 #define TAMPER5_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! TAMPER5 PF11 MFP Mask */
\r
2609 #define TM0_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! TM0 PC7 MFP Mask */
\r
2610 #define TM0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! TM0 PB5 MFP Mask */
\r
2611 #define TM0_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! TM0 PG2 MFP Mask */
\r
2612 #define TM0_EXT_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! TM0_EXT PA11 MFP Mask */
\r
2613 #define TM0_EXT_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! TM0_EXT PB15 MFP Mask */
\r
2614 #define TM1_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! TM1 PG3 MFP Mask */
\r
2615 #define TM1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! TM1 PB4 MFP Mask */
\r
2616 #define TM1_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! TM1 PC6 MFP Mask */
\r
2617 #define TM1_EXT_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! TM1_EXT PA10 MFP Mask */
\r
2618 #define TM1_EXT_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! TM1_EXT PB14 MFP Mask */
\r
2619 #define TM2_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! TM2 PG4 MFP Mask */
\r
2620 #define TM2_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! TM2 PD0 MFP Mask */
\r
2621 #define TM2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! TM2 PB3 MFP Mask */
\r
2622 #define TM2_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! TM2 PA7 MFP Mask */
\r
2623 #define TM2_EXT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! TM2_EXT PB13 MFP Mask */
\r
2624 #define TM2_EXT_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! TM2_EXT PA9 MFP Mask */
\r
2625 #define TM3_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! TM3 PA6 MFP Mask */
\r
2626 #define TM3_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! TM3 PF11 MFP Mask */
\r
2627 #define TM3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! TM3 PB2 MFP Mask */
\r
2628 #define TM3_EXT_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! TM3_EXT PA8 MFP Mask */
\r
2629 #define TM3_EXT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! TM3_EXT PB12 MFP Mask */
\r
2630 #define TRACE_CLK_PE12_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! TRACE_CLK PE12 MFP Mask */
\r
2631 #define TRACE_DATA0_PE11_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! TRACE_DATA0 PE11 MFP Mask */
\r
2632 #define TRACE_DATA1_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! TRACE_DATA1 PE10 MFP Mask */
\r
2633 #define TRACE_DATA2_PE9_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! TRACE_DATA2 PE9 MFP Mask */
\r
2634 #define TRACE_DATA3_PE8_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! TRACE_DATA3 PE8 MFP Mask */
\r
2635 #define UART0_RXD_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! UART0_RXD PD2 MFP Mask */
\r
2636 #define UART0_RXD_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! UART0_RXD PB8 MFP Mask */
\r
2637 #define UART0_RXD_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! UART0_RXD PA0 MFP Mask */
\r
2638 #define UART0_RXD_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! UART0_RXD PA6 MFP Mask */
\r
2639 #define UART0_RXD_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! UART0_RXD PB12 MFP Mask */
\r
2640 #define UART0_RXD_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! UART0_RXD PA15 MFP Mask */
\r
2641 #define UART0_RXD_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! UART0_RXD PC11 MFP Mask */
\r
2642 #define UART0_RXD_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! UART0_RXD PH11 MFP Mask */
\r
2643 #define UART0_RXD_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! UART0_RXD PF2 MFP Mask */
\r
2644 #define UART0_TXD_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! UART0_TXD PA7 MFP Mask */
\r
2645 #define UART0_TXD_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! UART0_TXD PD3 MFP Mask */
\r
2646 #define UART0_TXD_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! UART0_TXD PF3 MFP Mask */
\r
2647 #define UART0_TXD_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! UART0_TXD PC12 MFP Mask */
\r
2648 #define UART0_TXD_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! UART0_TXD PH10 MFP Mask */
\r
2649 #define UART0_TXD_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! UART0_TXD PA1 MFP Mask */
\r
2650 #define UART0_TXD_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! UART0_TXD PB9 MFP Mask */
\r
2651 #define UART0_TXD_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! UART0_TXD PB13 MFP Mask */
\r
2652 #define UART0_TXD_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! UART0_TXD PA14 MFP Mask */
\r
2653 #define UART0_nCTS_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! UART0_nCTS PA5 MFP Mask */
\r
2654 #define UART0_nCTS_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! UART0_nCTS PB11 MFP Mask */
\r
2655 #define UART0_nCTS_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! UART0_nCTS PB15 MFP Mask */
\r
2656 #define UART0_nCTS_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! UART0_nCTS PC7 MFP Mask */
\r
2657 #define UART0_nRTS_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! UART0_nRTS PB14 MFP Mask */
\r
2658 #define UART0_nRTS_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! UART0_nRTS PB10 MFP Mask */
\r
2659 #define UART0_nRTS_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! UART0_nRTS PC6 MFP Mask */
\r
2660 #define UART0_nRTS_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! UART0_nRTS PA4 MFP Mask */
\r
2661 #define UART1_RXD_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! UART1_RXD PF1 MFP Mask */
\r
2662 #define UART1_RXD_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! UART1_RXD PA8 MFP Mask */
\r
2663 #define UART1_RXD_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! UART1_RXD PA2 MFP Mask */
\r
2664 #define UART1_RXD_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! UART1_RXD PB2 MFP Mask */
\r
2665 #define UART1_RXD_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! UART1_RXD PB6 MFP Mask */
\r
2666 #define UART1_RXD_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! UART1_RXD PD6 MFP Mask */
\r
2667 #define UART1_RXD_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! UART1_RXD PD10 MFP Mask */
\r
2668 #define UART1_RXD_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! UART1_RXD PH9 MFP Mask */
\r
2669 #define UART1_RXD_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! UART1_RXD PC8 MFP Mask */
\r
2670 #define UART1_TXD_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! UART1_TXD PB3 MFP Mask */
\r
2671 #define UART1_TXD_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! UART1_TXD PA3 MFP Mask */
\r
2672 #define UART1_TXD_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! UART1_TXD PE13 MFP Mask */
\r
2673 #define UART1_TXD_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! UART1_TXD PA9 MFP Mask */
\r
2674 #define UART1_TXD_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! UART1_TXD PF0 MFP Mask */
\r
2675 #define UART1_TXD_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! UART1_TXD PD11 MFP Mask */
\r
2676 #define UART1_TXD_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! UART1_TXD PD7 MFP Mask */
\r
2677 #define UART1_TXD_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! UART1_TXD PB7 MFP Mask */
\r
2678 #define UART1_TXD_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! UART1_TXD PH8 MFP Mask */
\r
2679 #define UART1_nCTS_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! UART1_nCTS PE11 MFP Mask */
\r
2680 #define UART1_nCTS_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! UART1_nCTS PB9 MFP Mask */
\r
2681 #define UART1_nCTS_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! UART1_nCTS PA1 MFP Mask */
\r
2682 #define UART1_nRTS_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! UART1_nRTS PA0 MFP Mask */
\r
2683 #define UART1_nRTS_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! UART1_nRTS PE12 MFP Mask */
\r
2684 #define UART1_nRTS_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! UART1_nRTS PB8 MFP Mask */
\r
2685 #define UART2_RXD_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! UART2_RXD PB0 MFP Mask */
\r
2686 #define UART2_RXD_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! UART2_RXD PE15 MFP Mask */
\r
2687 #define UART2_RXD_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! UART2_RXD PD12 MFP Mask */
\r
2688 #define UART2_RXD_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! UART2_RXD PF5 MFP Mask */
\r
2689 #define UART2_RXD_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! UART2_RXD PC0 MFP Mask */
\r
2690 #define UART2_RXD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! UART2_RXD PC4 MFP Mask */
\r
2691 #define UART2_RXD_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! UART2_RXD PE9 MFP Mask */
\r
2692 #define UART2_TXD_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! UART2_TXD PE8 MFP Mask */
\r
2693 #define UART2_TXD_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! UART2_TXD PF4 MFP Mask */
\r
2694 #define UART2_TXD_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! UART2_TXD PC13 MFP Mask */
\r
2695 #define UART2_TXD_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! UART2_TXD PC1 MFP Mask */
\r
2696 #define UART2_TXD_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! UART2_TXD PE14 MFP Mask */
\r
2697 #define UART2_TXD_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! UART2_TXD PC5 MFP Mask */
\r
2698 #define UART2_TXD_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! UART2_TXD PB1 MFP Mask */
\r
2699 #define UART2_nCTS_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! UART2_nCTS PF5 MFP Mask */
\r
2700 #define UART2_nCTS_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! UART2_nCTS PD9 MFP Mask */
\r
2701 #define UART2_nCTS_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! UART2_nCTS PC2 MFP Mask */
\r
2702 #define UART2_nRTS_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! UART2_nRTS PF4 MFP Mask */
\r
2703 #define UART2_nRTS_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! UART2_nRTS PD8 MFP Mask */
\r
2704 #define UART2_nRTS_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! UART2_nRTS PC3 MFP Mask */
\r
2705 #define UART3_RXD_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! UART3_RXD PD0 MFP Mask */
\r
2706 #define UART3_RXD_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! UART3_RXD PE11 MFP Mask */
\r
2707 #define UART3_RXD_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! UART3_RXD PC9 MFP Mask */
\r
2708 #define UART3_RXD_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! UART3_RXD PE0 MFP Mask */
\r
2709 #define UART3_RXD_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! UART3_RXD PC2 MFP Mask */
\r
2710 #define UART3_RXD_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! UART3_RXD PB14 MFP Mask */
\r
2711 #define UART3_TXD_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! UART3_TXD PD1 MFP Mask */
\r
2712 #define UART3_TXD_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! UART3_TXD PC10 MFP Mask */
\r
2713 #define UART3_TXD_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! UART3_TXD PB15 MFP Mask */
\r
2714 #define UART3_TXD_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! UART3_TXD PC3 MFP Mask */
\r
2715 #define UART3_TXD_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! UART3_TXD PE1 MFP Mask */
\r
2716 #define UART3_TXD_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! UART3_TXD PE10 MFP Mask */
\r
2717 #define UART3_nCTS_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! UART3_nCTS PB12 MFP Mask */
\r
2718 #define UART3_nCTS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! UART3_nCTS PH9 MFP Mask */
\r
2719 #define UART3_nCTS_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! UART3_nCTS PD2 MFP Mask */
\r
2720 #define UART3_nRTS_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! UART3_nRTS PB13 MFP Mask */
\r
2721 #define UART3_nRTS_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! UART3_nRTS PH8 MFP Mask */
\r
2722 #define UART3_nRTS_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! UART3_nRTS PD3 MFP Mask */
\r
2723 #define UART4_RXD_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! UART4_RXD PA13 MFP Mask */
\r
2724 #define UART4_RXD_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! UART4_RXD PC6 MFP Mask */
\r
2725 #define UART4_RXD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! UART4_RXD PC4 MFP Mask */
\r
2726 #define UART4_RXD_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! UART4_RXD PB10 MFP Mask */
\r
2727 #define UART4_RXD_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! UART4_RXD PH11 MFP Mask */
\r
2728 #define UART4_RXD_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! UART4_RXD PA2 MFP Mask */
\r
2729 #define UART4_RXD_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! UART4_RXD PF6 MFP Mask */
\r
2730 #define UART4_TXD_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! UART4_TXD PH10 MFP Mask */
\r
2731 #define UART4_TXD_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! UART4_TXD PA3 MFP Mask */
\r
2732 #define UART4_TXD_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! UART4_TXD PA12 MFP Mask */
\r
2733 #define UART4_TXD_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! UART4_TXD PC7 MFP Mask */
\r
2734 #define UART4_TXD_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! UART4_TXD PB11 MFP Mask */
\r
2735 #define UART4_TXD_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! UART4_TXD PF7 MFP Mask */
\r
2736 #define UART4_TXD_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! UART4_TXD PC5 MFP Mask */
\r
2737 #define UART4_nCTS_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! UART4_nCTS PE1 MFP Mask */
\r
2738 #define UART4_nCTS_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! UART4_nCTS PC8 MFP Mask */
\r
2739 #define UART4_nRTS_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! UART4_nRTS PE0 MFP Mask */
\r
2740 #define UART4_nRTS_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! UART4_nRTS PE13 MFP Mask */
\r
2741 #define UART5_RXD_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! UART5_RXD PB4 MFP Mask */
\r
2742 #define UART5_RXD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! UART5_RXD PA4 MFP Mask */
\r
2743 #define UART5_RXD_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! UART5_RXD PE6 MFP Mask */
\r
2744 #define UART5_TXD_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! UART5_TXD PB5 MFP Mask */
\r
2745 #define UART5_TXD_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! UART5_TXD PE7 MFP Mask */
\r
2746 #define UART5_TXD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! UART5_TXD PA5 MFP Mask */
\r
2747 #define UART5_nCTS_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! UART5_nCTS PB2 MFP Mask */
\r
2748 #define UART5_nRTS_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! UART5_nRTS PB3 MFP Mask */
\r
2749 #define USB_D_P_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! USB_D_P PA14 MFP Mask */
\r
2750 #define USB_D_N_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! USB_D_N PA13 MFP Mask */
\r
2751 #define USB_OTG_ID_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! USB_OTG_ID PA15 MFP Mask */
\r
2752 #define USB_VBUS_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! USB_VBUS PA12 MFP Mask */
\r
2753 #define USB_VBUS_EN_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! USB_VBUS_EN PB6 MFP Mask */
\r
2754 #define USB_VBUS_EN_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! USB_VBUS_EN PB15 MFP Mask */
\r
2755 #define USB_VBUS_ST_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! USB_VBUS_ST PB14 MFP Mask */
\r
2756 #define USB_VBUS_ST_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! USB_VBUS_ST PB7 MFP Mask */
\r
2757 #define USB_VBUS_ST_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! USB_VBUS_ST PD4 MFP Mask */
\r
2758 #define USCI0_CLK_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! USCI0_CLK PD0 MFP Mask */
\r
2759 #define USCI0_CLK_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! USCI0_CLK PA11 MFP Mask */
\r
2760 #define USCI0_CLK_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! USCI0_CLK PE2 MFP Mask */
\r
2761 #define USCI0_CLK_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! USCI0_CLK PB12 MFP Mask */
\r
2762 #define USCI0_CTL0_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! USCI0_CTL0 PD4 MFP Mask */
\r
2763 #define USCI0_CTL0_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! USCI0_CTL0 PE6 MFP Mask */
\r
2764 #define USCI0_CTL0_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! USCI0_CTL0 PC13 MFP Mask */
\r
2765 #define USCI0_CTL0_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! USCI0_CTL0 PD14 MFP Mask */
\r
2766 #define USCI0_CTL1_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! USCI0_CTL1 PD3 MFP Mask */
\r
2767 #define USCI0_CTL1_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! USCI0_CTL1 PE5 MFP Mask */
\r
2768 #define USCI0_CTL1_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! USCI0_CTL1 PB15 MFP Mask */
\r
2769 #define USCI0_CTL1_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! USCI0_CTL1 PA8 MFP Mask */
\r
2770 #define USCI0_DAT0_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! USCI0_DAT0 PE3 MFP Mask */
\r
2771 #define USCI0_DAT0_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! USCI0_DAT0 PB13 MFP Mask */
\r
2772 #define USCI0_DAT0_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! USCI0_DAT0 PD1 MFP Mask */
\r
2773 #define USCI0_DAT0_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! USCI0_DAT0 PA10 MFP Mask */
\r
2774 #define USCI0_DAT1_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! USCI0_DAT1 PE4 MFP Mask */
\r
2775 #define USCI0_DAT1_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! USCI0_DAT1 PD2 MFP Mask */
\r
2776 #define USCI0_DAT1_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! USCI0_DAT1 PB14 MFP Mask */
\r
2777 #define USCI0_DAT1_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! USCI0_DAT1 PA9 MFP Mask */
\r
2778 #define USCI1_CLK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! USCI1_CLK PE12 MFP Mask */
\r
2779 #define USCI1_CLK_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! USCI1_CLK PD7 MFP Mask */
\r
2780 #define USCI1_CLK_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! USCI1_CLK PB8 MFP Mask */
\r
2781 #define USCI1_CLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! USCI1_CLK PB1 MFP Mask */
\r
2782 #define USCI1_CTL0_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! USCI1_CTL0 PB10 MFP Mask */
\r
2783 #define USCI1_CTL0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! USCI1_CTL0 PB5 MFP Mask */
\r
2784 #define USCI1_CTL0_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! USCI1_CTL0 PE9 MFP Mask */
\r
2785 #define USCI1_CTL0_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! USCI1_CTL0 PD3 MFP Mask */
\r
2786 #define USCI1_CTL1_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! USCI1_CTL1 PD4 MFP Mask */
\r
2787 #define USCI1_CTL1_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! USCI1_CTL1 PE8 MFP Mask */
\r
2788 #define USCI1_CTL1_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! USCI1_CTL1 PB9 MFP Mask */
\r
2789 #define USCI1_CTL1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! USCI1_CTL1 PB4 MFP Mask */
\r
2790 #define USCI1_DAT0_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! USCI1_DAT0 PB2 MFP Mask */
\r
2791 #define USCI1_DAT0_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! USCI1_DAT0 PB7 MFP Mask */
\r
2792 #define USCI1_DAT0_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! USCI1_DAT0 PE10 MFP Mask */
\r
2793 #define USCI1_DAT0_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! USCI1_DAT0 PD5 MFP Mask */
\r
2794 #define USCI1_DAT1_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! USCI1_DAT1 PD6 MFP Mask */
\r
2795 #define USCI1_DAT1_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! USCI1_DAT1 PB3 MFP Mask */
\r
2796 #define USCI1_DAT1_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! USCI1_DAT1 PE11 MFP Mask */
\r
2797 #define USCI1_DAT1_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! USCI1_DAT1 PB6 MFP Mask */
\r
2798 #define X32_IN_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! X32_IN PF5 MFP Mask */
\r
2799 #define X32_OUT_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! X32_OUT PF4 MFP Mask */
\r
2800 #define XT1_IN_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! XT1_IN PF3 MFP Mask */
\r
2801 #define XT1_OUT_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! XT1_OUT PF2 MFP Mask */
\r
2805 /*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
\r
2807 /** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
\r
2813 * @brief Clear Brown-out detector interrupt flag
\r
2816 * @details This macro clear Brown-out detector interrupt flag.
\r
2818 #define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
\r
2821 * @brief Set Brown-out detector function to normal mode
\r
2824 * @details This macro set Brown-out detector to normal mode.
\r
2825 * The register write-protection function should be disabled before using this macro.
\r
2827 #define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
\r
2830 * @brief Disable Brown-out detector function
\r
2833 * @details This macro disable Brown-out detector function.
\r
2834 * The register write-protection function should be disabled before using this macro.
\r
2836 #define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
\r
2839 * @brief Enable Brown-out detector function
\r
2842 * @details This macro enable Brown-out detector function.
\r
2843 * The register write-protection function should be disabled before using this macro.
\r
2845 #define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
\r
2848 * @brief Get Brown-out detector interrupt flag
\r
2850 * @retval 0 Brown-out detect interrupt flag is not set.
\r
2851 * @retval >=1 Brown-out detect interrupt flag is set.
\r
2852 * @details This macro get Brown-out detector interrupt flag.
\r
2854 #define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
\r
2857 * @brief Get Brown-out detector status
\r
2859 * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
\r
2860 * @retval >=1 System voltage is lower than BOD threshold voltage setting.
\r
2861 * @details This macro get Brown-out detector output status.
\r
2862 * If the BOD function is disabled, this function always return 0.
\r
2864 #define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
\r
2867 * @brief Enable Brown-out detector interrupt function
\r
2870 * @details This macro enable Brown-out detector interrupt function.
\r
2871 * The register write-protection function should be disabled before using this macro.
\r
2873 #define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
\r
2876 * @brief Enable Brown-out detector reset function
\r
2879 * @details This macro enable Brown-out detect reset function.
\r
2880 * The register write-protection function should be disabled before using this macro.
\r
2882 #define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
\r
2885 * @brief Set Brown-out detector function low power mode
\r
2888 * @details This macro set Brown-out detector to low power mode.
\r
2889 * The register write-protection function should be disabled before using this macro.
\r
2891 #define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
\r
2894 * @brief Set Brown-out detector voltage level
\r
2895 * @param[in] u32Level is Brown-out voltage level. Including :
\r
2896 * - \ref SYS_BODCTL_BODVL_1_6V
\r
2897 * - \ref SYS_BODCTL_BODVL_1_8V
\r
2898 * - \ref SYS_BODCTL_BODVL_2_0V
\r
2899 * - \ref SYS_BODCTL_BODVL_2_2V
\r
2900 * - \ref SYS_BODCTL_BODVL_2_4V
\r
2901 * - \ref SYS_BODCTL_BODVL_2_6V
\r
2902 * - \ref SYS_BODCTL_BODVL_2_8V
\r
2903 * - \ref SYS_BODCTL_BODVL_3_0V
\r
2905 * @details This macro set Brown-out detector voltage level.
\r
2906 * The write-protection function should be disabled before using this macro.
\r
2908 #define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
\r
2911 * @brief Get reset source is from Brown-out detector reset
\r
2913 * @retval 0 Previous reset source is not from Brown-out detector reset
\r
2914 * @retval >=1 Previous reset source is from Brown-out detector reset
\r
2915 * @details This macro get previous reset source is from Brown-out detect reset or not.
\r
2917 #define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
\r
2920 * @brief Get reset source is from CPU reset
\r
2922 * @retval 0 Previous reset source is not from CPU reset
\r
2923 * @retval >=1 Previous reset source is from CPU reset
\r
2924 * @details This macro get previous reset source is from CPU reset.
\r
2926 #define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
\r
2929 * @brief Get reset source is from LVR Reset
\r
2931 * @retval 0 Previous reset source is not from Low-Voltage-Reset
\r
2932 * @retval >=1 Previous reset source is from Low-Voltage-Reset
\r
2933 * @details This macro get previous reset source is from Low-Voltage-Reset.
\r
2935 #define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
\r
2938 * @brief Get reset source is from Power-on Reset
\r
2940 * @retval 0 Previous reset source is not from Power-on Reset
\r
2941 * @retval >=1 Previous reset source is from Power-on Reset
\r
2942 * @details This macro get previous reset source is from Power-on Reset.
\r
2944 #define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
\r
2947 * @brief Get reset source is from reset pin reset
\r
2949 * @retval 0 Previous reset source is not from reset pin reset
\r
2950 * @retval >=1 Previous reset source is from reset pin reset
\r
2951 * @details This macro get previous reset source is from reset pin reset.
\r
2953 #define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
\r
2956 * @brief Get reset source is from system reset
\r
2958 * @retval 0 Previous reset source is not from system reset
\r
2959 * @retval >=1 Previous reset source is from system reset
\r
2960 * @details This macro get previous reset source is from system reset.
\r
2962 #define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
\r
2965 * @brief Get reset source is from window watch dog reset
\r
2967 * @retval 0 Previous reset source is not from window watch dog reset
\r
2968 * @retval >=1 Previous reset source is from window watch dog reset
\r
2969 * @details This macro get previous reset source is from window watch dog reset.
\r
2971 #define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
\r
2974 * @brief Disable Low-Voltage-Reset function
\r
2977 * @details This macro disable Low-Voltage-Reset function.
\r
2978 * The register write-protection function should be disabled before using this macro.
\r
2980 #define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
\r
2983 * @brief Enable Low-Voltage-Reset function
\r
2986 * @details This macro enable Low-Voltage-Reset function.
\r
2987 * The register write-protection function should be disabled before using this macro.
\r
2989 #define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
\r
2992 * @brief Disable Power-on Reset function
\r
2995 * @details This macro disable Power-on Reset function.
\r
2996 * The register write-protection function should be disabled before using this macro.
\r
2998 #define SYS_DISABLE_POR() (SYS->PORCTL0 = 0x5AA5)
\r
3001 * @brief Enable Power-on Reset function
\r
3004 * @details This macro enable Power-on Reset function.
\r
3005 * The register write-protection function should be disabled before using this macro.
\r
3007 #define SYS_ENABLE_POR() (SYS->PORCTL0 = 0)
\r
3010 * @brief Clear reset source flag
\r
3011 * @param[in] u32RstSrc is reset source. Including :
\r
3012 * - \ref SYS_RSTSTS_PORF_Msk
\r
3013 * - \ref SYS_RSTSTS_PINRF_Msk
\r
3014 * - \ref SYS_RSTSTS_WDTRF_Msk
\r
3015 * - \ref SYS_RSTSTS_LVRF_Msk
\r
3016 * - \ref SYS_RSTSTS_BODRF_Msk
\r
3017 * - \ref SYS_RSTSTS_SYSRF_Msk
\r
3018 * - \ref SYS_RSTSTS_CPURF_Msk
\r
3019 * - \ref SYS_RSTSTS_CPULKRF_Msk
\r
3021 * @details This macro clear reset source flag.
\r
3023 #define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
\r
3026 /*---------------------------------------------------------------------------------------------------------*/
\r
3027 /* static inline functions */
\r
3028 /*---------------------------------------------------------------------------------------------------------*/
\r
3029 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
\r
3030 __STATIC_INLINE void SYS_UnlockReg(void);
\r
3031 __STATIC_INLINE void SYS_LockReg(void);
\r
3035 * @brief Disable register write-protection function
\r
3038 * @details This function disable register write-protection function.
\r
3039 * To unlock the protected register to allow write access.
\r
3041 __STATIC_INLINE void SYS_UnlockReg(void)
\r
3045 SYS->REGLCTL = 0x59UL;
\r
3046 SYS->REGLCTL = 0x16UL;
\r
3047 SYS->REGLCTL = 0x88UL;
\r
3049 while(SYS->REGLCTL == 0UL);
\r
3053 * @brief Enable register write-protection function
\r
3056 * @details This function is used to enable register write-protection function.
\r
3057 * To lock the protected register to forbid write access.
\r
3059 __STATIC_INLINE void SYS_LockReg(void)
\r
3061 SYS->REGLCTL = 0UL;
\r
3065 void SYS_ClearResetSrc(uint32_t u32Src);
\r
3066 uint32_t SYS_GetBODStatus(void);
\r
3067 uint32_t SYS_GetResetSrc(void);
\r
3068 uint32_t SYS_IsRegLocked(void);
\r
3069 uint32_t SYS_ReadPDID(void);
\r
3070 void SYS_ResetChip(void);
\r
3071 void SYS_ResetCPU(void);
\r
3072 void SYS_ResetModule(uint32_t u32ModuleIndex);
\r
3073 void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
\r
3074 void SYS_DisableBOD(void);
\r
3075 void SYS_SetPowerLevel(uint32_t u32PowerLevel);
\r
3076 uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator);
\r
3077 void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode);
\r
3078 void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode);
\r
3081 /*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
\r
3083 /*@}*/ /* end of group SYS_Driver */
\r
3085 /*@}*/ /* end of group Standard_Driver */
\r
3088 #ifdef __cplusplus
\r
3092 #endif /* __SYS_H__ */
\r
3095 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
\r
projects / freertos / blob