2 ******************************************************************************
\r
3 * @file stm32l1xx_hal_rcc_ex.h
\r
4 * @author MCD Application Team
\r
5 * @brief Header file of RCC HAL Extension module.
\r
6 ******************************************************************************
\r
9 * <h2><center>© Copyright(c) 2017 STMicroelectronics.
\r
10 * All rights reserved.</center></h2>
\r
12 * This software component is licensed by ST under BSD 3-Clause license,
\r
13 * the "License"; You may not use this file except in compliance with the
\r
14 * License. You may obtain a copy of the License at:
\r
15 * opensource.org/licenses/BSD-3-Clause
\r
17 ******************************************************************************
\r
20 /* Define to prevent recursive inclusion -------------------------------------*/
\r
21 #ifndef __STM32L1xx_HAL_RCC_EX_H
\r
22 #define __STM32L1xx_HAL_RCC_EX_H
\r
28 /* Includes ------------------------------------------------------------------*/
\r
29 #include "stm32l1xx_hal_def.h"
\r
31 /** @addtogroup STM32L1xx_HAL_Driver
\r
35 /** @addtogroup RCCEx
\r
39 /** @addtogroup RCCEx_Private_Constants
\r
43 #if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\
\r
44 || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
45 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
46 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
47 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\
\r
48 || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
50 /* Alias word address of LSECSSON bit */
\r
51 #define LSECSSON_BITNUMBER RCC_CSR_LSECSSON_Pos
\r
52 #define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U)))
\r
54 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/
\r
60 /** @addtogroup RCCEx_Private_Macros
\r
65 #define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))
\r
67 #else /* Not LCD LINE */
\r
69 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)
\r
77 /* Exported types ------------------------------------------------------------*/
\r
79 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
\r
84 * @brief RCC extended clocks structure definition
\r
88 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
\r
89 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
\r
91 uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
\r
92 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
\r
96 uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
\r
97 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
\r
100 } RCC_PeriphCLKInitTypeDef;
\r
106 /* Exported constants --------------------------------------------------------*/
\r
108 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
\r
112 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
\r
115 #define RCC_PERIPHCLK_RTC (0x00000001U)
\r
119 #define RCC_PERIPHCLK_LCD (0x00000002U)
\r
127 #if defined(RCC_LSECSS_SUPPORT)
\r
128 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
\r
131 #define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
\r
135 #endif /* RCC_LSECSS_SUPPORT */
\r
141 /* Exported macro ------------------------------------------------------------*/
\r
142 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
\r
146 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
\r
147 * @brief Enables or disables the AHB1 peripheral clock.
\r
148 * @note After reset, the peripheral clock (used for registers read/write access)
\r
149 * is disabled and the application software has to enable this clock before
\r
153 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
\r
154 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
155 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
156 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
157 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
158 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
160 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
\r
161 __IO uint32_t tmpreg; \
\r
162 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
\r
163 /* Delay after an RCC peripheral clock enabling */ \
\r
164 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
\r
167 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
\r
169 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
171 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
172 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
173 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
175 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
\r
176 __IO uint32_t tmpreg; \
\r
177 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
\r
178 /* Delay after an RCC peripheral clock enabling */ \
\r
179 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
\r
182 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
\r
183 __IO uint32_t tmpreg; \
\r
184 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
\r
185 /* Delay after an RCC peripheral clock enabling */ \
\r
186 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
\r
190 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
\r
191 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
\r
193 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
195 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
196 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
197 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
198 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
199 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
201 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
\r
202 __IO uint32_t tmpreg; \
\r
203 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
\r
204 /* Delay after an RCC peripheral clock enabling */ \
\r
205 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
\r
209 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
\r
211 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
213 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
214 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
216 #define __HAL_RCC_AES_CLK_ENABLE() do { \
\r
217 __IO uint32_t tmpreg; \
\r
218 SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
\r
219 /* Delay after an RCC peripheral clock enabling */ \
\r
220 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
\r
223 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
\r
225 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
\r
227 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
229 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
\r
230 __IO uint32_t tmpreg; \
\r
231 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
\r
232 /* Delay after an RCC peripheral clock enabling */ \
\r
233 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
\r
236 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
\r
238 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
240 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
\r
241 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
\r
242 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
\r
243 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
244 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
246 #define __HAL_RCC_LCD_CLK_ENABLE() do { \
\r
247 __IO uint32_t tmpreg; \
\r
248 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
\r
249 /* Delay after an RCC peripheral clock enabling */ \
\r
250 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
\r
253 #define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
\r
255 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
257 /** @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
\r
258 * @note After reset, the peripheral clock (used for registers read/write access)
\r
259 * is disabled and the application software has to enable this clock before
\r
262 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
\r
263 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
264 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
265 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
267 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
\r
268 __IO uint32_t tmpreg; \
\r
269 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
\r
270 /* Delay after an RCC peripheral clock enabling */ \
\r
271 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
\r
274 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
\r
276 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
278 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
279 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
280 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
281 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
282 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
284 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
\r
285 __IO uint32_t tmpreg; \
\r
286 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
\r
287 /* Delay after an RCC peripheral clock enabling */ \
\r
288 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
\r
291 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
\r
293 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
295 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
\r
296 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
298 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
\r
299 __IO uint32_t tmpreg; \
\r
300 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
\r
301 /* Delay after an RCC peripheral clock enabling */ \
\r
302 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
\r
305 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
\r
306 __IO uint32_t tmpreg; \
\r
307 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
\r
308 /* Delay after an RCC peripheral clock enabling */ \
\r
309 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
\r
313 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
\r
314 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
\r
316 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
318 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
319 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
320 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\
\r
321 || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
\r
322 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
\r
324 #define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */
\r
325 #define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */
\r
327 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */
\r
329 /** @brief Enables or disables the High Speed APB (APB2) peripheral clock.
\r
330 * @note After reset, the peripheral clock (used for registers read/write access)
\r
331 * is disabled and the application software has to enable this clock before
\r
334 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
336 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
\r
337 __IO uint32_t tmpreg; \
\r
338 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
\r
339 /* Delay after an RCC peripheral clock enabling */ \
\r
340 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
\r
343 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
\r
345 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
352 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
\r
353 * @brief Forces or releases AHB peripheral reset.
\r
356 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
\r
357 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
358 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
359 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
360 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
361 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
363 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
\r
364 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
\r
366 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
368 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
369 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
370 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
372 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
\r
373 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
\r
375 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
\r
376 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
\r
378 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
380 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
381 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
382 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
383 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
384 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
386 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))
\r
387 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))
\r
389 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
391 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
392 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
394 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))
\r
395 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))
\r
397 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
\r
399 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
401 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))
\r
402 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))
\r
404 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
406 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
\r
407 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
\r
408 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
\r
409 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
410 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
412 #define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
\r
413 #define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))
\r
415 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
417 /** @brief Forces or releases APB1 peripheral reset.
\r
419 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
\r
420 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
421 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
422 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
424 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
\r
425 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
\r
427 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
429 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
430 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
431 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
432 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
433 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
435 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
\r
436 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
\r
438 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
440 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
\r
441 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
443 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
\r
444 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
\r
446 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
\r
447 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
\r
449 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
451 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
452 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
453 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
\r
454 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
\r
456 #define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
\r
457 #define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
\r
459 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
\r
461 /** @brief Forces or releases APB2 peripheral reset.
\r
463 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
465 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
\r
466 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
\r
468 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
474 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
\r
475 * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
\r
476 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
477 * power consumption.
\r
478 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
479 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
482 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
\r
483 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
484 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
485 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
486 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
487 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
489 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))
\r
490 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))
\r
492 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
494 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
495 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
496 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
498 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))
\r
499 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))
\r
501 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))
\r
502 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))
\r
504 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
506 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
507 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
508 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
509 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
510 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
512 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))
\r
513 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))
\r
515 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
517 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
519 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))
\r
520 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))
\r
522 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
\r
524 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
526 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))
\r
527 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))
\r
529 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
531 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
\r
532 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
\r
533 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
\r
534 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
535 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
537 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))
\r
538 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))
\r
540 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
542 /** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
\r
543 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
544 * power consumption.
\r
545 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
546 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
548 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
\r
549 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
550 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
551 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
553 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
\r
554 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
\r
556 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
558 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
559 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
560 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
561 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
562 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
564 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
\r
565 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
\r
567 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
569 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
\r
570 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
572 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
\r
573 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
\r
575 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
\r
576 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
\r
578 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
580 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
581 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
582 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
\r
583 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
\r
585 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */
\r
586 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */
\r
588 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
\r
590 /** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
\r
591 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
592 * power consumption.
\r
593 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
594 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
596 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
598 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
\r
599 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
\r
601 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
607 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
\r
608 * @brief Get the enable or disable status of peripheral clock.
\r
609 * @note After reset, the peripheral clock (used for registers read/write access)
\r
610 * is disabled and the application software has to enable this clock before
\r
615 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
\r
616 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
617 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
618 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
619 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
620 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
622 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U)
\r
623 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U)
\r
625 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
627 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
628 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
629 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
631 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U)
\r
632 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U)
\r
633 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U)
\r
634 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U)
\r
636 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
638 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
639 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
640 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
641 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
642 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
644 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U)
\r
645 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U)
\r
647 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
649 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
650 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
652 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U)
\r
653 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U)
\r
655 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
\r
657 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
659 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U)
\r
660 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U)
\r
662 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
664 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
\r
665 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
\r
666 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
\r
667 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
668 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
670 #define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U)
\r
671 #define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U)
\r
673 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
675 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
\r
676 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
677 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
678 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
680 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U)
\r
681 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U)
\r
683 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
685 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
686 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
687 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
688 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
689 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
691 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U)
\r
692 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U)
\r
694 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
696 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
\r
697 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
699 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U)
\r
700 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U)
\r
701 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U)
\r
702 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U)
\r
704 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
706 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
707 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
708 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
\r
709 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
\r
711 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() __HAL_RCC_COMP_IS_CLK_ENABLED()
\r
712 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() __HAL_RCC_COMP_IS_CLK_DISABLED()
\r
714 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
\r
716 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
718 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U)
\r
719 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U)
\r
721 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
727 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status
\r
728 * @brief Get the enable or disable status of peripheral clock during Low Power (Sleep) mode.
\r
729 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
\r
730 * power consumption.
\r
731 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
\r
732 * @note By default, all peripheral clocks are enabled during SLEEP mode.
\r
736 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
\r
737 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
738 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
739 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
740 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
741 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
743 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U)
\r
744 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U)
\r
746 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
748 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
749 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
750 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
752 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U)
\r
753 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U)
\r
754 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U)
\r
755 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U)
\r
757 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
759 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
760 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
761 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
762 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
763 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
765 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U)
\r
766 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U)
\r
768 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
770 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
771 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
773 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U)
\r
774 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U)
\r
776 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
\r
778 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
780 #define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U)
\r
781 #define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U)
\r
783 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
785 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
\r
786 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
\r
787 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
\r
788 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
789 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
791 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U)
\r
792 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U)
\r
794 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
796 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
\r
797 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
798 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
799 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
801 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U)
\r
802 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U)
\r
804 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
806 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
\r
807 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
\r
808 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
\r
809 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
\r
810 || defined(STM32L162xE) || defined(STM32L162xDX)
\r
812 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U)
\r
813 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U)
\r
815 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
817 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
\r
818 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
\r
820 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U)
\r
821 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U)
\r
822 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U)
\r
823 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U)
\r
825 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
\r
827 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
\r
828 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
\r
829 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
\r
830 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
\r
832 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()
\r
833 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()
\r
835 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
\r
837 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
\r
839 #define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U)
\r
840 #define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U)
\r
842 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
\r
849 #if defined(RCC_LSECSS_SUPPORT)
\r
852 * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
\r
855 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
\r
858 * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
\r
861 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
\r
864 * @brief Enable event on RCC LSE CSS EXTI Line 19.
\r
867 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
\r
870 * @brief Disable event on RCC LSE CSS EXTI Line 19.
\r
873 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
\r
877 * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger.
\r
880 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
\r
884 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
\r
887 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
\r
891 * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger.
\r
894 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
\r
897 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
\r
900 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
\r
903 * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
\r
906 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
\r
908 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
\r
909 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
\r
913 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
\r
916 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
\r
918 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
\r
919 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
\r
923 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
\r
924 * @retval EXTI RCC LSE CSS Line Status.
\r
926 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
\r
929 * @brief Clear the RCC LSE CSS EXTI flag.
\r
932 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
\r
935 * @brief Generate a Software interrupt on selected EXTI line.
\r
938 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
\r
940 #endif /* RCC_LSECSS_SUPPORT */
\r
944 /** @defgroup RCCEx_LCD_Configuration LCD Configuration
\r
945 * @brief Macros to configure clock source of LCD peripherals.
\r
949 /** @brief Macro to configures LCD clock (LCDCLK).
\r
950 * @note LCD and RTC use the same configuration
\r
951 * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
\r
952 * LCD clock source.
\r
954 * @param __LCD_CLKSOURCE__ specifies the LCD clock source.
\r
955 * This parameter can be one of the following values:
\r
956 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
\r
957 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
\r
958 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
\r
959 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
\r
960 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
\r
961 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
\r
963 #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
\r
965 /** @brief Macro to get the LCD clock source.
\r
967 #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
\r
969 /** @brief Macro to get the LCD clock pre-scaler.
\r
971 #define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER()
\r
984 /* Exported functions --------------------------------------------------------*/
\r
985 /** @addtogroup RCCEx_Exported_Functions
\r
989 /** @addtogroup RCCEx_Exported_Functions_Group1
\r
993 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
\r
994 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
\r
995 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
\r
997 #if defined(RCC_LSECSS_SUPPORT)
\r
999 void HAL_RCCEx_EnableLSECSS(void);
\r
1000 void HAL_RCCEx_DisableLSECSS(void);
\r
1001 void HAL_RCCEx_EnableLSECSS_IT(void);
\r
1002 void HAL_RCCEx_LSECSS_IRQHandler(void);
\r
1003 void HAL_RCCEx_LSECSS_Callback(void);
\r
1005 #endif /* RCC_LSECSS_SUPPORT */
\r
1023 #ifdef __cplusplus
\r
1027 #endif /* __STM32L1xx_HAL_RCC_EX_H */
\r
1029 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r