2 ******************************************************************************
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3 * @file stm32l1xx_hal_tim.h
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4 * @author MCD Application Team
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5 * @brief Header file of TIM HAL module.
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6 ******************************************************************************
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9 * <h2><center>© Copyright (c) 2016 STMicroelectronics.
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10 * All rights reserved.</center></h2>
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12 * This software component is licensed by ST under BSD 3-Clause license,
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13 * the "License"; You may not use this file except in compliance with the
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14 * License. You may obtain a copy of the License at:
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15 * opensource.org/licenses/BSD-3-Clause
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17 ******************************************************************************
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20 /* Define to prevent recursive inclusion -------------------------------------*/
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21 #ifndef STM32L1xx_HAL_TIM_H
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22 #define STM32L1xx_HAL_TIM_H
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28 /* Includes ------------------------------------------------------------------*/
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29 #include "stm32l1xx_hal_def.h"
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31 /** @addtogroup STM32L1xx_HAL_Driver
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39 /* Exported types ------------------------------------------------------------*/
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40 /** @defgroup TIM_Exported_Types TIM Exported Types
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45 * @brief TIM Time base Configuration Structure definition
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49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
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50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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52 uint32_t CounterMode; /*!< Specifies the counter mode.
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53 This parameter can be a value of @ref TIM_Counter_Mode */
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55 uint32_t Period; /*!< Specifies the period value to be loaded into the active
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56 Auto-Reload Register at the next update event.
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57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
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59 uint32_t ClockDivision; /*!< Specifies the clock division.
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60 This parameter can be a value of @ref TIM_ClockDivision */
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62 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
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63 This parameter can be a value of @ref TIM_AutoReloadPreload */
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64 } TIM_Base_InitTypeDef;
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67 * @brief TIM Output Compare Configuration Structure definition
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71 uint32_t OCMode; /*!< Specifies the TIM mode.
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72 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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74 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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77 uint32_t OCPolarity; /*!< Specifies the output polarity.
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78 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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80 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
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81 This parameter can be a value of @ref TIM_Output_Fast_State
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82 @note This parameter is valid only in PWM1 and PWM2 mode. */
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83 } TIM_OC_InitTypeDef;
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86 * @brief TIM One Pulse Mode Configuration Structure definition
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90 uint32_t OCMode; /*!< Specifies the TIM mode.
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91 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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93 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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94 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
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96 uint32_t OCPolarity; /*!< Specifies the output polarity.
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97 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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99 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
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100 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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102 uint32_t ICSelection; /*!< Specifies the input.
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103 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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105 uint32_t ICFilter; /*!< Specifies the input capture filter.
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106 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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107 } TIM_OnePulse_InitTypeDef;
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110 * @brief TIM Input Capture Configuration Structure definition
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114 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
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115 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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117 uint32_t ICSelection; /*!< Specifies the input.
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118 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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120 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
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121 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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123 uint32_t ICFilter; /*!< Specifies the input capture filter.
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124 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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125 } TIM_IC_InitTypeDef;
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128 * @brief TIM Encoder Configuration Structure definition
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132 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
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133 This parameter can be a value of @ref TIM_Encoder_Mode */
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135 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
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136 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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138 uint32_t IC1Selection; /*!< Specifies the input.
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139 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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141 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
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142 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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144 uint32_t IC1Filter; /*!< Specifies the input capture filter.
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145 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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147 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
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148 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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150 uint32_t IC2Selection; /*!< Specifies the input.
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151 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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153 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
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154 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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156 uint32_t IC2Filter; /*!< Specifies the input capture filter.
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157 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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158 } TIM_Encoder_InitTypeDef;
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161 * @brief Clock Configuration Handle Structure definition
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165 uint32_t ClockSource; /*!< TIM clock sources
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166 This parameter can be a value of @ref TIM_Clock_Source */
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167 uint32_t ClockPolarity; /*!< TIM clock polarity
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168 This parameter can be a value of @ref TIM_Clock_Polarity */
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169 uint32_t ClockPrescaler; /*!< TIM clock prescaler
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170 This parameter can be a value of @ref TIM_Clock_Prescaler */
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171 uint32_t ClockFilter; /*!< TIM clock filter
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172 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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173 } TIM_ClockConfigTypeDef;
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176 * @brief TIM Clear Input Configuration Handle Structure definition
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180 uint32_t ClearInputState; /*!< TIM clear Input state
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181 This parameter can be ENABLE or DISABLE */
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182 uint32_t ClearInputSource; /*!< TIM clear Input sources
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183 This parameter can be a value of @ref TIM_ClearInput_Source */
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184 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
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185 This parameter can be a value of @ref TIM_ClearInput_Polarity */
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186 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
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187 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
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188 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
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189 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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190 } TIM_ClearInputConfigTypeDef;
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193 * @brief TIM Master configuration Structure definition
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197 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
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198 This parameter can be a value of @ref TIM_Master_Mode_Selection */
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199 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
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200 This parameter can be a value of @ref TIM_Master_Slave_Mode */
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201 } TIM_MasterConfigTypeDef;
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204 * @brief TIM Slave configuration Structure definition
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208 uint32_t SlaveMode; /*!< Slave mode selection
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209 This parameter can be a value of @ref TIM_Slave_Mode */
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210 uint32_t InputTrigger; /*!< Input Trigger source
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211 This parameter can be a value of @ref TIM_Trigger_Selection */
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212 uint32_t TriggerPolarity; /*!< Input Trigger polarity
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213 This parameter can be a value of @ref TIM_Trigger_Polarity */
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214 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
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215 This parameter can be a value of @ref TIM_Trigger_Prescaler */
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216 uint32_t TriggerFilter; /*!< Input trigger filter
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217 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
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219 } TIM_SlaveConfigTypeDef;
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222 * @brief HAL State structures definition
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226 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
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227 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
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228 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
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229 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
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230 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
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231 } HAL_TIM_StateTypeDef;
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234 * @brief HAL Active channel structures definition
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238 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
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239 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
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240 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
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241 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
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242 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
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243 } HAL_TIM_ActiveChannel;
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246 * @brief TIM Time Base Handle Structure definition
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248 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
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249 typedef struct __TIM_HandleTypeDef
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252 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
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254 TIM_TypeDef *Instance; /*!< Register base address */
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255 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
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256 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
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257 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
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258 This array is accessed by a @ref DMA_Handle_index */
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259 HAL_LockTypeDef Lock; /*!< Locking object */
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260 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
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262 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
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263 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
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264 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
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265 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
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266 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
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267 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
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268 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
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269 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
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270 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
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271 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
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272 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
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273 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
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274 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
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275 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
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276 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
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277 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
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278 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
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279 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
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280 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
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281 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
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282 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
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283 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
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284 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
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285 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
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286 } TIM_HandleTypeDef;
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288 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
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290 * @brief HAL TIM Callback ID enumeration definition
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294 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
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295 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
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296 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
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297 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
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298 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
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299 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
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300 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
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301 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
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302 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
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303 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
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304 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
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305 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
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306 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
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307 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
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308 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
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309 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
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311 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
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312 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
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313 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
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314 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
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315 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
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316 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
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317 } HAL_TIM_CallbackIDTypeDef;
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320 * @brief HAL TIM Callback pointer definition
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322 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
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324 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
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329 /* End of exported types -----------------------------------------------------*/
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331 /* Exported constants --------------------------------------------------------*/
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332 /** @defgroup TIM_Exported_Constants TIM Exported Constants
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336 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
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339 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
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340 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
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341 #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */
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346 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
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349 #define TIM_DMABASE_CR1 0x00000000U
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350 #define TIM_DMABASE_CR2 0x00000001U
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351 #define TIM_DMABASE_SMCR 0x00000002U
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352 #define TIM_DMABASE_DIER 0x00000003U
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353 #define TIM_DMABASE_SR 0x00000004U
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354 #define TIM_DMABASE_EGR 0x00000005U
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355 #define TIM_DMABASE_CCMR1 0x00000006U
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356 #define TIM_DMABASE_CCMR2 0x00000007U
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357 #define TIM_DMABASE_CCER 0x00000008U
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358 #define TIM_DMABASE_CNT 0x00000009U
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359 #define TIM_DMABASE_PSC 0x0000000AU
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360 #define TIM_DMABASE_ARR 0x0000000BU
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361 #define TIM_DMABASE_CCR1 0x0000000DU
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362 #define TIM_DMABASE_CCR2 0x0000000EU
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363 #define TIM_DMABASE_CCR3 0x0000000FU
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364 #define TIM_DMABASE_CCR4 0x00000010U
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365 #define TIM_DMABASE_DCR 0x00000012U
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366 #define TIM_DMABASE_DMAR 0x00000013U
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367 #define TIM_DMABASE_OR 0x00000014U
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372 /** @defgroup TIM_Event_Source TIM Event Source
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375 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
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376 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
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377 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
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378 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
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379 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
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380 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
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385 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
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388 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
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389 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
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390 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
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395 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
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398 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
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399 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
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404 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
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407 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
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408 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
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409 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
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410 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
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415 /** @defgroup TIM_Counter_Mode TIM Counter Mode
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418 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
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419 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
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420 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
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421 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
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422 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
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427 /** @defgroup TIM_ClockDivision TIM Clock Division
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430 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
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431 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
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432 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
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437 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
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440 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
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441 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
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446 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
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449 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
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450 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
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456 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
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459 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
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460 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
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465 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
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468 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
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469 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
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474 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
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477 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
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478 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
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483 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
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486 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
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487 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
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488 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
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493 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
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496 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
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497 connected to IC1, IC2, IC3 or IC4, respectively */
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498 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
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499 connected to IC2, IC1, IC4 or IC3, respectively */
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500 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
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505 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
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508 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
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509 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
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510 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
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511 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
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516 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
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519 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
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520 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
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525 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
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528 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
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529 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
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530 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
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535 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
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538 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
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539 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
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540 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
\r
541 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
\r
542 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
\r
543 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
\r
548 /** @defgroup TIM_DMA_sources TIM DMA Sources
\r
551 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
\r
552 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
\r
553 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
\r
554 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
\r
555 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
\r
556 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
\r
561 /** @defgroup TIM_Flag_definition TIM Flag Definition
\r
564 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
\r
565 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
\r
566 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
\r
567 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
\r
568 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
\r
569 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
\r
570 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
\r
571 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
\r
572 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
\r
573 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
\r
578 /** @defgroup TIM_Channel TIM Channel
\r
581 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
\r
582 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
\r
583 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
\r
584 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
\r
585 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
\r
590 /** @defgroup TIM_Clock_Source TIM Clock Source
\r
593 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
\r
594 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
\r
595 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
\r
596 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
\r
597 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
\r
598 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
\r
599 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
\r
600 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
\r
601 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
\r
602 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
\r
607 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
\r
610 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
\r
611 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
\r
612 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
\r
613 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
\r
614 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
\r
619 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
\r
622 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
\r
623 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
\r
624 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
\r
625 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
\r
630 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
\r
633 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
\r
634 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
\r
639 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
\r
642 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
\r
643 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
\r
644 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
\r
645 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
\r
650 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
\r
653 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
\r
654 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
\r
655 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
\r
656 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
\r
657 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
\r
658 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
\r
659 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
\r
660 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
\r
665 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
\r
668 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
\r
669 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
\r
674 /** @defgroup TIM_Slave_Mode TIM Slave mode
\r
677 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
\r
678 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
\r
679 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
\r
680 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
\r
681 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
\r
686 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
\r
689 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
\r
690 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
\r
691 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
\r
692 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
\r
693 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
\r
694 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
\r
695 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
\r
696 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
\r
701 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
\r
704 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
\r
705 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
\r
706 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
\r
707 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
\r
708 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
\r
709 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
\r
710 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
\r
711 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
\r
712 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
\r
717 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
\r
720 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
\r
721 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
\r
722 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
\r
723 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
\r
724 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
\r
729 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
\r
732 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
\r
733 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
\r
734 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
\r
735 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
\r
740 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
\r
743 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
\r
744 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
\r
749 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
\r
752 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
753 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
754 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
755 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
756 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
757 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
758 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
759 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
760 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
761 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
762 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
763 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
764 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
765 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
766 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
767 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
768 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
769 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
\r
774 /** @defgroup DMA_Handle_index TIM DMA Handle Index
\r
777 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
\r
778 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
\r
779 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
\r
780 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
\r
781 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
\r
782 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
\r
787 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
\r
790 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
\r
791 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
\r
799 /* End of exported constants -------------------------------------------------*/
\r
801 /* Exported macros -----------------------------------------------------------*/
\r
802 /** @defgroup TIM_Exported_Macros TIM Exported Macros
\r
806 /** @brief Reset TIM handle state.
\r
807 * @param __HANDLE__ TIM handle.
\r
810 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
\r
811 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
\r
812 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
\r
813 (__HANDLE__)->Base_MspInitCallback = NULL; \
\r
814 (__HANDLE__)->Base_MspDeInitCallback = NULL; \
\r
815 (__HANDLE__)->IC_MspInitCallback = NULL; \
\r
816 (__HANDLE__)->IC_MspDeInitCallback = NULL; \
\r
817 (__HANDLE__)->OC_MspInitCallback = NULL; \
\r
818 (__HANDLE__)->OC_MspDeInitCallback = NULL; \
\r
819 (__HANDLE__)->PWM_MspInitCallback = NULL; \
\r
820 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
\r
821 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
\r
822 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
\r
823 (__HANDLE__)->Encoder_MspInitCallback = NULL; \
\r
824 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
\r
827 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
\r
828 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
\r
831 * @brief Enable the TIM peripheral.
\r
832 * @param __HANDLE__ TIM handle
\r
835 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
\r
838 * @brief Disable the TIM peripheral.
\r
839 * @param __HANDLE__ TIM handle
\r
842 #define __HAL_TIM_DISABLE(__HANDLE__) \
\r
844 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
\r
846 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
\r
850 /** @brief Enable the specified TIM interrupt.
\r
851 * @param __HANDLE__ specifies the TIM Handle.
\r
852 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
\r
853 * This parameter can be one of the following values:
\r
854 * @arg TIM_IT_UPDATE: Update interrupt
\r
855 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
\r
856 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
\r
857 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
\r
858 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
\r
859 * @arg TIM_IT_TRIGGER: Trigger interrupt
\r
862 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
\r
864 /** @brief Disable the specified TIM interrupt.
\r
865 * @param __HANDLE__ specifies the TIM Handle.
\r
866 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
\r
867 * This parameter can be one of the following values:
\r
868 * @arg TIM_IT_UPDATE: Update interrupt
\r
869 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
\r
870 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
\r
871 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
\r
872 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
\r
873 * @arg TIM_IT_TRIGGER: Trigger interrupt
\r
876 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
\r
878 /** @brief Enable the specified DMA request.
\r
879 * @param __HANDLE__ specifies the TIM Handle.
\r
880 * @param __DMA__ specifies the TIM DMA request to enable.
\r
881 * This parameter can be one of the following values:
\r
882 * @arg TIM_DMA_UPDATE: Update DMA request
\r
883 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
\r
884 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
\r
885 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
\r
886 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
\r
887 * @arg TIM_DMA_TRIGGER: Trigger DMA request
\r
890 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
\r
892 /** @brief Disable the specified DMA request.
\r
893 * @param __HANDLE__ specifies the TIM Handle.
\r
894 * @param __DMA__ specifies the TIM DMA request to disable.
\r
895 * This parameter can be one of the following values:
\r
896 * @arg TIM_DMA_UPDATE: Update DMA request
\r
897 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
\r
898 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
\r
899 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
\r
900 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
\r
901 * @arg TIM_DMA_TRIGGER: Trigger DMA request
\r
904 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
\r
906 /** @brief Check whether the specified TIM interrupt flag is set or not.
\r
907 * @param __HANDLE__ specifies the TIM Handle.
\r
908 * @param __FLAG__ specifies the TIM interrupt flag to check.
\r
909 * This parameter can be one of the following values:
\r
910 * @arg TIM_FLAG_UPDATE: Update interrupt flag
\r
911 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
\r
912 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
\r
913 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
\r
914 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
\r
915 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
\r
916 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
\r
917 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
\r
918 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
\r
919 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
\r
920 * @retval The new state of __FLAG__ (TRUE or FALSE).
\r
922 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
\r
924 /** @brief Clear the specified TIM interrupt flag.
\r
925 * @param __HANDLE__ specifies the TIM Handle.
\r
926 * @param __FLAG__ specifies the TIM interrupt flag to clear.
\r
927 * This parameter can be one of the following values:
\r
928 * @arg TIM_FLAG_UPDATE: Update interrupt flag
\r
929 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
\r
930 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
\r
931 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
\r
932 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
\r
933 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
\r
934 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
\r
935 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
\r
936 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
\r
937 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
\r
938 * @retval The new state of __FLAG__ (TRUE or FALSE).
\r
940 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
\r
943 * @brief Check whether the specified TIM interrupt source is enabled or not.
\r
944 * @param __HANDLE__ TIM handle
\r
945 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
\r
946 * This parameter can be one of the following values:
\r
947 * @arg TIM_IT_UPDATE: Update interrupt
\r
948 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
\r
949 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
\r
950 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
\r
951 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
\r
952 * @arg TIM_IT_TRIGGER: Trigger interrupt
\r
953 * @retval The state of TIM_IT (SET or RESET).
\r
955 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
\r
957 /** @brief Clear the TIM interrupt pending bits.
\r
958 * @param __HANDLE__ TIM handle
\r
959 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
\r
960 * This parameter can be one of the following values:
\r
961 * @arg TIM_IT_UPDATE: Update interrupt
\r
962 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
\r
963 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
\r
964 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
\r
965 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
\r
966 * @arg TIM_IT_TRIGGER: Trigger interrupt
\r
969 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
\r
972 * @brief Indicates whether or not the TIM Counter is used as downcounter.
\r
973 * @param __HANDLE__ TIM handle.
\r
974 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
\r
975 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
\r
978 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
\r
981 * @brief Set the TIM Prescaler on runtime.
\r
982 * @param __HANDLE__ TIM handle.
\r
983 * @param __PRESC__ specifies the Prescaler new value.
\r
986 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
\r
989 * @brief Set the TIM Counter Register value on runtime.
\r
990 * @param __HANDLE__ TIM handle.
\r
991 * @param __COUNTER__ specifies the Counter register new value.
\r
994 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
\r
997 * @brief Get the TIM Counter Register value on runtime.
\r
998 * @param __HANDLE__ TIM handle.
\r
999 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
\r
1001 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
\r
1002 ((__HANDLE__)->Instance->CNT)
\r
1005 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
\r
1006 * @param __HANDLE__ TIM handle.
\r
1007 * @param __AUTORELOAD__ specifies the Counter register new value.
\r
1010 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
\r
1012 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
\r
1013 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
\r
1017 * @brief Get the TIM Autoreload Register value on runtime.
\r
1018 * @param __HANDLE__ TIM handle.
\r
1019 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
\r
1021 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
\r
1022 ((__HANDLE__)->Instance->ARR)
\r
1025 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
\r
1026 * @param __HANDLE__ TIM handle.
\r
1027 * @param __CKD__ specifies the clock division value.
\r
1028 * This parameter can be one of the following value:
\r
1029 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
\r
1030 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
\r
1031 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
\r
1034 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
\r
1036 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
\r
1037 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
\r
1038 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
\r
1042 * @brief Get the TIM Clock Division value on runtime.
\r
1043 * @param __HANDLE__ TIM handle.
\r
1044 * @retval The clock division can be one of the following values:
\r
1045 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
\r
1046 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
\r
1047 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
\r
1049 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
\r
1050 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
\r
1053 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
\r
1054 * @param __HANDLE__ TIM handle.
\r
1055 * @param __CHANNEL__ TIM Channels to be configured.
\r
1056 * This parameter can be one of the following values:
\r
1057 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1058 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1059 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1060 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1061 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
\r
1062 * This parameter can be one of the following values:
\r
1063 * @arg TIM_ICPSC_DIV1: no prescaler
\r
1064 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
1065 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
1066 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
1069 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
\r
1071 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
\r
1072 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
\r
1076 * @brief Get the TIM Input Capture prescaler on runtime.
\r
1077 * @param __HANDLE__ TIM handle.
\r
1078 * @param __CHANNEL__ TIM Channels to be configured.
\r
1079 * This parameter can be one of the following values:
\r
1080 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
\r
1081 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
\r
1082 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
\r
1083 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
\r
1084 * @retval The input capture prescaler can be one of the following values:
\r
1085 * @arg TIM_ICPSC_DIV1: no prescaler
\r
1086 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
1087 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
1088 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
1090 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
\r
1091 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
\r
1092 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
\r
1093 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
\r
1094 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
\r
1097 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
\r
1098 * @param __HANDLE__ TIM handle.
\r
1099 * @param __CHANNEL__ TIM Channels to be configured.
\r
1100 * This parameter can be one of the following values:
\r
1101 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1102 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1103 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1104 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1105 * @param __COMPARE__ specifies the Capture Compare register new value.
\r
1108 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
\r
1109 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
\r
1110 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
\r
1111 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
\r
1112 ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
\r
1115 * @brief Get the TIM Capture Compare Register value on runtime.
\r
1116 * @param __HANDLE__ TIM handle.
\r
1117 * @param __CHANNEL__ TIM Channel associated with the capture compare register
\r
1118 * This parameter can be one of the following values:
\r
1119 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
\r
1120 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
\r
1121 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
\r
1122 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
\r
1123 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
\r
1125 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
\r
1126 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
\r
1127 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
\r
1128 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
\r
1129 ((__HANDLE__)->Instance->CCR4))
\r
1132 * @brief Set the TIM Output compare preload.
\r
1133 * @param __HANDLE__ TIM handle.
\r
1134 * @param __CHANNEL__ TIM Channels to be configured.
\r
1135 * This parameter can be one of the following values:
\r
1136 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1137 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1138 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1139 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1142 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
\r
1143 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
\r
1144 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
\r
1145 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
\r
1146 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
\r
1149 * @brief Reset the TIM Output compare preload.
\r
1150 * @param __HANDLE__ TIM handle.
\r
1151 * @param __CHANNEL__ TIM Channels to be configured.
\r
1152 * This parameter can be one of the following values:
\r
1153 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1154 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1155 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1156 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1159 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
\r
1160 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
\r
1161 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
\r
1162 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
\r
1163 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
\r
1166 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
\r
1167 * @param __HANDLE__ TIM handle.
\r
1168 * @note When the URS bit of the TIMx_CR1 register is set, only counter
\r
1169 * overflow/underflow generates an update interrupt or DMA request (if
\r
1173 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
\r
1174 ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
\r
1177 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
\r
1178 * @param __HANDLE__ TIM handle.
\r
1179 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
\r
1180 * following events generate an update interrupt or DMA request (if
\r
1182 * _ Counter overflow underflow
\r
1183 * _ Setting the UG bit
\r
1184 * _ Update generation through the slave mode controller
\r
1187 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
\r
1188 ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
\r
1191 * @brief Set the TIM Capture x input polarity on runtime.
\r
1192 * @param __HANDLE__ TIM handle.
\r
1193 * @param __CHANNEL__ TIM Channels to be configured.
\r
1194 * This parameter can be one of the following values:
\r
1195 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
\r
1196 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
\r
1197 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
\r
1198 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
\r
1199 * @param __POLARITY__ Polarity for TIx source
\r
1200 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
\r
1201 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
\r
1202 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
\r
1205 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
\r
1207 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
\r
1208 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
\r
1214 /* End of exported macros ----------------------------------------------------*/
\r
1216 /* Private constants ---------------------------------------------------------*/
\r
1217 /** @defgroup TIM_Private_Constants TIM Private Constants
\r
1220 /* The counter of a timer instance is disabled only if all the CCx and CCxN
\r
1221 channels have been disabled */
\r
1222 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
\r
1226 /* End of private constants --------------------------------------------------*/
\r
1228 /* Private macros ------------------------------------------------------------*/
\r
1229 /** @defgroup TIM_Private_Macros TIM Private Macros
\r
1232 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
\r
1233 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
\r
1234 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))
\r
1236 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
\r
1237 ((__BASE__) == TIM_DMABASE_CR2) || \
\r
1238 ((__BASE__) == TIM_DMABASE_SMCR) || \
\r
1239 ((__BASE__) == TIM_DMABASE_DIER) || \
\r
1240 ((__BASE__) == TIM_DMABASE_SR) || \
\r
1241 ((__BASE__) == TIM_DMABASE_EGR) || \
\r
1242 ((__BASE__) == TIM_DMABASE_CCMR1) || \
\r
1243 ((__BASE__) == TIM_DMABASE_CCMR2) || \
\r
1244 ((__BASE__) == TIM_DMABASE_CCER) || \
\r
1245 ((__BASE__) == TIM_DMABASE_CNT) || \
\r
1246 ((__BASE__) == TIM_DMABASE_PSC) || \
\r
1247 ((__BASE__) == TIM_DMABASE_ARR) || \
\r
1248 ((__BASE__) == TIM_DMABASE_CCR1) || \
\r
1249 ((__BASE__) == TIM_DMABASE_CCR2) || \
\r
1250 ((__BASE__) == TIM_DMABASE_CCR3) || \
\r
1251 ((__BASE__) == TIM_DMABASE_CCR4) || \
\r
1252 ((__BASE__) == TIM_DMABASE_OR))
\r
1254 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
\r
1256 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
\r
1257 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
\r
1258 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
\r
1259 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
\r
1260 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
\r
1262 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
\r
1263 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
\r
1264 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
\r
1266 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
\r
1267 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
\r
1269 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
\r
1270 ((__STATE__) == TIM_OCFAST_ENABLE))
\r
1272 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
\r
1273 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
\r
1275 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
\r
1276 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
\r
1277 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
\r
1279 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
\r
1280 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
\r
1281 ((__SELECTION__) == TIM_ICSELECTION_TRC))
\r
1283 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
\r
1284 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
\r
1285 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
\r
1286 ((__PRESCALER__) == TIM_ICPSC_DIV8))
\r
1288 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
\r
1289 ((__MODE__) == TIM_OPMODE_REPETITIVE))
\r
1291 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
\r
1292 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
\r
1293 ((__MODE__) == TIM_ENCODERMODE_TI12))
\r
1295 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
\r
1297 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
1298 ((__CHANNEL__) == TIM_CHANNEL_2) || \
\r
1299 ((__CHANNEL__) == TIM_CHANNEL_3) || \
\r
1300 ((__CHANNEL__) == TIM_CHANNEL_4) || \
\r
1301 ((__CHANNEL__) == TIM_CHANNEL_ALL))
\r
1303 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
\r
1304 ((__CHANNEL__) == TIM_CHANNEL_2))
\r
1306 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
\r
1307 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
\r
1308 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
\r
1309 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
\r
1310 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
\r
1311 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
\r
1312 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
\r
1313 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
\r
1314 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
\r
1315 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
\r
1317 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
\r
1318 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
\r
1319 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
\r
1320 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
\r
1321 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
\r
1323 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
\r
1324 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
\r
1325 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
\r
1326 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
\r
1328 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
\r
1330 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
\r
1331 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
\r
1333 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
\r
1334 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
\r
1335 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
\r
1336 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
\r
1338 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
\r
1340 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
\r
1341 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
\r
1342 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
\r
1343 ((__SOURCE__) == TIM_TRGO_OC1) || \
\r
1344 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
\r
1345 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
\r
1346 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
\r
1347 ((__SOURCE__) == TIM_TRGO_OC4REF))
\r
1349 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
\r
1350 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
\r
1352 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
\r
1353 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
\r
1354 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
\r
1355 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
\r
1356 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
\r
1358 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
\r
1359 ((__MODE__) == TIM_OCMODE_PWM2))
\r
1361 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
\r
1362 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
\r
1363 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
\r
1364 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
\r
1365 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
\r
1366 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
\r
1368 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
\r
1369 ((__SELECTION__) == TIM_TS_ITR1) || \
\r
1370 ((__SELECTION__) == TIM_TS_ITR2) || \
\r
1371 ((__SELECTION__) == TIM_TS_ITR3) || \
\r
1372 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
\r
1373 ((__SELECTION__) == TIM_TS_TI1FP1) || \
\r
1374 ((__SELECTION__) == TIM_TS_TI2FP2) || \
\r
1375 ((__SELECTION__) == TIM_TS_ETRF))
\r
1377 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
\r
1378 ((__SELECTION__) == TIM_TS_ITR1) || \
\r
1379 ((__SELECTION__) == TIM_TS_ITR2) || \
\r
1380 ((__SELECTION__) == TIM_TS_ITR3) || \
\r
1381 ((__SELECTION__) == TIM_TS_NONE))
\r
1383 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
\r
1384 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
\r
1385 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
\r
1386 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
\r
1387 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
\r
1389 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
\r
1390 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
\r
1391 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
\r
1392 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
\r
1394 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
\r
1396 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
\r
1397 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
\r
1399 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
\r
1400 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
\r
1401 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
\r
1402 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
\r
1403 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
\r
1404 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
\r
1405 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
\r
1406 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
\r
1407 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
\r
1408 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
\r
1409 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
\r
1410 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
\r
1411 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
\r
1412 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
\r
1413 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
\r
1414 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
\r
1415 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
\r
1416 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
\r
1418 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
\r
1420 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
\r
1422 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
\r
1423 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
\r
1424 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
\r
1425 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
\r
1426 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
\r
1428 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
\r
1429 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
\r
1430 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
\r
1431 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
\r
1432 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
\r
1434 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
\r
1435 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
\r
1436 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
\r
1437 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
\r
1438 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
\r
1440 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
\r
1441 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
\r
1442 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
\r
1443 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
\r
1444 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
\r
1449 /* End of private macros -----------------------------------------------------*/
\r
1451 /* Include TIM HAL Extended module */
\r
1452 #include "stm32l1xx_hal_tim_ex.h"
\r
1454 /* Exported functions --------------------------------------------------------*/
\r
1455 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
\r
1459 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
\r
1460 * @brief Time Base functions
\r
1463 /* Time Base functions ********************************************************/
\r
1464 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
\r
1465 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
\r
1466 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
\r
1467 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
\r
1468 /* Blocking mode: Polling */
\r
1469 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
\r
1470 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
\r
1471 /* Non-Blocking mode: Interrupt */
\r
1472 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
\r
1473 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
\r
1474 /* Non-Blocking mode: DMA */
\r
1475 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
\r
1476 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
\r
1481 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
\r
1482 * @brief TIM Output Compare functions
\r
1485 /* Timer Output Compare functions *********************************************/
\r
1486 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
\r
1487 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
\r
1488 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
\r
1489 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
\r
1490 /* Blocking mode: Polling */
\r
1491 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1492 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1493 /* Non-Blocking mode: Interrupt */
\r
1494 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1495 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1496 /* Non-Blocking mode: DMA */
\r
1497 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
\r
1498 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1503 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
\r
1504 * @brief TIM PWM functions
\r
1507 /* Timer PWM functions ********************************************************/
\r
1508 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
\r
1509 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
\r
1510 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
\r
1511 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
\r
1512 /* Blocking mode: Polling */
\r
1513 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1514 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1515 /* Non-Blocking mode: Interrupt */
\r
1516 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1517 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1518 /* Non-Blocking mode: DMA */
\r
1519 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
\r
1520 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1525 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
\r
1526 * @brief TIM Input Capture functions
\r
1529 /* Timer Input Capture functions **********************************************/
\r
1530 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
\r
1531 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
\r
1532 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
\r
1533 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
\r
1534 /* Blocking mode: Polling */
\r
1535 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1536 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1537 /* Non-Blocking mode: Interrupt */
\r
1538 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1539 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1540 /* Non-Blocking mode: DMA */
\r
1541 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
\r
1542 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1547 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
\r
1548 * @brief TIM One Pulse functions
\r
1551 /* Timer One Pulse functions **************************************************/
\r
1552 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
\r
1553 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
\r
1554 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
\r
1555 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
\r
1556 /* Blocking mode: Polling */
\r
1557 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1558 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1559 /* Non-Blocking mode: Interrupt */
\r
1560 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1561 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
\r
1566 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
\r
1567 * @brief TIM Encoder functions
\r
1570 /* Timer Encoder functions ****************************************************/
\r
1571 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
\r
1572 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
\r
1573 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
\r
1574 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
\r
1575 /* Blocking mode: Polling */
\r
1576 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1577 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1578 /* Non-Blocking mode: Interrupt */
\r
1579 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1580 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1581 /* Non-Blocking mode: DMA */
\r
1582 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
\r
1583 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1588 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
\r
1589 * @brief IRQ handler management
\r
1592 /* Interrupt Handler functions ***********************************************/
\r
1593 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
\r
1598 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
\r
1599 * @brief Peripheral Control functions
\r
1602 /* Control functions *********************************************************/
\r
1603 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
\r
1604 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
\r
1605 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
\r
1606 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
\r
1607 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
\r
1608 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
\r
1609 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
\r
1610 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
\r
1611 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
\r
1612 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
\r
1613 uint32_t *BurstBuffer, uint32_t BurstLength);
\r
1614 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
\r
1615 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
\r
1616 uint32_t *BurstBuffer, uint32_t BurstLength);
\r
1617 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
\r
1618 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
\r
1619 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
\r
1624 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
\r
1625 * @brief TIM Callbacks functions
\r
1628 /* Callback in non blocking modes (Interrupt and DMA) *************************/
\r
1629 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
\r
1630 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
\r
1631 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
\r
1632 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
\r
1633 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
\r
1634 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
\r
1635 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
\r
1636 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
\r
1637 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
\r
1638 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
\r
1640 /* Callbacks Register/UnRegister functions ***********************************/
\r
1641 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
\r
1642 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
\r
1643 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
\r
1644 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
\r
1650 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
\r
1651 * @brief Peripheral State functions
\r
1654 /* Peripheral State functions ************************************************/
\r
1655 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
\r
1656 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
\r
1657 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
\r
1658 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
\r
1659 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
\r
1660 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
\r
1668 /* End of exported functions -------------------------------------------------*/
\r
1670 /* Private functions----------------------------------------------------------*/
\r
1671 /** @defgroup TIM_Private_Functions TIM Private Functions
\r
1674 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
\r
1675 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
\r
1676 void TIM_DMAError(DMA_HandleTypeDef *hdma);
\r
1677 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
\r
1678 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
\r
1680 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
\r
1681 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
\r
1682 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
\r
1687 /* End of private functions --------------------------------------------------*/
\r
1697 #ifdef __cplusplus
\r
1701 #endif /* STM32L1xx_HAL_TIM_H */
\r
1703 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r