1 /******************************************************************************
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31 ******************************************************************************/
32 /*****************************************************************************/
36 * @addtogroup bram_v4_0
39 * This header file contains identifiers and driver functions (or
40 * macros) that can be used to access the device. The user should refer to the
41 * hardware device specification for more details of the device operation.
44 * MODIFICATION HISTORY:
46 * Ver Who Date Changes
47 * ----- ---- -------- -----------------------------------------------
48 * 1.00a sa 24/11/10 First release
51 ******************************************************************************/
52 #ifndef XBRAM_HW_H /* prevent circular inclusions */
53 #define XBRAM_HW_H /* by using protection macros */
59 /***************************** Include Files *********************************/
61 #include "xil_types.h"
62 #include "xil_assert.h"
65 /************************** Constant Definitions *****************************/
69 * Register offsets for this device.
73 #define XBRAM_ECC_STATUS_OFFSET 0x0 /**< ECC status Register */
74 #define XBRAM_ECC_EN_IRQ_OFFSET 0x4 /**< ECC interrupt enable Register */
75 #define XBRAM_ECC_ON_OFF_OFFSET 0x8 /**< ECC on/off register */
76 #define XBRAM_CE_CNT_OFFSET 0xC /**< Correctable error counter Register */
78 #define XBRAM_CE_FFD_0_OFFSET 0x100 /**< Correctable error first failing
79 * data Register, 31-0 */
80 #define XBRAM_CE_FFD_1_OFFSET 0x104 /**< Correctable error first failing
81 * data Register, 63-32 */
82 #define XBRAM_CE_FFD_2_OFFSET 0x108 /**< Correctable error first failing
83 * data Register, 95-64 */
84 #define XBRAM_CE_FFD_3_OFFSET 0x10C /**< Correctable error first failing
85 * data Register, 127-96 */
86 #define XBRAM_CE_FFD_4_OFFSET 0x110 /**< Correctable error first failing
87 * data Register, 159-128 */
88 #define XBRAM_CE_FFD_5_OFFSET 0x114 /**< Correctable error first failing
89 * data Register, 191-160 */
90 #define XBRAM_CE_FFD_6_OFFSET 0x118 /**< Correctable error first failing
91 * data Register, 223-192 */
92 #define XBRAM_CE_FFD_7_OFFSET 0x11C /**< Correctable error first failing
93 * data Register, 255-224 */
94 #define XBRAM_CE_FFD_8_OFFSET 0x120 /**< Correctable error first failing
95 * data Register, 287-256 */
96 #define XBRAM_CE_FFD_9_OFFSET 0x124 /**< Correctable error first failing
97 * data Register, 319-288 */
98 #define XBRAM_CE_FFD_10_OFFSET 0x128 /**< Correctable error first failing
99 * data Register, 351-320 */
100 #define XBRAM_CE_FFD_11_OFFSET 0x12C /**< Correctable error first failing
101 * data Register, 383-352 */
102 #define XBRAM_CE_FFD_12_OFFSET 0x130 /**< Correctable error first failing
103 * data Register, 415-384 */
104 #define XBRAM_CE_FFD_13_OFFSET 0x134 /**< Correctable error first failing
105 * data Register, 447-416 */
106 #define XBRAM_CE_FFD_14_OFFSET 0x138 /**< Correctable error first failing
107 * data Register, 479-448 */
108 #define XBRAM_CE_FFD_15_OFFSET 0x13C /**< Correctable error first failing
109 * data Register, 511-480 */
110 #define XBRAM_CE_FFD_16_OFFSET 0x140 /**< Correctable error first failing
111 * data Register, 543-512 */
112 #define XBRAM_CE_FFD_17_OFFSET 0x144 /**< Correctable error first failing
113 * data Register, 575-544 */
114 #define XBRAM_CE_FFD_18_OFFSET 0x148 /**< Correctable error first failing
115 * data Register, 607-576 */
116 #define XBRAM_CE_FFD_19_OFFSET 0x14C /**< Correctable error first failing
117 * data Register, 639-608 */
118 #define XBRAM_CE_FFD_20_OFFSET 0x150 /**< Correctable error first failing
119 * data Register, 671-640 */
120 #define XBRAM_CE_FFD_21_OFFSET 0x154 /**< Correctable error first failing
121 * data Register, 703-672 */
122 #define XBRAM_CE_FFD_22_OFFSET 0x158 /**< Correctable error first failing
123 * data Register, 735-704 */
124 #define XBRAM_CE_FFD_23_OFFSET 0x15C /**< Correctable error first failing
125 * data Register, 767-736 */
126 #define XBRAM_CE_FFD_24_OFFSET 0x160 /**< Correctable error first failing
127 * data Register, 799-768 */
128 #define XBRAM_CE_FFD_25_OFFSET 0x164 /**< Correctable error first failing
129 * data Register, 831-800 */
130 #define XBRAM_CE_FFD_26_OFFSET 0x168 /**< Correctable error first failing
131 * data Register, 863-832 */
132 #define XBRAM_CE_FFD_27_OFFSET 0x16C /**< Correctable error first failing
133 * data Register, 895-864 */
134 #define XBRAM_CE_FFD_28_OFFSET 0x170 /**< Correctable error first failing
135 * data Register, 927-896 */
136 #define XBRAM_CE_FFD_29_OFFSET 0x174 /**< Correctable error first failing
137 * data Register, 959-928 */
138 #define XBRAM_CE_FFD_30_OFFSET 0x178 /**< Correctable error first failing
139 * data Register, 991-960 */
140 #define XBRAM_CE_FFD_31_OFFSET 0x17C /**< Correctable error first failing
141 * data Register, 1023-992 */
143 #define XBRAM_CE_FFE_0_OFFSET 0x180 /**< Correctable error first failing
144 * ECC Register, 31-0 */
145 #define XBRAM_CE_FFE_1_OFFSET 0x184 /**< Correctable error first failing
146 * ECC Register, 63-32 */
147 #define XBRAM_CE_FFE_2_OFFSET 0x188 /**< Correctable error first failing
148 * ECC Register, 95-64 */
149 #define XBRAM_CE_FFE_3_OFFSET 0x18C /**< Correctable error first failing
150 * ECC Register, 127-96 */
151 #define XBRAM_CE_FFE_4_OFFSET 0x190 /**< Correctable error first failing
152 * ECC Register, 159-128 */
153 #define XBRAM_CE_FFE_5_OFFSET 0x194 /**< Correctable error first failing
154 * ECC Register, 191-160 */
155 #define XBRAM_CE_FFE_6_OFFSET 0x198 /**< Correctable error first failing
156 * ECC Register, 223-192 */
157 #define XBRAM_CE_FFE_7_OFFSET 0x19C /**< Correctable error first failing
158 * ECC Register, 255-224 */
160 #define XBRAM_CE_FFA_0_OFFSET 0x1C0 /**< Correctable error first failing
161 * address Register 31-0 */
162 #define XBRAM_CE_FFA_1_OFFSET 0x1C4 /**< Correctable error first failing
163 * address Register 63-32 */
165 #define XBRAM_UE_FFD_0_OFFSET 0x200 /**< Uncorrectable error first failing
166 * data Register, 31-0 */
167 #define XBRAM_UE_FFD_1_OFFSET 0x204 /**< Uncorrectable error first failing
168 * data Register, 63-32 */
169 #define XBRAM_UE_FFD_2_OFFSET 0x208 /**< Uncorrectable error first failing
170 * data Register, 95-64 */
171 #define XBRAM_UE_FFD_3_OFFSET 0x20C /**< Uncorrectable error first failing
172 * data Register, 127-96 */
173 #define XBRAM_UE_FFD_4_OFFSET 0x210 /**< Uncorrectable error first failing
174 * data Register, 159-128 */
175 #define XBRAM_UE_FFD_5_OFFSET 0x214 /**< Uncorrectable error first failing
176 * data Register, 191-160 */
177 #define XBRAM_UE_FFD_6_OFFSET 0x218 /**< Uncorrectable error first failing
178 * data Register, 223-192 */
179 #define XBRAM_UE_FFD_7_OFFSET 0x21C /**< Uncorrectable error first failing
180 * data Register, 255-224 */
181 #define XBRAM_UE_FFD_8_OFFSET 0x220 /**< Uncorrectable error first failing
182 * data Register, 287-256 */
183 #define XBRAM_UE_FFD_9_OFFSET 0x224 /**< Uncorrectable error first failing
184 * data Register, 319-288 */
185 #define XBRAM_UE_FFD_10_OFFSET 0x228 /**< Uncorrectable error first failing
186 * data Register, 351-320 */
187 #define XBRAM_UE_FFD_11_OFFSET 0x22C /**< Uncorrectable error first failing
188 * data Register, 383-352 */
189 #define XBRAM_UE_FFD_12_OFFSET 0x230 /**< Uncorrectable error first failing
190 * data Register, 415-384 */
191 #define XBRAM_UE_FFD_13_OFFSET 0x234 /**< Uncorrectable error first failing
192 * data Register, 447-416 */
193 #define XBRAM_UE_FFD_14_OFFSET 0x238 /**< Uncorrectable error first failing
194 * data Register, 479-448 */
195 #define XBRAM_UE_FFD_15_OFFSET 0x23C /**< Uncorrectable error first failing
196 * data Register, 511-480 */
197 #define XBRAM_UE_FFD_16_OFFSET 0x240 /**< Uncorrectable error first failing
198 * data Register, 543-512 */
199 #define XBRAM_UE_FFD_17_OFFSET 0x244 /**< Uncorrectable error first failing
200 * data Register, 575-544 */
201 #define XBRAM_UE_FFD_18_OFFSET 0x248 /**< Uncorrectable error first failing
202 * data Register, 607-576 */
203 #define XBRAM_UE_FFD_19_OFFSET 0x24C /**< Uncorrectable error first failing
204 * data Register, 639-608 */
205 #define XBRAM_UE_FFD_20_OFFSET 0x250 /**< Uncorrectable error first failing
206 * data Register, 671-640 */
207 #define XBRAM_UE_FFD_21_OFFSET 0x254 /**< Uncorrectable error first failing
208 * data Register, 703-672 */
209 #define XBRAM_UE_FFD_22_OFFSET 0x258 /**< Uncorrectable error first failing
210 * data Register, 735-704 */
211 #define XBRAM_UE_FFD_23_OFFSET 0x25C /**< Uncorrectable error first failing
212 * data Register, 767-736 */
213 #define XBRAM_UE_FFD_24_OFFSET 0x260 /**< Uncorrectable error first failing
214 * data Register, 799-768 */
215 #define XBRAM_UE_FFD_25_OFFSET 0x264 /**< Uncorrectable error first failing
216 * data Register, 831-800 */
217 #define XBRAM_UE_FFD_26_OFFSET 0x268 /**< Uncorrectable error first failing
218 * data Register, 863-832 */
219 #define XBRAM_UE_FFD_27_OFFSET 0x26C /**< Uncorrectable error first failing
220 * data Register, 895-864 */
221 #define XBRAM_UE_FFD_28_OFFSET 0x270 /**< Uncorrectable error first failing
222 * data Register, 927-896 */
223 #define XBRAM_UE_FFD_29_OFFSET 0x274 /**< Uncorrectable error first failing
224 * data Register, 959-928 */
225 #define XBRAM_UE_FFD_30_OFFSET 0x278 /**< Uncorrectable error first failing
226 * data Register, 991-960 */
227 #define XBRAM_UE_FFD_31_OFFSET 0x27C /**< Uncorrectable error first failing
228 * data Register, 1023-992 */
230 #define XBRAM_UE_FFE_0_OFFSET 0x280 /**< Uncorrectable error first failing
231 * ECC Register, 31-0 */
232 #define XBRAM_UE_FFE_1_OFFSET 0x284 /**< Uncorrectable error first failing
233 * ECC Register, 63-32 */
234 #define XBRAM_UE_FFE_2_OFFSET 0x288 /**< Uncorrectable error first failing
235 * ECC Register, 95-64 */
236 #define XBRAM_UE_FFE_3_OFFSET 0x28C /**< Uncorrectable error first failing
237 * ECC Register, 127-96 */
238 #define XBRAM_UE_FFE_4_OFFSET 0x290 /**< Uncorrectable error first failing
239 * ECC Register, 159-128 */
240 #define XBRAM_UE_FFE_5_OFFSET 0x294 /**< Uncorrectable error first failing
241 * ECC Register, 191-160 */
242 #define XBRAM_UE_FFE_6_OFFSET 0x298 /**< Uncorrectable error first failing
243 * ECC Register, 223-192 */
244 #define XBRAM_UE_FFE_7_OFFSET 0x29C /**< Uncorrectable error first failing
245 * ECC Register, 255-224 */
247 #define XBRAM_UE_FFA_0_OFFSET 0x2C0 /**< Uncorrectable error first failing
248 * address Register 31-0 */
249 #define XBRAM_UE_FFA_1_OFFSET 0x2C4 /**< Uncorrectable error first failing
250 * address Register 63-32 */
252 #define XBRAM_FI_D_0_OFFSET 0x300 /**< Fault injection Data Register,
254 #define XBRAM_FI_D_1_OFFSET 0x304 /**< Fault injection Data Register,
256 #define XBRAM_FI_D_2_OFFSET 0x308 /**< Fault injection Data Register,
258 #define XBRAM_FI_D_3_OFFSET 0x30C /**< Fault injection Data Register,
260 #define XBRAM_FI_D_4_OFFSET 0x310 /**< Fault injection Data Register,
262 #define XBRAM_FI_D_5_OFFSET 0x314 /**< Fault injection Data Register,
264 #define XBRAM_FI_D_6_OFFSET 0x318 /**< Fault injection Data Register,
266 #define XBRAM_FI_D_7_OFFSET 0x31C /**< Fault injection Data Register,
268 #define XBRAM_FI_D_8_OFFSET 0x320 /**< Fault injection Data Register,
270 #define XBRAM_FI_D_9_OFFSET 0x324 /**< Fault injection Data Register,
272 #define XBRAM_FI_D_10_OFFSET 0x328 /**< Fault injection Data Register,
274 #define XBRAM_FI_D_11_OFFSET 0x32C /**< Fault injection Data Register,
276 #define XBRAM_FI_D_12_OFFSET 0x330 /**< Fault injection Data Register,
278 #define XBRAM_FI_D_13_OFFSET 0x334 /**< Fault injection Data Register,
280 #define XBRAM_FI_D_14_OFFSET 0x338 /**< Fault injection Data Register,
282 #define XBRAM_FI_D_15_OFFSET 0x33C /**< Fault injection Data Register,
284 #define XBRAM_FI_D_16_OFFSET 0x340 /**< Fault injection Data Register,
286 #define XBRAM_FI_D_17_OFFSET 0x344 /**< Fault injection Data Register,
288 #define XBRAM_FI_D_18_OFFSET 0x348 /**< Fault injection Data Register,
290 #define XBRAM_FI_D_19_OFFSET 0x34C /**< Fault injection Data Register,
292 #define XBRAM_FI_D_20_OFFSET 0x350 /**< Fault injection Data Register,
294 #define XBRAM_FI_D_21_OFFSET 0x354 /**< Fault injection Data Register,
296 #define XBRAM_FI_D_22_OFFSET 0x358 /**< Fault injection Data Register,
298 #define XBRAM_FI_D_23_OFFSET 0x35C /**< Fault injection Data Register,
300 #define XBRAM_FI_D_24_OFFSET 0x360 /**< Fault injection Data Register,
302 #define XBRAM_FI_D_25_OFFSET 0x364 /**< Fault injection Data Register,
304 #define XBRAM_FI_D_26_OFFSET 0x368 /**< Fault injection Data Register,
306 #define XBRAM_FI_D_27_OFFSET 0x36C /**< Fault injection Data Register,
308 #define XBRAM_FI_D_28_OFFSET 0x370 /**< Fault injection Data Register,
310 #define XBRAM_FI_D_29_OFFSET 0x374 /**< Fault injection Data Register,
312 #define XBRAM_FI_D_30_OFFSET 0x378 /**< Fault injection Data Register,
314 #define XBRAM_FI_D_31_OFFSET 0x37C /**< Fault injection Data Register,
317 #define XBRAM_FI_ECC_0_OFFSET 0x380 /**< Fault injection ECC Register,
319 #define XBRAM_FI_ECC_1_OFFSET 0x384 /**< Fault injection ECC Register,
321 #define XBRAM_FI_ECC_2_OFFSET 0x388 /**< Fault injection ECC Register,
323 #define XBRAM_FI_ECC_3_OFFSET 0x38C /**< Fault injection ECC Register,
325 #define XBRAM_FI_ECC_4_OFFSET 0x390 /**< Fault injection ECC Register,
327 #define XBRAM_FI_ECC_5_OFFSET 0x394 /**< Fault injection ECC Register,
329 #define XBRAM_FI_ECC_6_OFFSET 0x398 /**< Fault injection ECC Register,
331 #define XBRAM_FI_ECC_7_OFFSET 0x39C /**< Fault injection ECC Register,
337 /** @name Interrupt Status and Enable Register bitmaps and masks
339 * Bit definitions for the ECC status register and ECC interrupt enable register.
342 #define XBRAM_IR_CE_MASK 0x2 /**< Mask for the correctable error */
343 #define XBRAM_IR_UE_MASK 0x1 /**< Mask for the uncorrectable error */
344 #define XBRAM_IR_ALL_MASK 0x3 /**< Mask of all bits */
348 /**************************** Type Definitions *******************************/
351 /***************** Macros (Inline Functions) Definitions *********************/
353 #define XBram_In32 Xil_In32
354 #define XBram_Out32 Xil_Out32
356 #define XBram_In16 Xil_In16
357 #define XBram_Out16 Xil_Out16
359 #define XBram_In8 Xil_In8
360 #define XBram_Out8 Xil_Out8
363 /****************************************************************************/
366 * Write a value to a BRAM register. A 32 bit write is performed.
368 * @param BaseAddress is the base address of the BRAM device register.
369 * @param RegOffset is the register offset from the base to write to.
370 * @param Data is the data written to the register.
374 * @note C-style signature:
375 * void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
377 ****************************************************************************/
378 #define XBram_WriteReg(BaseAddress, RegOffset, Data) \
379 XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
381 /****************************************************************************/
384 * Read a value from a BRAM register. A 32 bit read is performed.
386 * @param BaseAddress is the base address of the BRAM device registers.
387 * @param RegOffset is the register offset from the base to read from.
389 * @return Data read from the register.
391 * @note C-style signature:
392 * u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
394 ****************************************************************************/
395 #define XBram_ReadReg(BaseAddress, RegOffset) \
396 XBram_In32((BaseAddress) + (RegOffset))
398 /************************** Function Prototypes ******************************/
400 /************************** Variable Definitions *****************************/
408 #endif /* end of protection macro */