1 /*****************************************************************************
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2 * (c) 2014 Microchip Technology Inc. and its subsidiaries.
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3 * You may use this software and any derivatives exclusively with
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4 * Microchip products.
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5 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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6 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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7 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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8 * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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9 * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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10 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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14 * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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15 * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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16 * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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19 *****************************************************************************/
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22 *Interrupt service routines for MIPS using vanilla GCC and MCHP XC32
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24 /** @defgroup MEC14xx ISR
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29 #include "platform.h"
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30 #include "MEC14xx/mec14xx.h"
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31 #include "MEC14xx/mec14xx_girqs.h"
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32 #include "MEC14xx/mec14xx_gpio.h"
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33 #include "MEC14xx/mec14xx_bbled.h"
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34 #include "MEC14xx/mec14xx_trace_func.h"
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37 typedef void (* GIRQ24_FPVU8)(uint8_t);
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40 /* MIPS M14K internal counter is connected to GIRQ24 bit[0]
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41 * It is a simple counter which fires an interrupt when its
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42 * count value is equal to a match value.
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46 #if GIRQ24_DISAGG == 0
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49 void girq24_dflt_handler(uint8_t inum)
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51 JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].EN_CLR = (1ul << inum);
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52 JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << inum);
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55 void __attribute__((weak)) m14k_counter_handler(uint8_t inum)
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61 r = _CP0_GET_COUNT();
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62 r += (M14K_TIMER_COMPARE);
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63 /* Write of CP0.Compare clears status in M14K */
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66 JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
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71 * TODO - FreeRTOS M14K Software Interrupt 0 handler
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72 * is vPortYieldISR in port_asm.S
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73 * vPortYieldISR was designed to be entered directly by the
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74 * CPU not via a higher level ISR handler.
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75 * One work-around is to modify vPortYieldISR to do the work
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76 * of girq24_handler below. It must determine which GIRQ24 source
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77 * was active: M14K counter, SoftIRQ0, or SoftIRQ1.
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79 void __attribute__((weak)) m14k_soft_irq0(uint8_t inum)
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83 JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 1);
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87 void __attribute__((weak)) m14k_soft_irq1(uint8_t inum)
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91 JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 2);
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95 void girq24_b_0_2( void )
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99 d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
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101 if ( d & (1ul << 0) )
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103 m14k_counter_handler(0);
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106 if ( d & (1ul << 2) )
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113 const GIRQ24_FPVU8 girq24_htable[GIRQ24_NUM_SOURCES] =
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115 m14k_counter_handler, /* m14k_counter_handler, */
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116 m14k_soft_irq0, /* m14k_soft_irq0, */
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117 m14k_soft_irq1, /* m14k_soft_irq1 */
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120 void __attribute__((weak, interrupt, nomips16, section(".girqs")))
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126 d = JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].RESULT & (GIRQ24_SRC_MASK);
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129 bitpos = 31 - ((uint8_t)__builtin_clz(d) & 0x1F);
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130 (girq24_htable[bitpos])(bitpos);
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131 d &= ~(1ul << bitpos);
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137 void __attribute__((weak, interrupt, nomips16))
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142 r = _CP0_GET_COUNT();
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143 r += (M14K_TIMER_COMPARE);
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146 JTVIC_GIRQ->REGS[MEC14xx_GIRQ24_ID].SOURCE = (1ul << 0);
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149 void __attribute__((weak, interrupt, nomips16))
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153 _CP0_BIC_CAUSE(0x100ul);
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155 jtvic_clr_source(MEC14xx_GIRQ24_ID, 1);
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158 void __attribute__((weak, interrupt, nomips16))
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162 _CP0_BIC_CAUSE(0x200ul);
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164 jtvic_clr_source(MEC14xx_GIRQ24_ID, 2);
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