1 /*****************************************************************************
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2 * (c) 2014 Microchip Technology Inc. and its subsidiaries.
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3 * You may use this software and any derivatives exclusively with
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4 * Microchip products.
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5 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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6 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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7 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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8 * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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9 * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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10 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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14 * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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15 * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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16 * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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19 *****************************************************************************/
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21 /** @file mec14xx_girqs.h
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22 *MEC14xx Interrupt Table Header
\r
24 /** @defgroup MEC14xx interrupt
\r
29 #ifndef _MEC14XX_GIRQS_H
\r
30 #define _MEC14XX_GIRQS_H
\r
38 #include "mec14xx.h"
\r
39 #include "mec14xx_jtvic.h"
\r
40 #include "mec14xx_girqm.h"
\r
42 #define GIRQ08_SRC00_PRI JTVIC_PRI1
\r
43 #define GIRQ08_SRC01_PRI JTVIC_PRI1
\r
44 #define GIRQ08_SRC02_PRI JTVIC_PRI1
\r
45 #define GIRQ08_SRC03_PRI JTVIC_PRI1
\r
46 #define GIRQ08_SRC04_PRI JTVIC_PRI1
\r
47 #define GIRQ08_SRC05_PRI JTVIC_PRI1
\r
48 #define GIRQ08_SRC06_PRI JTVIC_PRI1
\r
49 #define GIRQ08_SRC07_PRI JTVIC_PRI1
\r
50 #define GIRQ08_SRC08_PRI JTVIC_PRI1
\r
51 #define GIRQ08_SRC09_PRI JTVIC_PRI1
\r
52 #define GIRQ08_SRC10_PRI JTVIC_PRI1
\r
53 #define GIRQ08_SRC11_PRI JTVIC_PRI1
\r
54 #define GIRQ08_SRC12_PRI JTVIC_PRI1
\r
55 #define GIRQ08_SRC13_PRI JTVIC_PRI1
\r
56 #define GIRQ08_SRC14_PRI JTVIC_PRI1
\r
57 #define GIRQ08_SRC15_PRI JTVIC_PRI1
\r
58 #define GIRQ08_SRC16_PRI JTVIC_PRI1
\r
59 #define GIRQ08_SRC17_PRI JTVIC_PRI1
\r
60 #define GIRQ08_SRC18_PRI JTVIC_PRI1
\r
61 #define GIRQ08_SRC19_PRI JTVIC_PRI1
\r
62 #define GIRQ08_SRC20_PRI JTVIC_PRI1
\r
63 #define GIRQ08_SRC21_PRI JTVIC_PRI1
\r
64 #define GIRQ08_SRC22_PRI JTVIC_PRI1
\r
67 #define GIRQ08_PRI_A (JTVIC_PRI_VAL(0, GIRQ08_SRC00_PRI) + \
\r
68 JTVIC_PRI_VAL(1, GIRQ08_SRC01_PRI) + \
\r
69 JTVIC_PRI_VAL(2, GIRQ08_SRC02_PRI) + \
\r
70 JTVIC_PRI_VAL(3, GIRQ08_SRC03_PRI) + \
\r
71 JTVIC_PRI_VAL(4, GIRQ08_SRC04_PRI) + \
\r
72 JTVIC_PRI_VAL(5, GIRQ08_SRC05_PRI) + \
\r
73 JTVIC_PRI_VAL(6, GIRQ08_SRC06_PRI) + \
\r
74 JTVIC_PRI_VAL(7, GIRQ08_SRC07_PRI))
\r
76 #define GIRQ08_PRI_B (JTVIC_PRI_VAL(0, GIRQ08_SRC08_PRI) + \
\r
77 JTVIC_PRI_VAL(1, GIRQ08_SRC09_PRI) + \
\r
78 JTVIC_PRI_VAL(2, GIRQ08_SRC10_PRI) + \
\r
79 JTVIC_PRI_VAL(3, GIRQ08_SRC11_PRI) + \
\r
80 JTVIC_PRI_VAL(4, GIRQ08_SRC12_PRI) + \
\r
81 JTVIC_PRI_VAL(5, GIRQ08_SRC13_PRI) + \
\r
82 JTVIC_PRI_VAL(6, GIRQ08_SRC14_PRI) + \
\r
83 JTVIC_PRI_VAL(7, GIRQ08_SRC15_PRI))
\r
85 #define GIRQ08_PRI_C (JTVIC_PRI_VAL(0, GIRQ08_SRC16_PRI) + \
\r
86 JTVIC_PRI_VAL(1, GIRQ08_SRC17_PRI) + \
\r
87 JTVIC_PRI_VAL(2, GIRQ08_SRC18_PRI) + \
\r
88 JTVIC_PRI_VAL(3, GIRQ08_SRC19_PRI) + \
\r
89 JTVIC_PRI_VAL(4, GIRQ08_SRC20_PRI) + \
\r
90 JTVIC_PRI_VAL(5, GIRQ08_SRC21_PRI) + \
\r
91 JTVIC_PRI_VAL(6, GIRQ08_SRC22_PRI) )
\r
93 #define GIRQ08_PRI_D (0ul)
\r
99 #define GIRQ09_SRC00_PRI JTVIC_PRI1
\r
100 #define GIRQ09_SRC01_PRI JTVIC_PRI1
\r
101 #define GIRQ09_SRC02_PRI JTVIC_PRI1
\r
102 #define GIRQ09_SRC03_PRI JTVIC_PRI1
\r
103 #define GIRQ09_SRC04_PRI JTVIC_PRI1
\r
104 #define GIRQ09_SRC05_PRI JTVIC_PRI1
\r
105 #define GIRQ09_SRC06_PRI JTVIC_PRI1
\r
106 #define GIRQ09_SRC07_PRI JTVIC_PRI1
\r
107 #define GIRQ09_SRC08_PRI JTVIC_PRI1
\r
108 #define GIRQ09_SRC09_PRI JTVIC_PRI1
\r
109 #define GIRQ09_SRC10_PRI JTVIC_PRI1
\r
110 #define GIRQ09_SRC11_PRI JTVIC_PRI1
\r
111 #define GIRQ09_SRC12_PRI JTVIC_PRI1
\r
112 #define GIRQ09_SRC13_PRI JTVIC_PRI1
\r
113 #define GIRQ09_SRC14_PRI JTVIC_PRI1
\r
114 #define GIRQ09_SRC15_PRI JTVIC_PRI1
\r
115 #define GIRQ09_SRC16_PRI JTVIC_PRI1
\r
116 #define GIRQ09_SRC17_PRI JTVIC_PRI1
\r
117 #define GIRQ09_SRC18_PRI JTVIC_PRI1
\r
118 #define GIRQ09_SRC19_PRI JTVIC_PRI1
\r
119 #define GIRQ09_SRC20_PRI JTVIC_PRI1
\r
120 #define GIRQ09_SRC21_PRI JTVIC_PRI1
\r
121 #define GIRQ09_SRC22_PRI JTVIC_PRI1
\r
122 #define GIRQ09_SRC23_PRI JTVIC_PRI1
\r
123 #define GIRQ09_SRC24_PRI JTVIC_PRI1
\r
124 #define GIRQ09_SRC25_PRI JTVIC_PRI1
\r
125 #define GIRQ09_SRC26_PRI JTVIC_PRI1
\r
126 #define GIRQ09_SRC27_PRI JTVIC_PRI1
\r
127 #define GIRQ09_SRC28_PRI JTVIC_PRI1
\r
128 #define GIRQ09_SRC29_PRI JTVIC_PRI1
\r
129 #define GIRQ09_SRC30_PRI JTVIC_PRI1
\r
132 #define GIRQ09_PRI_A (JTVIC_PRI_VAL(0, GIRQ09_SRC00_PRI) + \
\r
133 JTVIC_PRI_VAL(1, GIRQ09_SRC01_PRI) + \
\r
134 JTVIC_PRI_VAL(2, GIRQ09_SRC02_PRI) + \
\r
135 JTVIC_PRI_VAL(3, GIRQ09_SRC03_PRI) + \
\r
136 JTVIC_PRI_VAL(4, GIRQ09_SRC04_PRI) + \
\r
137 JTVIC_PRI_VAL(5, GIRQ09_SRC05_PRI) + \
\r
138 JTVIC_PRI_VAL(6, GIRQ09_SRC06_PRI) + \
\r
139 JTVIC_PRI_VAL(7, GIRQ09_SRC07_PRI))
\r
141 #define GIRQ09_PRI_B (JTVIC_PRI_VAL(0, GIRQ09_SRC08_PRI) + \
\r
142 JTVIC_PRI_VAL(1, GIRQ09_SRC09_PRI) + \
\r
143 JTVIC_PRI_VAL(2, GIRQ09_SRC10_PRI) + \
\r
144 JTVIC_PRI_VAL(3, GIRQ09_SRC11_PRI) + \
\r
145 JTVIC_PRI_VAL(4, GIRQ09_SRC12_PRI) + \
\r
146 JTVIC_PRI_VAL(5, GIRQ09_SRC13_PRI) + \
\r
147 JTVIC_PRI_VAL(6, GIRQ09_SRC14_PRI) + \
\r
148 JTVIC_PRI_VAL(7, GIRQ09_SRC15_PRI))
\r
150 #define GIRQ09_PRI_C (JTVIC_PRI_VAL(0, GIRQ09_SRC16_PRI) + \
\r
151 JTVIC_PRI_VAL(1, GIRQ09_SRC17_PRI) + \
\r
152 JTVIC_PRI_VAL(2, GIRQ09_SRC18_PRI) + \
\r
153 JTVIC_PRI_VAL(3, GIRQ09_SRC19_PRI) + \
\r
154 JTVIC_PRI_VAL(4, GIRQ09_SRC20_PRI) + \
\r
155 JTVIC_PRI_VAL(5, GIRQ09_SRC21_PRI) + \
\r
156 JTVIC_PRI_VAL(6, GIRQ09_SRC22_PRI) + \
\r
157 JTVIC_PRI_VAL(7, GIRQ09_SRC23_PRI))
\r
159 #define GIRQ09_PRI_D (JTVIC_PRI_VAL(0, GIRQ09_SRC24_PRI) + \
\r
160 JTVIC_PRI_VAL(1, GIRQ09_SRC25_PRI) + \
\r
161 JTVIC_PRI_VAL(2, GIRQ09_SRC26_PRI) + \
\r
162 JTVIC_PRI_VAL(3, GIRQ09_SRC27_PRI) + \
\r
163 JTVIC_PRI_VAL(4, GIRQ09_SRC28_PRI) + \
\r
164 JTVIC_PRI_VAL(5, GIRQ09_SRC29_PRI) + \
\r
165 JTVIC_PRI_VAL(6, GIRQ09_SRC30_PRI) )
\r
171 #define GIRQ10_SRC00_PRI JTVIC_PRI1
\r
172 #define GIRQ10_SRC01_PRI JTVIC_PRI1
\r
173 #define GIRQ10_SRC02_PRI JTVIC_PRI1
\r
174 #define GIRQ10_SRC03_PRI JTVIC_PRI1
\r
175 #define GIRQ10_SRC04_PRI JTVIC_PRI1
\r
176 #define GIRQ10_SRC05_PRI JTVIC_PRI1
\r
177 #define GIRQ10_SRC06_PRI JTVIC_PRI1
\r
178 #define GIRQ10_SRC07_PRI JTVIC_PRI1
\r
179 #define GIRQ10_SRC08_PRI JTVIC_PRI1
\r
180 #define GIRQ10_SRC09_PRI JTVIC_PRI1
\r
181 #define GIRQ10_SRC10_PRI JTVIC_PRI1
\r
182 #define GIRQ10_SRC11_PRI JTVIC_PRI1
\r
183 #define GIRQ10_SRC12_PRI JTVIC_PRI7
\r
184 #define GIRQ10_SRC13_PRI JTVIC_PRI1
\r
185 #define GIRQ10_SRC14_PRI JTVIC_PRI1
\r
186 #define GIRQ10_SRC15_PRI JTVIC_PRI1
\r
187 #define GIRQ10_SRC16_PRI JTVIC_PRI1
\r
188 #define GIRQ10_SRC17_PRI JTVIC_PRI1
\r
189 #define GIRQ10_SRC18_PRI JTVIC_PRI1
\r
190 #define GIRQ10_SRC19_PRI JTVIC_PRI1
\r
191 #define GIRQ10_SRC20_PRI JTVIC_PRI1
\r
192 /* Sources [21:22] Reserved */
\r
193 #define GIRQ10_SRC23_PRI JTVIC_PRI1
\r
196 #define GIRQ10_PRI_A (JTVIC_PRI_VAL(0, GIRQ10_SRC00_PRI) + \
\r
197 JTVIC_PRI_VAL(1, GIRQ10_SRC01_PRI) + \
\r
198 JTVIC_PRI_VAL(2, GIRQ10_SRC02_PRI) + \
\r
199 JTVIC_PRI_VAL(3, GIRQ10_SRC03_PRI) + \
\r
200 JTVIC_PRI_VAL(4, GIRQ10_SRC04_PRI) + \
\r
201 JTVIC_PRI_VAL(5, GIRQ10_SRC05_PRI) + \
\r
202 JTVIC_PRI_VAL(6, GIRQ10_SRC06_PRI) + \
\r
203 JTVIC_PRI_VAL(7, GIRQ10_SRC07_PRI))
\r
205 #define GIRQ10_PRI_B (JTVIC_PRI_VAL(0, GIRQ10_SRC08_PRI) + \
\r
206 JTVIC_PRI_VAL(1, GIRQ10_SRC09_PRI) + \
\r
207 JTVIC_PRI_VAL(2, GIRQ10_SRC10_PRI) + \
\r
208 JTVIC_PRI_VAL(3, GIRQ10_SRC11_PRI) + \
\r
209 JTVIC_PRI_VAL(4, GIRQ10_SRC12_PRI) + \
\r
210 JTVIC_PRI_VAL(5, GIRQ10_SRC13_PRI) + \
\r
211 JTVIC_PRI_VAL(6, GIRQ10_SRC14_PRI) + \
\r
212 JTVIC_PRI_VAL(7, GIRQ10_SRC15_PRI))
\r
214 #define GIRQ10_PRI_C (JTVIC_PRI_VAL(0, GIRQ10_SRC16_PRI) + \
\r
215 JTVIC_PRI_VAL(1, GIRQ10_SRC17_PRI) + \
\r
216 JTVIC_PRI_VAL(2, GIRQ10_SRC18_PRI) + \
\r
217 JTVIC_PRI_VAL(3, GIRQ10_SRC19_PRI) + \
\r
218 JTVIC_PRI_VAL(4, GIRQ10_SRC20_PRI) + \
\r
219 JTVIC_PRI_VAL(7, GIRQ10_SRC23_PRI))
\r
221 #define GIRQ10_PRI_D (0ul)
\r
227 /* Source[0] Reserved */
\r
228 #define GIRQ11_SRC01_PRI JTVIC_PRI1
\r
229 #define GIRQ11_SRC02_PRI JTVIC_PRI1
\r
230 #define GIRQ11_SRC03_PRI JTVIC_PRI1
\r
231 #define GIRQ11_SRC04_PRI JTVIC_PRI1
\r
232 #define GIRQ11_SRC05_PRI JTVIC_PRI1
\r
233 #define GIRQ11_SRC06_PRI JTVIC_PRI1
\r
234 #define GIRQ11_SRC07_PRI JTVIC_PRI1
\r
235 #define GIRQ11_SRC08_PRI JTVIC_PRI1
\r
236 #define GIRQ11_SRC09_PRI JTVIC_PRI1
\r
237 #define GIRQ11_SRC10_PRI JTVIC_PRI1
\r
238 #define GIRQ11_SRC11_PRI JTVIC_PRI1
\r
239 #define GIRQ11_SRC12_PRI JTVIC_PRI1
\r
240 #define GIRQ11_SRC13_PRI JTVIC_PRI1
\r
241 #define GIRQ11_SRC14_PRI JTVIC_PRI1
\r
242 #define GIRQ11_SRC15_PRI JTVIC_PRI1
\r
243 #define GIRQ11_SRC16_PRI JTVIC_PRI1
\r
244 #define GIRQ11_SRC17_PRI JTVIC_PRI1
\r
245 #define GIRQ11_SRC18_PRI JTVIC_PRI1
\r
246 #define GIRQ11_SRC19_PRI JTVIC_PRI1
\r
247 #define GIRQ11_SRC20_PRI JTVIC_PRI1
\r
248 #define GIRQ11_SRC21_PRI JTVIC_PRI1
\r
249 #define GIRQ11_SRC22_PRI JTVIC_PRI1
\r
250 #define GIRQ11_SRC23_PRI JTVIC_PRI1
\r
251 #define GIRQ11_SRC24_PRI JTVIC_PRI1
\r
252 #define GIRQ11_SRC25_PRI JTVIC_PRI1
\r
253 #define GIRQ11_SRC26_PRI JTVIC_PRI1
\r
254 #define GIRQ11_SRC27_PRI JTVIC_PRI1
\r
255 #define GIRQ11_SRC28_PRI JTVIC_PRI1
\r
256 #define GIRQ11_SRC29_PRI JTVIC_PRI1
\r
257 #define GIRQ11_SRC30_PRI JTVIC_PRI1
\r
260 #define GIRQ11_PRI_A (JTVIC_PRI_VAL(1, GIRQ11_SRC01_PRI) + \
\r
261 JTVIC_PRI_VAL(2, GIRQ11_SRC02_PRI) + \
\r
262 JTVIC_PRI_VAL(3, GIRQ11_SRC03_PRI) + \
\r
263 JTVIC_PRI_VAL(4, GIRQ11_SRC04_PRI) + \
\r
264 JTVIC_PRI_VAL(5, GIRQ11_SRC05_PRI) + \
\r
265 JTVIC_PRI_VAL(6, GIRQ11_SRC06_PRI) + \
\r
266 JTVIC_PRI_VAL(7, GIRQ11_SRC07_PRI))
\r
268 #define GIRQ11_PRI_B (JTVIC_PRI_VAL(0, GIRQ11_SRC08_PRI) + \
\r
269 JTVIC_PRI_VAL(1, GIRQ11_SRC09_PRI) + \
\r
270 JTVIC_PRI_VAL(2, GIRQ11_SRC10_PRI) + \
\r
271 JTVIC_PRI_VAL(3, GIRQ11_SRC11_PRI) + \
\r
272 JTVIC_PRI_VAL(4, GIRQ11_SRC12_PRI) + \
\r
273 JTVIC_PRI_VAL(5, GIRQ11_SRC13_PRI) + \
\r
274 JTVIC_PRI_VAL(6, GIRQ11_SRC14_PRI) + \
\r
275 JTVIC_PRI_VAL(7, GIRQ11_SRC15_PRI))
\r
277 #define GIRQ11_PRI_C (JTVIC_PRI_VAL(0, GIRQ11_SRC16_PRI) + \
\r
278 JTVIC_PRI_VAL(1, GIRQ11_SRC17_PRI) + \
\r
279 JTVIC_PRI_VAL(2, GIRQ11_SRC18_PRI) + \
\r
280 JTVIC_PRI_VAL(3, GIRQ11_SRC19_PRI) + \
\r
281 JTVIC_PRI_VAL(4, GIRQ11_SRC20_PRI) + \
\r
282 JTVIC_PRI_VAL(5, GIRQ11_SRC21_PRI) + \
\r
283 JTVIC_PRI_VAL(6, GIRQ11_SRC22_PRI) + \
\r
284 JTVIC_PRI_VAL(7, GIRQ11_SRC23_PRI))
\r
286 #define GIRQ11_PRI_D (JTVIC_PRI_VAL(0, GIRQ11_SRC24_PRI) + \
\r
287 JTVIC_PRI_VAL(1, GIRQ11_SRC25_PRI) + \
\r
288 JTVIC_PRI_VAL(2, GIRQ11_SRC26_PRI) + \
\r
289 JTVIC_PRI_VAL(3, GIRQ11_SRC27_PRI) + \
\r
290 JTVIC_PRI_VAL(4, GIRQ11_SRC28_PRI) + \
\r
291 JTVIC_PRI_VAL(5, GIRQ11_SRC29_PRI) + \
\r
292 JTVIC_PRI_VAL(6, GIRQ11_SRC30_PRI) )
\r
299 #define GIRQ12_SRC00_PRI JTVIC_PRI1
\r
300 #define GIRQ12_SRC01_PRI JTVIC_PRI1
\r
301 #define GIRQ12_SRC02_PRI JTVIC_PRI1
\r
304 #define GIRQ12_PRI_A (JTVIC_PRI_VAL(0, GIRQ12_SRC00_PRI) + \
\r
305 JTVIC_PRI_VAL(1, GIRQ12_SRC01_PRI) + \
\r
306 JTVIC_PRI_VAL(2, GIRQ12_SRC02_PRI) )
\r
308 #define GIRQ12_PRI_B (0ul)
\r
309 #define GIRQ12_PRI_C (0ul)
\r
310 #define GIRQ12_PRI_D (0ul)
\r
316 #define GIRQ13_SRC00_PRI JTVIC_PRI1
\r
317 #define GIRQ13_SRC01_PRI JTVIC_PRI1
\r
318 #define GIRQ13_SRC02_PRI JTVIC_PRI1
\r
319 #define GIRQ13_SRC03_PRI JTVIC_PRI1
\r
320 #define GIRQ13_SRC04_PRI JTVIC_PRI1
\r
321 #define GIRQ13_SRC05_PRI JTVIC_PRI1
\r
322 #define GIRQ13_SRC06_PRI JTVIC_PRI1
\r
325 #define GIRQ13_PRI_A (JTVIC_PRI_VAL(0, GIRQ13_SRC00_PRI) + \
\r
326 JTVIC_PRI_VAL(1, GIRQ13_SRC01_PRI) + \
\r
327 JTVIC_PRI_VAL(2, GIRQ13_SRC02_PRI) + \
\r
328 JTVIC_PRI_VAL(3, GIRQ13_SRC03_PRI) + \
\r
329 JTVIC_PRI_VAL(4, GIRQ13_SRC04_PRI) + \
\r
330 JTVIC_PRI_VAL(5, GIRQ13_SRC05_PRI) + \
\r
331 JTVIC_PRI_VAL(6, GIRQ13_SRC06_PRI) )
\r
333 #define GIRQ13_PRI_B (0ul)
\r
334 #define GIRQ13_PRI_C (0ul)
\r
335 #define GIRQ13_PRI_D (0ul)
\r
341 #define GIRQ14_SRC00_PRI JTVIC_PRI1
\r
342 #define GIRQ14_SRC01_PRI JTVIC_PRI1
\r
343 #define GIRQ14_SRC02_PRI JTVIC_PRI1
\r
344 #define GIRQ14_SRC03_PRI JTVIC_PRI1
\r
345 #define GIRQ14_SRC04_PRI JTVIC_PRI1
\r
346 #define GIRQ14_SRC05_PRI JTVIC_PRI1
\r
349 #define GIRQ14_PRI_A (JTVIC_PRI_VAL(0, GIRQ14_SRC00_PRI) + \
\r
350 JTVIC_PRI_VAL(1, GIRQ14_SRC01_PRI) + \
\r
351 JTVIC_PRI_VAL(2, GIRQ14_SRC02_PRI) + \
\r
352 JTVIC_PRI_VAL(3, GIRQ14_SRC03_PRI) + \
\r
353 JTVIC_PRI_VAL(4, GIRQ14_SRC04_PRI) + \
\r
354 JTVIC_PRI_VAL(5, GIRQ14_SRC05_PRI) )
\r
356 #define GIRQ14_PRI_B (0ul)
\r
357 #define GIRQ14_PRI_C (0ul)
\r
358 #define GIRQ14_PRI_D (0ul)
\r
364 #define GIRQ15_SRC00_PRI JTVIC_PRI1
\r
365 #define GIRQ15_SRC01_PRI JTVIC_PRI1
\r
366 #define GIRQ15_SRC02_PRI JTVIC_PRI1
\r
367 #define GIRQ15_SRC03_PRI JTVIC_PRI1
\r
368 #define GIRQ15_SRC04_PRI JTVIC_PRI1
\r
369 #define GIRQ15_SRC05_PRI JTVIC_PRI1
\r
370 #define GIRQ15_SRC06_PRI JTVIC_PRI1
\r
371 #define GIRQ15_SRC07_PRI JTVIC_PRI1
\r
372 #define GIRQ15_SRC08_PRI JTVIC_PRI1
\r
373 #define GIRQ15_SRC09_PRI JTVIC_PRI1
\r
374 #define GIRQ15_SRC10_PRI JTVIC_PRI1
\r
375 #define GIRQ15_SRC11_PRI JTVIC_PRI1
\r
376 #define GIRQ15_SRC12_PRI JTVIC_PRI1
\r
377 #define GIRQ15_SRC13_PRI JTVIC_PRI1
\r
378 #define GIRQ15_SRC14_PRI JTVIC_PRI1
\r
379 #define GIRQ15_SRC15_PRI JTVIC_PRI1
\r
380 #define GIRQ15_SRC16_PRI JTVIC_PRI1
\r
381 #define GIRQ15_SRC17_PRI JTVIC_PRI1
\r
382 #define GIRQ15_SRC18_PRI JTVIC_PRI1
\r
385 #define GIRQ15_PRI_A (JTVIC_PRI_VAL(0, GIRQ15_SRC00_PRI) + \
\r
386 JTVIC_PRI_VAL(1, GIRQ15_SRC01_PRI) + \
\r
387 JTVIC_PRI_VAL(2, GIRQ15_SRC02_PRI) + \
\r
388 JTVIC_PRI_VAL(3, GIRQ15_SRC03_PRI) + \
\r
389 JTVIC_PRI_VAL(4, GIRQ15_SRC04_PRI) + \
\r
390 JTVIC_PRI_VAL(5, GIRQ15_SRC05_PRI) + \
\r
391 JTVIC_PRI_VAL(6, GIRQ15_SRC06_PRI) + \
\r
392 JTVIC_PRI_VAL(7, GIRQ15_SRC07_PRI))
\r
394 #define GIRQ15_PRI_B (JTVIC_PRI_VAL(0, GIRQ15_SRC08_PRI) + \
\r
395 JTVIC_PRI_VAL(1, GIRQ15_SRC09_PRI) + \
\r
396 JTVIC_PRI_VAL(2, GIRQ15_SRC10_PRI) + \
\r
397 JTVIC_PRI_VAL(3, GIRQ15_SRC11_PRI) + \
\r
398 JTVIC_PRI_VAL(4, GIRQ15_SRC12_PRI) + \
\r
399 JTVIC_PRI_VAL(5, GIRQ15_SRC13_PRI) + \
\r
400 JTVIC_PRI_VAL(6, GIRQ15_SRC14_PRI) + \
\r
401 JTVIC_PRI_VAL(7, GIRQ15_SRC15_PRI))
\r
403 #define GIRQ15_PRI_C (JTVIC_PRI_VAL(0, GIRQ15_SRC16_PRI) + \
\r
404 JTVIC_PRI_VAL(1, GIRQ15_SRC17_PRI) + \
\r
405 JTVIC_PRI_VAL(2, GIRQ15_SRC18_PRI) )
\r
407 #define GIRQ15_PRI_D (0ul)
\r
413 #define GIRQ16_SRC00_PRI JTVIC_PRI1
\r
414 #define GIRQ16_SRC01_PRI JTVIC_PRI1
\r
415 #define GIRQ16_SRC02_PRI JTVIC_PRI1
\r
416 #define GIRQ16_SRC03_PRI JTVIC_PRI1
\r
417 #define GIRQ16_SRC04_PRI JTVIC_PRI1
\r
418 #define GIRQ16_SRC05_PRI JTVIC_PRI1
\r
419 #define GIRQ16_SRC06_PRI JTVIC_PRI1
\r
420 #define GIRQ16_SRC07_PRI JTVIC_PRI1
\r
421 #define GIRQ16_SRC08_PRI JTVIC_PRI1
\r
422 #define GIRQ16_SRC09_PRI JTVIC_PRI1
\r
425 #define GIRQ16_PRI_A (JTVIC_PRI_VAL(0, GIRQ16_SRC00_PRI) + \
\r
426 JTVIC_PRI_VAL(1, GIRQ16_SRC01_PRI) + \
\r
427 JTVIC_PRI_VAL(2, GIRQ16_SRC02_PRI) + \
\r
428 JTVIC_PRI_VAL(3, GIRQ16_SRC03_PRI) + \
\r
429 JTVIC_PRI_VAL(4, GIRQ16_SRC04_PRI) + \
\r
430 JTVIC_PRI_VAL(5, GIRQ16_SRC05_PRI) + \
\r
431 JTVIC_PRI_VAL(6, GIRQ16_SRC06_PRI) + \
\r
432 JTVIC_PRI_VAL(7, GIRQ16_SRC07_PRI))
\r
434 #define GIRQ16_PRI_B (JTVIC_PRI_VAL(0, GIRQ16_SRC08_PRI) + \
\r
435 JTVIC_PRI_VAL(1, GIRQ16_SRC09_PRI) )
\r
437 #define GIRQ16_PRI_C (0ul)
\r
438 #define GIRQ16_PRI_D (0ul)
\r
444 #define GIRQ17_SRC00_PRI JTVIC_PRI1
\r
445 #define GIRQ17_SRC01_PRI JTVIC_PRI1
\r
446 #define GIRQ17_SRC02_PRI JTVIC_PRI1
\r
447 #define GIRQ17_SRC03_PRI JTVIC_PRI1
\r
448 #define GIRQ17_SRC04_PRI JTVIC_PRI1
\r
449 #define GIRQ17_SRC05_PRI JTVIC_PRI1
\r
450 #define GIRQ17_SRC06_PRI JTVIC_PRI1
\r
451 #define GIRQ17_SRC07_PRI JTVIC_PRI1
\r
452 #define GIRQ17_SRC08_PRI JTVIC_PRI1
\r
453 #define GIRQ17_SRC09_PRI JTVIC_PRI1
\r
454 #define GIRQ17_SRC10_PRI JTVIC_PRI1
\r
457 #define GIRQ17_PRI_A (JTVIC_PRI_VAL(0, GIRQ17_SRC00_PRI) + \
\r
458 JTVIC_PRI_VAL(1, GIRQ17_SRC01_PRI) + \
\r
459 JTVIC_PRI_VAL(2, GIRQ17_SRC02_PRI) + \
\r
460 JTVIC_PRI_VAL(3, GIRQ17_SRC03_PRI) + \
\r
461 JTVIC_PRI_VAL(4, GIRQ17_SRC04_PRI) + \
\r
462 JTVIC_PRI_VAL(5, GIRQ17_SRC05_PRI) + \
\r
463 JTVIC_PRI_VAL(6, GIRQ17_SRC06_PRI) + \
\r
464 JTVIC_PRI_VAL(7, GIRQ17_SRC07_PRI))
\r
466 #define GIRQ17_PRI_B (JTVIC_PRI_VAL(0, GIRQ17_SRC08_PRI) + \
\r
467 JTVIC_PRI_VAL(1, GIRQ17_SRC09_PRI) + \
\r
468 JTVIC_PRI_VAL(2, GIRQ17_SRC10_PRI) )
\r
470 #define GIRQ17_PRI_C (0ul)
\r
471 #define GIRQ17_PRI_D (0ul)
\r
477 #define GIRQ18_DISAGG (0)
\r
478 #define GIRQ18_SRC00_PRI JTVIC_PRI1
\r
481 #define GIRQ18_PRI_A (JTVIC_PRI_VAL(0, GIRQ18_SRC00_PRI) )
\r
483 #define GIRQ18_PRI_B (0ul)
\r
484 #define GIRQ18_PRI_C (0ul)
\r
485 #define GIRQ18_PRI_D (0ul)
\r
491 #define GIRQ19_SRC00_PRI JTVIC_PRI1
\r
492 #define GIRQ19_SRC01_PRI JTVIC_PRI1
\r
493 #define GIRQ19_SRC02_PRI JTVIC_PRI1
\r
494 #define GIRQ19_SRC03_PRI JTVIC_PRI1
\r
495 #define GIRQ19_SRC04_PRI JTVIC_PRI1
\r
496 #define GIRQ19_SRC05_PRI JTVIC_PRI1
\r
497 #define GIRQ19_SRC06_PRI JTVIC_PRI1
\r
498 #define GIRQ19_SRC07_PRI JTVIC_PRI1
\r
499 #define GIRQ19_SRC08_PRI JTVIC_PRI1
\r
502 #define GIRQ19_PRI_A (JTVIC_PRI_VAL(0, GIRQ19_SRC00_PRI) + \
\r
503 JTVIC_PRI_VAL(1, GIRQ19_SRC01_PRI) + \
\r
504 JTVIC_PRI_VAL(2, GIRQ19_SRC02_PRI) + \
\r
505 JTVIC_PRI_VAL(3, GIRQ19_SRC03_PRI) + \
\r
506 JTVIC_PRI_VAL(4, GIRQ19_SRC04_PRI) + \
\r
507 JTVIC_PRI_VAL(5, GIRQ19_SRC05_PRI) + \
\r
508 JTVIC_PRI_VAL(6, GIRQ19_SRC06_PRI) + \
\r
509 JTVIC_PRI_VAL(7, GIRQ19_SRC07_PRI))
\r
511 #define GIRQ19_PRI_B (JTVIC_PRI_VAL(0, GIRQ19_SRC08_PRI) )
\r
513 #define GIRQ19_PRI_C (0ul)
\r
514 #define GIRQ19_PRI_D (0ul)
\r
520 #define GIRQ20_SRC00_PRI JTVIC_PRI1
\r
521 #define GIRQ20_SRC01_PRI JTVIC_PRI1
\r
522 #define GIRQ20_SRC02_PRI JTVIC_PRI1
\r
523 #define GIRQ20_SRC03_PRI JTVIC_PRI1
\r
524 #define GIRQ20_SRC04_PRI JTVIC_PRI1
\r
525 #define GIRQ20_SRC05_PRI JTVIC_PRI1
\r
528 #define GIRQ20_PRI_A (JTVIC_PRI_VAL(0, GIRQ20_SRC00_PRI) + \
\r
529 JTVIC_PRI_VAL(1, GIRQ20_SRC01_PRI) + \
\r
530 JTVIC_PRI_VAL(2, GIRQ20_SRC02_PRI) + \
\r
531 JTVIC_PRI_VAL(3, GIRQ20_SRC03_PRI) + \
\r
532 JTVIC_PRI_VAL(4, GIRQ20_SRC04_PRI) + \
\r
533 JTVIC_PRI_VAL(5, GIRQ20_SRC05_PRI) )
\r
535 #define GIRQ20_PRI_B (0ul)
\r
536 #define GIRQ20_PRI_C (0ul)
\r
537 #define GIRQ20_PRI_D (0ul)
\r
540 /* GIRQ21 is for Wake purposes. It only wakes IA logic and
\r
541 * does not fire an interrupt to the CPU.
\r
542 * No GIRQ21 sources are defined!
\r
544 #define GIRQ21_DISAGG (0)
\r
545 #define GIRQ21_PRI_A (0ul)
\r
546 #define GIRQ21_PRI_B (0ul)
\r
547 #define GIRQ21_PRI_C (0ul)
\r
548 #define GIRQ21_PRI_D (0ul)
\r
554 #define GIRQ22_SRC00_PRI JTVIC_PRI1
\r
555 #define GIRQ22_SRC01_PRI JTVIC_PRI1
\r
556 #define GIRQ22_SRC02_PRI JTVIC_PRI1
\r
557 #define GIRQ22_SRC03_PRI JTVIC_PRI1
\r
558 #define GIRQ22_SRC04_PRI JTVIC_PRI1
\r
559 #define GIRQ22_SRC05_PRI JTVIC_PRI1
\r
560 #define GIRQ22_SRC06_PRI JTVIC_PRI1
\r
561 #define GIRQ22_SRC07_PRI JTVIC_PRI1
\r
562 #define GIRQ22_SRC08_PRI JTVIC_PRI1
\r
563 #define GIRQ22_SRC09_PRI JTVIC_PRI1
\r
566 #define GIRQ22_PRI_A (JTVIC_PRI_VAL(0, GIRQ22_SRC00_PRI) + \
\r
567 JTVIC_PRI_VAL(1, GIRQ22_SRC01_PRI) + \
\r
568 JTVIC_PRI_VAL(2, GIRQ22_SRC02_PRI) + \
\r
569 JTVIC_PRI_VAL(3, GIRQ22_SRC03_PRI) + \
\r
570 JTVIC_PRI_VAL(4, GIRQ22_SRC04_PRI) + \
\r
571 JTVIC_PRI_VAL(5, GIRQ22_SRC05_PRI) + \
\r
572 JTVIC_PRI_VAL(6, GIRQ22_SRC06_PRI) + \
\r
573 JTVIC_PRI_VAL(7, GIRQ22_SRC07_PRI))
\r
575 #define GIRQ22_PRI_B (JTVIC_PRI_VAL(0, GIRQ22_SRC08_PRI) + \
\r
576 JTVIC_PRI_VAL(1, GIRQ22_SRC09_PRI) )
\r
578 #define GIRQ22_PRI_C (0ul)
\r
579 #define GIRQ22_PRI_D (0ul)
\r
585 #define GIRQ23_SRC00_PRI JTVIC_PRI1
\r
586 #define GIRQ23_SRC01_PRI JTVIC_PRI1
\r
587 #define GIRQ23_SRC02_PRI JTVIC_PRI1
\r
588 #define GIRQ23_SRC03_PRI JTVIC_PRI1
\r
589 #define GIRQ23_SRC04_PRI JTVIC_PRI1
\r
590 #define GIRQ23_SRC05_PRI JTVIC_PRI1
\r
591 #define GIRQ23_SRC06_PRI JTVIC_PRI1
\r
592 #define GIRQ23_SRC07_PRI JTVIC_PRI1
\r
593 #define GIRQ23_SRC08_PRI JTVIC_PRI1
\r
594 #define GIRQ23_SRC09_PRI JTVIC_PRI1
\r
595 #define GIRQ23_SRC10_PRI JTVIC_PRI1
\r
596 #define GIRQ23_SRC11_PRI JTVIC_PRI1
\r
597 #define GIRQ23_SRC12_PRI JTVIC_PRI1
\r
598 #define GIRQ23_SRC13_PRI JTVIC_PRI1
\r
599 #define GIRQ23_SRC14_PRI JTVIC_PRI1
\r
600 #define GIRQ23_SRC15_PRI JTVIC_PRI1
\r
603 #define GIRQ23_PRI_A (JTVIC_PRI_VAL(0, GIRQ23_SRC00_PRI) + \
\r
604 JTVIC_PRI_VAL(1, GIRQ23_SRC01_PRI) + \
\r
605 JTVIC_PRI_VAL(2, GIRQ23_SRC02_PRI) + \
\r
606 JTVIC_PRI_VAL(3, GIRQ23_SRC03_PRI) + \
\r
607 JTVIC_PRI_VAL(4, GIRQ23_SRC04_PRI) + \
\r
608 JTVIC_PRI_VAL(5, GIRQ23_SRC05_PRI) + \
\r
609 JTVIC_PRI_VAL(6, GIRQ23_SRC06_PRI) + \
\r
610 JTVIC_PRI_VAL(7, GIRQ23_SRC07_PRI))
\r
612 #define GIRQ23_PRI_B (JTVIC_PRI_VAL(0, GIRQ23_SRC08_PRI) + \
\r
613 JTVIC_PRI_VAL(1, GIRQ23_SRC09_PRI) + \
\r
614 JTVIC_PRI_VAL(2, GIRQ23_SRC10_PRI) + \
\r
615 JTVIC_PRI_VAL(3, GIRQ23_SRC11_PRI) + \
\r
616 JTVIC_PRI_VAL(4, GIRQ23_SRC12_PRI) + \
\r
617 JTVIC_PRI_VAL(5, GIRQ23_SRC13_PRI) + \
\r
618 JTVIC_PRI_VAL(6, GIRQ23_SRC14_PRI) + \
\r
619 JTVIC_PRI_VAL(7, GIRQ23_SRC15_PRI))
\r
621 #define GIRQ23_PRI_C (0ul)
\r
622 #define GIRQ23_PRI_D (0ul)
\r
628 #define GIRQ24_SRC00_PRI JTVIC_PRI3
\r
629 #define GIRQ24_SRC01_PRI JTVIC_PRI1
\r
630 #define GIRQ24_SRC02_PRI JTVIC_PRI1
\r
633 #define GIRQ24_PRI_A (JTVIC_PRI_VAL(0, GIRQ24_SRC00_PRI) + \
\r
634 JTVIC_PRI_VAL(1, GIRQ24_SRC01_PRI) + \
\r
635 JTVIC_PRI_VAL(2, GIRQ24_SRC02_PRI) )
\r
637 #define GIRQ24_PRI_B (0ul)
\r
638 #define GIRQ24_PRI_C (0ul)
\r
639 #define GIRQ24_PRI_D (0ul)
\r
645 #define GIRQ25_SRC00_PRI JTVIC_PRI1
\r
646 #define GIRQ25_SRC01_PRI JTVIC_PRI1
\r
647 #define GIRQ25_SRC02_PRI JTVIC_PRI1
\r
648 #define GIRQ25_SRC03_PRI JTVIC_PRI1
\r
649 #define GIRQ25_SRC04_PRI JTVIC_PRI1
\r
650 #define GIRQ25_SRC05_PRI JTVIC_PRI1
\r
651 #define GIRQ25_SRC06_PRI JTVIC_PRI1
\r
652 #define GIRQ25_SRC07_PRI JTVIC_PRI1
\r
653 #define GIRQ25_SRC08_PRI JTVIC_PRI1
\r
654 #define GIRQ25_SRC09_PRI JTVIC_PRI1
\r
655 #define GIRQ25_SRC10_PRI JTVIC_PRI1
\r
656 #define GIRQ25_SRC11_PRI JTVIC_PRI1
\r
657 #define GIRQ25_SRC12_PRI JTVIC_PRI1
\r
658 #define GIRQ25_SRC13_PRI JTVIC_PRI1
\r
659 #define GIRQ25_SRC14_PRI JTVIC_PRI1
\r
660 #define GIRQ25_SRC15_PRI JTVIC_PRI1
\r
661 #define GIRQ25_SRC16_PRI JTVIC_PRI1
\r
662 #define GIRQ25_SRC17_PRI JTVIC_PRI1
\r
663 #define GIRQ25_SRC18_PRI JTVIC_PRI1
\r
664 #define GIRQ25_SRC19_PRI JTVIC_PRI1
\r
665 #define GIRQ25_SRC20_PRI JTVIC_PRI1
\r
666 #define GIRQ25_SRC21_PRI JTVIC_PRI1
\r
667 #define GIRQ25_SRC22_PRI JTVIC_PRI1
\r
668 #define GIRQ25_SRC23_PRI JTVIC_PRI1
\r
669 #define GIRQ25_SRC24_PRI JTVIC_PRI1
\r
670 #define GIRQ25_SRC25_PRI JTVIC_PRI1
\r
671 #define GIRQ25_SRC26_PRI JTVIC_PRI1
\r
672 #define GIRQ25_SRC27_PRI JTVIC_PRI1
\r
675 #define GIRQ25_PRI_A (JTVIC_PRI_VAL(0, GIRQ25_SRC00_PRI) + \
\r
676 JTVIC_PRI_VAL(1, GIRQ25_SRC01_PRI) + \
\r
677 JTVIC_PRI_VAL(2, GIRQ25_SRC02_PRI) + \
\r
678 JTVIC_PRI_VAL(3, GIRQ25_SRC03_PRI) + \
\r
679 JTVIC_PRI_VAL(4, GIRQ25_SRC04_PRI) + \
\r
680 JTVIC_PRI_VAL(5, GIRQ25_SRC05_PRI) + \
\r
681 JTVIC_PRI_VAL(6, GIRQ25_SRC06_PRI) + \
\r
682 JTVIC_PRI_VAL(7, GIRQ25_SRC07_PRI))
\r
684 #define GIRQ25_PRI_B (JTVIC_PRI_VAL(0, GIRQ25_SRC08_PRI) + \
\r
685 JTVIC_PRI_VAL(1, GIRQ25_SRC09_PRI) + \
\r
686 JTVIC_PRI_VAL(2, GIRQ25_SRC10_PRI) + \
\r
687 JTVIC_PRI_VAL(3, GIRQ25_SRC11_PRI) + \
\r
688 JTVIC_PRI_VAL(4, GIRQ25_SRC12_PRI) + \
\r
689 JTVIC_PRI_VAL(5, GIRQ25_SRC13_PRI) + \
\r
690 JTVIC_PRI_VAL(6, GIRQ25_SRC14_PRI) + \
\r
691 JTVIC_PRI_VAL(7, GIRQ25_SRC15_PRI))
\r
693 #define GIRQ25_PRI_C (JTVIC_PRI_VAL(0, GIRQ25_SRC16_PRI) + \
\r
694 JTVIC_PRI_VAL(1, GIRQ25_SRC17_PRI) + \
\r
695 JTVIC_PRI_VAL(2, GIRQ25_SRC18_PRI) + \
\r
696 JTVIC_PRI_VAL(3, GIRQ25_SRC19_PRI) + \
\r
697 JTVIC_PRI_VAL(4, GIRQ25_SRC20_PRI) + \
\r
698 JTVIC_PRI_VAL(5, GIRQ25_SRC21_PRI) + \
\r
699 JTVIC_PRI_VAL(6, GIRQ25_SRC22_PRI) + \
\r
700 JTVIC_PRI_VAL(7, GIRQ25_SRC23_PRI))
\r
702 #define GIRQ25_PRI_D (JTVIC_PRI_VAL(0, GIRQ25_SRC24_PRI) + \
\r
703 JTVIC_PRI_VAL(1, GIRQ25_SRC25_PRI) + \
\r
704 JTVIC_PRI_VAL(2, GIRQ25_SRC26_PRI) + \
\r
705 JTVIC_PRI_VAL(3, GIRQ25_SRC27_PRI) )
\r
711 #define GIRQ26_SRC00_PRI JTVIC_PRI1
\r
712 #define GIRQ26_SRC01_PRI JTVIC_PRI1
\r
713 #define GIRQ26_SRC02_PRI JTVIC_PRI1
\r
714 #define GIRQ26_SRC03_PRI JTVIC_PRI1
\r
715 #define GIRQ26_SRC04_PRI JTVIC_PRI1
\r
716 #define GIRQ26_SRC05_PRI JTVIC_PRI1
\r
717 #define GIRQ26_SRC06_PRI JTVIC_PRI1
\r
718 #define GIRQ26_SRC07_PRI JTVIC_PRI1
\r
719 #define GIRQ26_SRC08_PRI JTVIC_PRI1
\r
720 #define GIRQ26_SRC09_PRI JTVIC_PRI1
\r
721 #define GIRQ26_SRC10_PRI JTVIC_PRI1
\r
722 #define GIRQ26_SRC11_PRI JTVIC_PRI1
\r
725 #define GIRQ26_PRI_A (JTVIC_PRI_VAL(0, GIRQ26_SRC00_PRI) + \
\r
726 JTVIC_PRI_VAL(1, GIRQ26_SRC01_PRI) + \
\r
727 JTVIC_PRI_VAL(2, GIRQ26_SRC02_PRI) + \
\r
728 JTVIC_PRI_VAL(3, GIRQ26_SRC03_PRI) + \
\r
729 JTVIC_PRI_VAL(4, GIRQ26_SRC04_PRI) + \
\r
730 JTVIC_PRI_VAL(5, GIRQ26_SRC05_PRI) + \
\r
731 JTVIC_PRI_VAL(6, GIRQ26_SRC06_PRI) + \
\r
732 JTVIC_PRI_VAL(7, GIRQ26_SRC07_PRI))
\r
734 #define GIRQ26_PRI_B (JTVIC_PRI_VAL(0, GIRQ26_SRC08_PRI) + \
\r
735 JTVIC_PRI_VAL(1, GIRQ26_SRC09_PRI) + \
\r
736 JTVIC_PRI_VAL(2, GIRQ26_SRC10_PRI) + \
\r
737 JTVIC_PRI_VAL(3, GIRQ26_SRC11_PRI) )
\r
739 #define GIRQ26_PRI_C (0ul)
\r
740 #define GIRQ26_PRI_D (0ul)
\r
744 * b[7:0] = GIRQ number (0-18) -> GIRQ(8,26)
\r
745 * b[15:8] = bit number (0-31)
\r
749 GPIO140_IRQn = ((0 << 8) + 0),
\r
750 GPIO141_IRQn = ((1 << 8) + 0),
\r
751 GPIO142_IRQn = ((2 << 8) + 0),
\r
752 GPIO143_IRQn = ((3 << 8) + 0),
\r
753 GPIO144_IRQn = ((4 << 8) + 0),
\r
754 GPIO145_IRQn = ((5 << 8) + 0),
\r
755 GPIO146_IRQn = ((6 << 8) + 0),
\r
756 GPIO147_IRQn = ((7 << 8) + 0),
\r
757 GPIO150_IRQn = ((8 << 8) + 0),
\r
758 GPIO151_IRQn = ((9 << 8) + 0),
\r
759 GPIO152_IRQn = ((10 << 8) + 0),
\r
760 GPIO153_IRQn = ((11 << 8) + 0),
\r
761 GPIO154_IRQn = ((12 << 8) + 0),
\r
762 GPIO155_IRQn = ((13 << 8) + 0),
\r
763 GPIO156_IRQn = ((14 << 8) + 0),
\r
764 GPIO157_IRQn = ((15 << 8) + 0),
\r
765 GPIO160_IRQn = ((16 << 8) + 0),
\r
766 GPIO161_IRQn = ((17 << 8) + 0),
\r
767 GPIO162_IRQn = ((18 << 8) + 0),
\r
768 GPIO163_IRQn = ((19 << 8) + 0),
\r
769 GPIO164_IRQn = ((20 << 8) + 0),
\r
770 GPIO165_IRQn = ((21 << 8) + 0),
\r
771 GPIO166_IRQn = ((22 << 8) + 0),
\r
773 GPIO100_IRQn = ((0 << 8) + 1),
\r
774 GPIO101_IRQn = ((1 << 8) + 1),
\r
775 GPIO102_IRQn = ((2 << 8) + 1),
\r
776 GPIO103_IRQn = ((3 << 8) + 1),
\r
777 GPIO104_IRQn = ((4 << 8) + 1),
\r
778 GPIO105_IRQn = ((5 << 8) + 1),
\r
779 GPIO106_IRQn = ((6 << 8) + 1),
\r
780 GPIO107_IRQn = ((7 << 8) + 1),
\r
781 GPIO110_IRQn = ((8 << 8) + 1),
\r
782 GPIO111_IRQn = ((9 << 8) + 1),
\r
783 GPIO112_IRQn = ((10 << 8) + 1),
\r
784 GPIO113_IRQn = ((11 << 8) + 1),
\r
785 GPIO114_IRQn = ((12 << 8) + 1),
\r
786 GPIO115_IRQn = ((13 << 8) + 1),
\r
787 GPIO116_IRQn = ((14 << 8) + 1),
\r
788 GPIO117_IRQn = ((15 << 8) + 1),
\r
789 GPIO120_IRQn = ((16 << 8) + 1),
\r
790 GPIO121_IRQn = ((17 << 8) + 1),
\r
791 GPIO122_IRQn = ((18 << 8) + 1),
\r
792 GPIO123_IRQn = ((19 << 8) + 1),
\r
793 GPIO124_IRQn = ((20 << 8) + 1),
\r
794 GPIO125_IRQn = ((21 << 8) + 1),
\r
795 GPIO126_IRQn = ((22 << 8) + 1),
\r
796 GPIO127_IRQn = ((23 << 8) + 1),
\r
797 GPIO130_IRQn = ((24 << 8) + 1),
\r
798 GPIO131_IRQn = ((25 << 8) + 1),
\r
799 GPIO132_IRQn = ((26 << 8) + 1),
\r
800 GPIO133_IRQn = ((27 << 8) + 1),
\r
801 GPIO134_IRQn = ((28 << 8) + 1),
\r
802 GPIO135_IRQn = ((29 << 8) + 1),
\r
803 GPIO136_IRQn = ((30 << 8) + 1),
\r
805 GPIO040_IRQn = ((0 << 8) + 2),
\r
806 GPIO041_IRQn = ((1 << 8) + 2),
\r
807 GPIO042_IRQn = ((2 << 8) + 2),
\r
808 GPIO043_IRQn = ((3 << 8) + 2),
\r
809 GPIO044_IRQn = ((4 << 8) + 2),
\r
810 GPIO045_IRQn = ((5 << 8) + 2),
\r
811 GPIO046_IRQn = ((6 << 8) + 2),
\r
812 GPIO047_IRQn = ((7 << 8) + 2),
\r
813 GPIO050_IRQn = ((8 << 8) + 2),
\r
814 GPIO051_IRQn = ((9 << 8) + 2),
\r
815 GPIO052_IRQn = ((10 << 8) + 2),
\r
816 GPIO053_IRQn = ((11 << 8) + 2),
\r
817 GPIO054_IRQn = ((12 << 8) + 2),
\r
818 GPIO055_IRQn = ((13 << 8) + 2),
\r
819 GPIO056_IRQn = ((14 << 8) + 2),
\r
820 GPIO057_IRQn = ((15 << 8) + 2),
\r
821 GPIO060_IRQn = ((16 << 8) + 2),
\r
822 GPIO061_IRQn = ((17 << 8) + 2),
\r
823 GPIO062_IRQn = ((18 << 8) + 2),
\r
824 GPIO063_IRQn = ((19 << 8) + 2),
\r
825 GPIO064_IRQn = ((20 << 8) + 2),
\r
826 GPIO065_IRQn = ((21 << 8) + 2),
\r
827 GPIO066_IRQn = ((22 << 8) + 2),
\r
828 GPIO067_IRQn = ((23 << 8) + 2),
\r
830 GPIO001_IRQn = ((1 << 8) + 3),
\r
831 GPIO002_IRQn = ((2 << 8) + 3),
\r
832 GPIO003_IRQn = ((3 << 8) + 3),
\r
833 GPIO004_IRQn = ((4 << 8) + 3),
\r
834 GPIO005_IRQn = ((5 << 8) + 3),
\r
835 GPIO006_IRQn = ((6 << 8) + 3),
\r
836 GPIO007_IRQn = ((7 << 8) + 3),
\r
837 GPIO010_IRQn = ((8 << 8) + 3),
\r
838 GPIO011_IRQn = ((9 << 8) + 3),
\r
839 GPIO012_IRQn = ((10 << 8) + 3),
\r
840 GPIO013_IRQn = ((11 << 8) + 3),
\r
841 GPIO014_IRQn = ((12 << 8) + 3),
\r
842 GPIO015_IRQn = ((13 << 8) + 3),
\r
843 GPIO016_IRQn = ((14 << 8) + 3),
\r
844 GPIO017_IRQn = ((15 << 8) + 3),
\r
845 GPIO020_IRQn = ((16 << 8) + 3),
\r
846 GPIO021_IRQn = ((17 << 8) + 3),
\r
847 GPIO022_IRQn = ((18 << 8) + 3),
\r
848 GPIO023_IRQn = ((19 << 8) + 3),
\r
849 GPIO024_IRQn = ((20 << 8) + 3),
\r
850 GPIO025_IRQn = ((21 << 8) + 3),
\r
851 GPIO026_IRQn = ((22 << 8) + 3),
\r
852 GPIO027_IRQn = ((23 << 8) + 3),
\r
853 GPIO030_IRQn = ((24 << 8) + 3),
\r
854 GPIO031_IRQn = ((25 << 8) + 3),
\r
855 GPIO032_IRQn = ((26 << 8) + 3),
\r
856 GPIO033_IRQn = ((27 << 8) + 3),
\r
857 GPIO034_IRQn = ((28 << 8) + 3),
\r
858 GPIO035_IRQn = ((29 << 8) + 3),
\r
859 GPIO036_IRQn = ((30 << 8) + 3),
\r
861 SMB0_IRQn = ((0 << 8) + 4),
\r
862 SMB1_IRQn = ((1 << 8) + 4),
\r
863 SMB2_IRQn = ((2 << 8) + 4),
\r
865 DMA0_IRQn = ((0 << 8) + 5),
\r
866 DMA1_IRQn = ((1 << 8) + 5),
\r
867 DMA2_IRQn = ((2 << 8) + 5),
\r
868 DMA3_IRQn = ((3 << 8) + 5),
\r
869 DMA4_IRQn = ((4 << 8) + 5),
\r
870 DMA5_IRQn = ((5 << 8) + 5),
\r
871 DMA6_IRQn = ((6 << 8) + 5),
\r
873 LPC_ERR_IRQn = ((0 << 8) + 6),
\r
874 PFR_STS_IRQn = ((1 << 8) + 6),
\r
875 LED0_IRQn = ((2 << 8) + 6),
\r
876 LED1_IRQn = ((3 << 8) + 6),
\r
877 LED2_IRQn = ((4 << 8) + 6),
\r
878 INT32K_RDY_IRQn = ((5 << 8) + 6),
\r
880 MBOX_IRQn = ((0 << 8) + 7),
\r
881 EMI0_IRQn = ((2 << 8) + 7),
\r
882 KBD_OBF_IRQn = ((4 << 8) + 7),
\r
883 KBD_IBF_IRQn = ((5 << 8) + 7),
\r
884 P80A_IRQn = ((6 << 8) + 7),
\r
885 P80B_IRQn = ((7 << 8) + 7),
\r
886 ACPI_PM1_CTL_IRQn = ((8 << 8) + 7),
\r
887 ACPI_PM1_EN_IRQn = ((9 << 8) + 7),
\r
888 ACPI_PM1_STS_IRQn = ((10 << 8) + 7),
\r
889 ACPI_EC0_IBF_IRQn = ((11 << 8) + 7),
\r
890 ACPI_EC0_OBF_IRQn = ((12 << 8) + 7),
\r
891 ACPI_EC1_IBF_IRQn = ((13 << 8) + 7),
\r
892 ACPI_EC1_OBF_IRQn = ((14 << 8) + 7),
\r
893 ACPI_EC2_IBF_IRQn = ((15 << 8) + 7),
\r
894 ACPI_EC2_OBF_IRQn = ((16 << 8) + 7),
\r
895 ACPI_EC3_IBF_IRQn = ((17 << 8) + 7),
\r
896 ACPI_EC3_OBF_IRQn = ((18 << 8) + 7),
\r
898 LPC_WAKE_IRQn = ((0 << 8) + 8),
\r
899 SMB0_WAKE_IRQn = ((1 << 8) + 8),
\r
900 SMB1_WAKE_IRQn = ((2 << 8) + 8),
\r
901 SMB2_WAKE_IRQn = ((3 << 8) + 8),
\r
902 PS2D0_WAKE_IRQn = ((4 << 8) + 8),
\r
903 PS2D1A_WAKE_IRQn = ((5 << 8) + 8),
\r
904 PS2D1B_WAKE_IRQn = ((6 << 8) + 8),
\r
905 KSC_WAKE_IRQn = ((7 << 8) + 8),
\r
906 ICSP_WAKE_IRQn = ((8 << 8) + 8),
\r
907 ESPI_WAKE_IRQn = ((9 << 8) + 8),
\r
909 ADC_SGL_IRQn = ((0 << 8) + 9),
\r
910 ADC_RPT_IRQn = ((1 << 8) + 9),
\r
911 PS2D0_ACT_IRQn = ((4 << 8) + 9),
\r
912 PS2D1_ACT_IRQn = ((5 << 8) + 9),
\r
913 KSC_IRQn = ((6 << 8) + 9),
\r
914 UART0_IRQn = ((7 << 8) + 9),
\r
915 PECI_HOST_IRQn = ((8 << 8) + 9),
\r
916 TACH0_IRQn = ((9 << 8) + 9),
\r
917 TACH1_IRQn = ((10 << 8) + 9),
\r
919 QMSPI0_IRQn = ((0 << 8) + 10),
\r
921 ESPI_PC_IRQn = ((0 << 8) + 11),
\r
922 ESPI_BM1_IRQn = ((1 << 8) + 11),
\r
923 ESPI_BM2_IRQn = ((2 << 8) + 11),
\r
924 ESPI_LTR_IRQn = ((3 << 8) + 11),
\r
925 ESPI_OOB_UP_IRQn = ((4 << 8) + 11),
\r
926 ESPI_OOB_DN_IRQn = ((5 << 8) + 11),
\r
927 ESPI_FLASH_IRQn = ((6 << 8) + 11),
\r
928 ESPI_RESET_IRQn = ((7 << 8) + 11),
\r
929 SUBDEC_IRQn = ((8 << 8) + 11),
\r
931 BC0_BUSY_IRQn = ((0 << 8) + 12),
\r
932 BC0_ERR_IRQn = ((1 << 8) + 12),
\r
933 BC0_EV_IRQn = ((2 << 8) + 12),
\r
934 BC1_BUSY_IRQn = ((3 << 8) + 12),
\r
935 BC1_ERR_IRQn = ((4 << 8) + 12),
\r
936 BC1_EV_IRQn = ((5 << 8) + 12),
\r
938 STAP_OBF_IRQn = ((0 << 8) + 13),
\r
939 STAP_IBF_IRQn = ((1 << 8) + 13),
\r
940 STAP_WAKE_IRQn = ((2 << 8) + 13),
\r
942 LPC_WAKE_ONLY_IRQn = ((0 << 8) + 14),
\r
943 SMB0_WAKE_ONLY_IRQn = ((1 << 8) + 14),
\r
944 SMB1_WAKE_ONLY_IRQn = ((2 << 8) + 14),
\r
945 SMB2_WAKE_ONLY_IRQn = ((3 << 8) + 14),
\r
946 PS2D0_WAKE_ONLY_IRQn = ((4 << 8) + 14),
\r
947 PS2D1A_WAKE_ONLY_IRQn = ((5 << 8) + 14),
\r
948 PS2D1B_WAKE_ONLY_IRQn = ((6 << 8) + 14),
\r
949 KSC_WAKE_ONLY_IRQn = ((7 << 8) + 14),
\r
950 ICSP_WAKE_ONLY_IRQn = ((8 << 8) + 14),
\r
951 ESPI_WAKE_ONLY_IRQn = ((9 << 8) + 14),
\r
953 TMR0_IRQn = ((0 << 8) + 15),
\r
954 TMR1_IRQn = ((1 << 8) + 15),
\r
955 TMR2_IRQn = ((2 << 8) + 15),
\r
956 TMR3_IRQn = ((3 << 8) + 15),
\r
957 RTOS_TMR_IRQn = ((4 << 8) + 15),
\r
958 HIBTMR_IRQn = ((5 << 8) + 15),
\r
959 WEEK_ALARM_IRQn = ((6 << 8) + 15),
\r
960 SUB_WEEK_ALARM_IRQn = ((7 << 8) + 15),
\r
961 ONE_SEC_WEEK_IRQn = ((8 << 8) + 15),
\r
962 SUB_SEC_WEEK_IRQn = ((9 << 8) + 15),
\r
963 SYSPWR_PRES_IRQn = ((10 << 8) + 15),
\r
964 VCI_OVRD_IN_IRQn = ((11 << 8) + 15),
\r
965 VCI_IN0_IRQn = ((12 << 8) + 15),
\r
966 VCI_IN1_IRQn = ((13 << 8) + 15),
\r
968 M14K_COUNTER_IRQn = ((0 << 8) + 16),
\r
969 M14K_SOFT_IRQ0_IRQn = ((1 << 8) + 16),
\r
970 M14K_SOFT_IRQ1_IRQn = ((2 << 8) + 16),
\r
972 ESPI_MSVW00_S0_IRQn = ((0 << 8) + 17),
\r
973 ESPI_MSVW00_S1_IRQn = ((1 << 8) + 17),
\r
974 ESPI_MSVW00_S2_IRQn = ((2 << 8) + 17),
\r
975 ESPI_MSVW00_S3_IRQn = ((3 << 8) + 17),
\r
976 ESPI_MSVW01_S0_IRQn = ((4 << 8) + 17),
\r
977 ESPI_MSVW01_S1_IRQn = ((5 << 8) + 17),
\r
978 ESPI_MSVW01_S2_IRQn = ((6 << 8) + 17),
\r
979 ESPI_MSVW01_S3_IRQn = ((7 << 8) + 17),
\r
980 ESPI_MSVW02_S0_IRQn = ((8 << 8) + 17),
\r
981 ESPI_MSVW02_S1_IRQn = ((9 << 8) + 17),
\r
982 ESPI_MSVW02_S2_IRQn = ((10 << 8) + 17),
\r
983 ESPI_MSVW02_S3_IRQn = ((11 << 8) + 17),
\r
984 ESPI_MSVW03_S0_IRQn = ((12 << 8) + 17),
\r
985 ESPI_MSVW03_S1_IRQn = ((13 << 8) + 17),
\r
986 ESPI_MSVW03_S2_IRQn = ((14 << 8) + 17),
\r
987 ESPI_MSVW03_S3_IRQn = ((15 << 8) + 17),
\r
988 ESPI_MSVW04_S0_IRQn = ((16 << 8) + 17),
\r
989 ESPI_MSVW04_S1_IRQn = ((17 << 8) + 17),
\r
990 ESPI_MSVW04_S2_IRQn = ((18 << 8) + 17),
\r
991 ESPI_MSVW04_S3_IRQn = ((19 << 8) + 17),
\r
992 ESPI_MSVW05_S0_IRQn = ((20 << 8) + 17),
\r
993 ESPI_MSVW05_S1_IRQn = ((21 << 8) + 17),
\r
994 ESPI_MSVW05_S2_IRQn = ((22 << 8) + 17),
\r
995 ESPI_MSVW05_S3_IRQn = ((23 << 8) + 17),
\r
996 ESPI_MSVW06_S0_IRQn = ((24 << 8) + 17),
\r
997 ESPI_MSVW06_S1_IRQn = ((25 << 8) + 17),
\r
998 ESPI_MSVW06_S2_IRQn = ((26 << 8) + 17),
\r
999 ESPI_MSVW06_S3_IRQn = ((27 << 8) + 17),
\r
1001 ESPI_MSVW07_S0_IRQn = ((0 << 8) + 18),
\r
1002 ESPI_MSVW07_S1_IRQn = ((1 << 8) + 18),
\r
1003 ESPI_MSVW07_S2_IRQn = ((2 << 8) + 18),
\r
1004 ESPI_MSVW07_S3_IRQn = ((3 << 8) + 18),
\r
1005 ESPI_MSVW08_S0_IRQn = ((4 << 8) + 18),
\r
1006 ESPI_MSVW08_S1_IRQn = ((5 << 8) + 18),
\r
1007 ESPI_MSVW08_S2_IRQn = ((6 << 8) + 18),
\r
1008 ESPI_MSVW08_S3_IRQn = ((7 << 8) + 18),
\r
1009 ESPI_MSVW09_S0_IRQn = ((8 << 8) + 18),
\r
1010 ESPI_MSVW09_S1_IRQn = ((9 << 8) + 18),
\r
1011 ESPI_MSVW09_S2_IRQn = ((10 << 8) + 18),
\r
1012 ESPI_MSVW09_S3_IRQn = ((11 << 8) + 18),
\r
1017 * GIRQn ISR prototypes used to export handlers.
\r
1018 * NOTE: We need nomips16 on both prototype and
\r
1019 * function definition. Do not add the other
\r
1020 * attributes from the function definition to
\r
1021 * these prototypes.
\r
1023 void __attribute__((nomips16)) girq08_isr(void);
\r
1024 void __attribute__((nomips16)) girq09_isr(void);
\r
1025 void __attribute__((nomips16)) girq10_isr(void);
\r
1026 void __attribute__((nomips16)) girq11_isr(void);
\r
1027 void __attribute__((nomips16)) girq12_isr(void);
\r
1028 void __attribute__((nomips16)) girq13_isr(void);
\r
1029 void __attribute__((nomips16)) girq14_isr(void);
\r
1030 void __attribute__((nomips16)) girq15_isr(void);
\r
1031 void __attribute__((nomips16)) girq16_isr(void);
\r
1032 void __attribute__((nomips16)) girq17_isr(void);
\r
1033 void __attribute__((nomips16)) girq18_isr(void);
\r
1034 void __attribute__((nomips16)) girq19_isr(void);
\r
1035 void __attribute__((nomips16)) girq20_isr(void);
\r
1036 void __attribute__((nomips16)) girq21_isr(void);
\r
1037 void __attribute__((nomips16)) girq22_isr(void);
\r
1038 void __attribute__((nomips16)) girq23_isr(void);
\r
1039 void __attribute__((nomips16)) girq24_isr(void);
\r
1040 void __attribute__((nomips16)) girq25_isr(void);
\r
1041 void __attribute__((nomips16)) girq26_isr(void);
\r
1044 extern const JTVIC_CFG dflt_ih_table[];
\r
1046 #ifdef __cplusplus
\r
1050 #endif /* _MEC14XX_GIRQS_H */
\r
projects / freertos / blob