1 /*****************************************************************************
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2 * Copyright 2014 Microchip Technology Inc. and its subsidiaries.
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3 * You may use this software and any derivatives exclusively with
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4 * Microchip products.
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5 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".
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6 * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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7 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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8 * AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP
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9 * PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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10 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.
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14 * TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL
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15 * CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF
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16 * FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE
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19 *****************************************************************************/
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22 /** @file mec14xx_tfdp.h
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23 *MEC14xx TRACE FIFO Data Port definitions
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25 /** @defgroup MEC14xx Peripherals TFDP
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28 #ifndef _MEC14XX_TFDP_H
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29 #define _MEC14XX_TFDP_H
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37 #define TFDP_NUM_INSTANCES (1u)
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39 #define TFDP_FRAME_START (0xFD)
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43 // Offset +00h TFDP Data Register: 8-bit R/W
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45 #define TFDP_DATA_REG_OFS (0ul)
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46 #define TFDP_DATA_REG_MASK (0xFFul)
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49 // Offset +04h TFDP Control Register 8-bit R/W
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51 #define TFDP_CTRL_REG_OFS (0x04ul)
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52 #define TFDP_CTRL_REG_MASK (0x7Ful)
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54 #define TFDP_CTRL_ENABLE_BITPOS (0u)
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55 #define TFDP_CTRL_EDGE_SEL_BITPOS (1u)
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56 #define TFDP_CTRL_DIVSEL_BITPOS (2ul)
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57 #define TFDP_CTRL_IP_DELAY_BITPOS (4ul)
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59 #define TFDP_CTRL_ENABLE (1u << (TFDP_CTRL_ENABLE_BITPOS))
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60 // Select clock edge data on which data is shifted out
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61 #define TFDP_CTRL_RISING_EDGE (0u << (TFDP_CTRL_EDGE_SEL_BITPOS))
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62 #define TFDP_CTRL_FALLING_EDGE (1u << (TFDP_CTRL_EDGE_SEL_BITPOS))
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63 // TFDP Clock divisor
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64 #define TFDP_CTRL_CLK_DIV2 (0u << (TFDP_CTRL_DIVSEL_BITPOS))
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65 #define TFDP_CTRL_CLK_DIV4 (1u << (TFDP_CTRL_DIVSEL_BITPOS))
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66 #define TFDP_CTRL_CLK_DIV8 (2u << (TFDP_CTRL_DIVSEL_BITPOS))
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67 #define TFDP_CTRL_CLK_DIV2_RSVD (3u << (TFDP_CTRL_DIVSEL_BITPOS))
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68 // Number of clocks to delay between each byte
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69 // Note: this will affect time TFDP block holds off CPU on next
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70 // write to TFDP data register.
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71 #define TFDP_CTRL_IP_1CLKS (0u << (TFDP_CTRL_IP_DELAY_BITPOS))
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72 #define TFDP_CTRL_IP_2CLKS (1u << (TFDP_CTRL_IP_DELAY_BITPOS))
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73 #define TFDP_CTRL_IP_3CLKS (2u << (TFDP_CTRL_IP_DELAY_BITPOS))
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74 #define TFDP_CTRL_IP_4CLKS (3u << (TFDP_CTRL_IP_DELAY_BITPOS))
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75 #define TFDP_CTRL_IP_5CLKS (4u << (TFDP_CTRL_IP_DELAY_BITPOS))
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76 #define TFDP_CTRL_IP_6CLKS (5u << (TFDP_CTRL_IP_DELAY_BITPOS))
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77 #define TFDP_CTRL_IP_7CLKS (6u << (TFDP_CTRL_IP_DELAY_BITPOS))
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78 #define TFDP_CTRL_IP_8CLKS (7u << (TFDP_CTRL_IP_DELAY_BITPOS))
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85 #endif // #ifndef _MEC14XX_TFDP_H
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86 /* end mec14xx_tfdp.h */
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