1 // See LICENSE for license details.
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3 #ifndef RISCV_CSR_ENCODING_H
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4 #define RISCV_CSR_ENCODING_H
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6 #define MSTATUS_UIE 0x00000001
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7 #define MSTATUS_SIE 0x00000002
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8 #define MSTATUS_HIE 0x00000004
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9 #define MSTATUS_MIE 0x00000008
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10 #define MSTATUS_UPIE 0x00000010
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11 #define MSTATUS_SPIE 0x00000020
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12 #define MSTATUS_HPIE 0x00000040
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13 #define MSTATUS_MPIE 0x00000080
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14 #define MSTATUS_SPP 0x00000100
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15 #define MSTATUS_HPP 0x00000600
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16 #define MSTATUS_MPP 0x00001800
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17 #define MSTATUS_FS 0x00006000
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18 #define MSTATUS_XS 0x00018000
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19 #define MSTATUS_MPRV 0x00020000
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20 #define MSTATUS_PUM 0x00040000
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21 #define MSTATUS_MXR 0x00080000
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22 #define MSTATUS_VM 0x1F000000
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23 #define MSTATUS32_SD 0x80000000
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24 #define MSTATUS64_SD 0x8000000000000000
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26 #define SSTATUS_UIE 0x00000001
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27 #define SSTATUS_SIE 0x00000002
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28 #define SSTATUS_UPIE 0x00000010
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29 #define SSTATUS_SPIE 0x00000020
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30 #define SSTATUS_SPP 0x00000100
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31 #define SSTATUS_FS 0x00006000
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32 #define SSTATUS_XS 0x00018000
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33 #define SSTATUS_PUM 0x00040000
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34 #define SSTATUS32_SD 0x80000000
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35 #define SSTATUS64_SD 0x8000000000000000
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37 #define DCSR_XDEBUGVER (3U<<30)
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38 #define DCSR_NDRESET (1<<29)
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39 #define DCSR_FULLRESET (1<<28)
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40 #define DCSR_EBREAKM (1<<15)
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41 #define DCSR_EBREAKH (1<<14)
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42 #define DCSR_EBREAKS (1<<13)
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43 #define DCSR_EBREAKU (1<<12)
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44 #define DCSR_STOPCYCLE (1<<10)
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45 #define DCSR_STOPTIME (1<<9)
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46 #define DCSR_CAUSE (7<<6)
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47 #define DCSR_DEBUGINT (1<<5)
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48 #define DCSR_HALT (1<<3)
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49 #define DCSR_STEP (1<<2)
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50 #define DCSR_PRV (3<<0)
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52 #define DCSR_CAUSE_NONE 0
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53 #define DCSR_CAUSE_SWBP 1
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54 #define DCSR_CAUSE_HWBP 2
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55 #define DCSR_CAUSE_DEBUGINT 3
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56 #define DCSR_CAUSE_STEP 4
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57 #define DCSR_CAUSE_HALT 5
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59 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
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60 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
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61 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
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63 #define MCONTROL_SELECT (1<<19)
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64 #define MCONTROL_TIMING (1<<18)
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65 #define MCONTROL_ACTION (0x3f<<12)
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66 #define MCONTROL_CHAIN (1<<11)
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67 #define MCONTROL_MATCH (0xf<<7)
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68 #define MCONTROL_M (1<<6)
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69 #define MCONTROL_H (1<<5)
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70 #define MCONTROL_S (1<<4)
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71 #define MCONTROL_U (1<<3)
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72 #define MCONTROL_EXECUTE (1<<2)
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73 #define MCONTROL_STORE (1<<1)
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74 #define MCONTROL_LOAD (1<<0)
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76 #define MCONTROL_TYPE_NONE 0
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77 #define MCONTROL_TYPE_MATCH 2
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79 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0
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80 #define MCONTROL_ACTION_DEBUG_MODE 1
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81 #define MCONTROL_ACTION_TRACE_START 2
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82 #define MCONTROL_ACTION_TRACE_STOP 3
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83 #define MCONTROL_ACTION_TRACE_EMIT 4
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85 #define MCONTROL_MATCH_EQUAL 0
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86 #define MCONTROL_MATCH_NAPOT 1
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87 #define MCONTROL_MATCH_GE 2
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88 #define MCONTROL_MATCH_LT 3
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89 #define MCONTROL_MATCH_MASK_LOW 4
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90 #define MCONTROL_MATCH_MASK_HIGH 5
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92 #define MIP_SSIP (1 << IRQ_S_SOFT)
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93 #define MIP_HSIP (1 << IRQ_H_SOFT)
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94 #define MIP_MSIP (1 << IRQ_M_SOFT)
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95 #define MIP_STIP (1 << IRQ_S_TIMER)
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96 #define MIP_HTIP (1 << IRQ_H_TIMER)
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97 #define MIP_MTIP (1 << IRQ_M_TIMER)
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98 #define MIP_SEIP (1 << IRQ_S_EXT)
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99 #define MIP_HEIP (1 << IRQ_H_EXT)
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100 #define MIP_MEIP (1 << IRQ_M_EXT)
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102 #define SIP_SSIP MIP_SSIP
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103 #define SIP_STIP MIP_STIP
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117 #define IRQ_S_SOFT 1
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118 #define IRQ_H_SOFT 2
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119 #define IRQ_M_SOFT 3
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120 #define IRQ_S_TIMER 5
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121 #define IRQ_H_TIMER 6
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122 #define IRQ_M_TIMER 7
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123 #define IRQ_S_EXT 9
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124 #define IRQ_H_EXT 10
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125 #define IRQ_M_EXT 11
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127 #define IRQ_HOST 13
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129 #define DEFAULT_RSTVEC 0x00001000
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130 #define DEFAULT_NMIVEC 0x00001004
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131 #define DEFAULT_MTVEC 0x00001010
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132 #define CONFIG_STRING_ADDR 0x0000100C
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133 #define EXT_IO_BASE 0x40000000
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134 #define DRAM_BASE 0x80000000
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136 // page table entry (PTE) fields
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137 #define PTE_V 0x001 // Valid
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138 #define PTE_R 0x002 // Read
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139 #define PTE_W 0x004 // Write
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140 #define PTE_X 0x008 // Execute
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141 #define PTE_U 0x010 // User
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142 #define PTE_G 0x020 // Global
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143 #define PTE_A 0x040 // Accessed
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144 #define PTE_D 0x080 // Dirty
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145 #define PTE_SOFT 0x300 // Reserved for Software
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147 #define PTE_PPN_SHIFT 10
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149 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
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154 # define MSTATUS_SD MSTATUS64_SD
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155 # define SSTATUS_SD SSTATUS64_SD
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156 # define RISCV_PGLEVEL_BITS 9
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158 # define MSTATUS_SD MSTATUS32_SD
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159 # define SSTATUS_SD SSTATUS32_SD
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160 # define RISCV_PGLEVEL_BITS 10
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162 #define RISCV_PGSHIFT 12
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163 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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165 #ifndef __ASSEMBLER__
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169 #define read_csr(reg) ({ unsigned long __tmp; \
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170 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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173 #define write_csr(reg, val) ({ \
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174 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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175 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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177 asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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179 #define swap_csr(reg, val) ({ unsigned long __tmp; \
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180 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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181 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
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183 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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186 #define set_csr(reg, bit) ({ unsigned long __tmp; \
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187 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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188 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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190 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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193 #define clear_csr(reg, bit) ({ unsigned long __tmp; \
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194 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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195 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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197 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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200 #define rdtime() read_csr(time)
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201 #define rdcycle() read_csr(cycle)
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202 #define rdinstret() read_csr(instret)
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211 /* Automatically generated by parse-opcodes */
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212 #ifndef RISCV_ENCODING_H
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213 #define RISCV_ENCODING_H
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214 #define MATCH_BEQ 0x63
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215 #define MASK_BEQ 0x707f
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216 #define MATCH_BNE 0x1063
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217 #define MASK_BNE 0x707f
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218 #define MATCH_BLT 0x4063
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219 #define MASK_BLT 0x707f
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220 #define MATCH_BGE 0x5063
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221 #define MASK_BGE 0x707f
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222 #define MATCH_BLTU 0x6063
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223 #define MASK_BLTU 0x707f
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224 #define MATCH_BGEU 0x7063
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225 #define MASK_BGEU 0x707f
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226 #define MATCH_JALR 0x67
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227 #define MASK_JALR 0x707f
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228 #define MATCH_JAL 0x6f
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229 #define MASK_JAL 0x7f
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230 #define MATCH_LUI 0x37
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231 #define MASK_LUI 0x7f
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232 #define MATCH_AUIPC 0x17
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233 #define MASK_AUIPC 0x7f
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234 #define MATCH_ADDI 0x13
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235 #define MASK_ADDI 0x707f
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236 #define MATCH_SLLI 0x1013
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237 #define MASK_SLLI 0xfc00707f
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238 #define MATCH_SLTI 0x2013
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239 #define MASK_SLTI 0x707f
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240 #define MATCH_SLTIU 0x3013
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241 #define MASK_SLTIU 0x707f
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242 #define MATCH_XORI 0x4013
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243 #define MASK_XORI 0x707f
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244 #define MATCH_SRLI 0x5013
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245 #define MASK_SRLI 0xfc00707f
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246 #define MATCH_SRAI 0x40005013
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247 #define MASK_SRAI 0xfc00707f
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248 #define MATCH_ORI 0x6013
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249 #define MASK_ORI 0x707f
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250 #define MATCH_ANDI 0x7013
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251 #define MASK_ANDI 0x707f
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252 #define MATCH_ADD 0x33
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253 #define MASK_ADD 0xfe00707f
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254 #define MATCH_SUB 0x40000033
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255 #define MASK_SUB 0xfe00707f
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256 #define MATCH_SLL 0x1033
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257 #define MASK_SLL 0xfe00707f
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258 #define MATCH_SLT 0x2033
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259 #define MASK_SLT 0xfe00707f
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260 #define MATCH_SLTU 0x3033
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261 #define MASK_SLTU 0xfe00707f
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262 #define MATCH_XOR 0x4033
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263 #define MASK_XOR 0xfe00707f
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264 #define MATCH_SRL 0x5033
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265 #define MASK_SRL 0xfe00707f
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266 #define MATCH_SRA 0x40005033
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267 #define MASK_SRA 0xfe00707f
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268 #define MATCH_OR 0x6033
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269 #define MASK_OR 0xfe00707f
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270 #define MATCH_AND 0x7033
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271 #define MASK_AND 0xfe00707f
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272 #define MATCH_ADDIW 0x1b
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273 #define MASK_ADDIW 0x707f
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274 #define MATCH_SLLIW 0x101b
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275 #define MASK_SLLIW 0xfe00707f
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276 #define MATCH_SRLIW 0x501b
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277 #define MASK_SRLIW 0xfe00707f
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278 #define MATCH_SRAIW 0x4000501b
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279 #define MASK_SRAIW 0xfe00707f
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280 #define MATCH_ADDW 0x3b
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281 #define MASK_ADDW 0xfe00707f
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282 #define MATCH_SUBW 0x4000003b
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283 #define MASK_SUBW 0xfe00707f
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284 #define MATCH_SLLW 0x103b
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285 #define MASK_SLLW 0xfe00707f
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286 #define MATCH_SRLW 0x503b
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287 #define MASK_SRLW 0xfe00707f
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288 #define MATCH_SRAW 0x4000503b
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289 #define MASK_SRAW 0xfe00707f
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290 #define MATCH_LB 0x3
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291 #define MASK_LB 0x707f
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292 #define MATCH_LH 0x1003
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293 #define MASK_LH 0x707f
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294 #define MATCH_LW 0x2003
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295 #define MASK_LW 0x707f
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296 #define MATCH_LD 0x3003
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297 #define MASK_LD 0x707f
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298 #define MATCH_LBU 0x4003
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299 #define MASK_LBU 0x707f
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300 #define MATCH_LHU 0x5003
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301 #define MASK_LHU 0x707f
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302 #define MATCH_LWU 0x6003
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303 #define MASK_LWU 0x707f
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304 #define MATCH_SB 0x23
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305 #define MASK_SB 0x707f
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306 #define MATCH_SH 0x1023
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307 #define MASK_SH 0x707f
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308 #define MATCH_SW 0x2023
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309 #define MASK_SW 0x707f
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310 #define MATCH_SD 0x3023
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311 #define MASK_SD 0x707f
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312 #define MATCH_FENCE 0xf
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313 #define MASK_FENCE 0x707f
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314 #define MATCH_FENCE_I 0x100f
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315 #define MASK_FENCE_I 0x707f
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316 #define MATCH_MUL 0x2000033
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317 #define MASK_MUL 0xfe00707f
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318 #define MATCH_MULH 0x2001033
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319 #define MASK_MULH 0xfe00707f
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320 #define MATCH_MULHSU 0x2002033
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321 #define MASK_MULHSU 0xfe00707f
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322 #define MATCH_MULHU 0x2003033
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323 #define MASK_MULHU 0xfe00707f
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324 #define MATCH_DIV 0x2004033
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325 #define MASK_DIV 0xfe00707f
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326 #define MATCH_DIVU 0x2005033
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327 #define MASK_DIVU 0xfe00707f
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328 #define MATCH_REM 0x2006033
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329 #define MASK_REM 0xfe00707f
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330 #define MATCH_REMU 0x2007033
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331 #define MASK_REMU 0xfe00707f
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332 #define MATCH_MULW 0x200003b
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333 #define MASK_MULW 0xfe00707f
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334 #define MATCH_DIVW 0x200403b
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335 #define MASK_DIVW 0xfe00707f
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336 #define MATCH_DIVUW 0x200503b
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337 #define MASK_DIVUW 0xfe00707f
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338 #define MATCH_REMW 0x200603b
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339 #define MASK_REMW 0xfe00707f
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340 #define MATCH_REMUW 0x200703b
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341 #define MASK_REMUW 0xfe00707f
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342 #define MATCH_AMOADD_W 0x202f
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343 #define MASK_AMOADD_W 0xf800707f
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344 #define MATCH_AMOXOR_W 0x2000202f
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345 #define MASK_AMOXOR_W 0xf800707f
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346 #define MATCH_AMOOR_W 0x4000202f
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347 #define MASK_AMOOR_W 0xf800707f
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348 #define MATCH_AMOAND_W 0x6000202f
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349 #define MASK_AMOAND_W 0xf800707f
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350 #define MATCH_AMOMIN_W 0x8000202f
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351 #define MASK_AMOMIN_W 0xf800707f
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352 #define MATCH_AMOMAX_W 0xa000202f
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353 #define MASK_AMOMAX_W 0xf800707f
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354 #define MATCH_AMOMINU_W 0xc000202f
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355 #define MASK_AMOMINU_W 0xf800707f
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356 #define MATCH_AMOMAXU_W 0xe000202f
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357 #define MASK_AMOMAXU_W 0xf800707f
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358 #define MATCH_AMOSWAP_W 0x800202f
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359 #define MASK_AMOSWAP_W 0xf800707f
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360 #define MATCH_LR_W 0x1000202f
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361 #define MASK_LR_W 0xf9f0707f
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362 #define MATCH_SC_W 0x1800202f
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363 #define MASK_SC_W 0xf800707f
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364 #define MATCH_AMOADD_D 0x302f
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365 #define MASK_AMOADD_D 0xf800707f
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366 #define MATCH_AMOXOR_D 0x2000302f
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367 #define MASK_AMOXOR_D 0xf800707f
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368 #define MATCH_AMOOR_D 0x4000302f
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369 #define MASK_AMOOR_D 0xf800707f
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370 #define MATCH_AMOAND_D 0x6000302f
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371 #define MASK_AMOAND_D 0xf800707f
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372 #define MATCH_AMOMIN_D 0x8000302f
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373 #define MASK_AMOMIN_D 0xf800707f
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374 #define MATCH_AMOMAX_D 0xa000302f
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375 #define MASK_AMOMAX_D 0xf800707f
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376 #define MATCH_AMOMINU_D 0xc000302f
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377 #define MASK_AMOMINU_D 0xf800707f
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378 #define MATCH_AMOMAXU_D 0xe000302f
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379 #define MASK_AMOMAXU_D 0xf800707f
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380 #define MATCH_AMOSWAP_D 0x800302f
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381 #define MASK_AMOSWAP_D 0xf800707f
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382 #define MATCH_LR_D 0x1000302f
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383 #define MASK_LR_D 0xf9f0707f
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384 #define MATCH_SC_D 0x1800302f
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385 #define MASK_SC_D 0xf800707f
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386 #define MATCH_ECALL 0x73
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387 #define MASK_ECALL 0xffffffff
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388 #define MATCH_EBREAK 0x100073
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389 #define MASK_EBREAK 0xffffffff
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390 #define MATCH_URET 0x200073
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391 #define MASK_URET 0xffffffff
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392 #define MATCH_SRET 0x10200073
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393 #define MASK_SRET 0xffffffff
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394 #define MATCH_HRET 0x20200073
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395 #define MASK_HRET 0xffffffff
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396 #define MATCH_MRET 0x30200073
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397 #define MASK_MRET 0xffffffff
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398 #define MATCH_DRET 0x7b200073
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399 #define MASK_DRET 0xffffffff
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400 #define MATCH_SFENCE_VM 0x10400073
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401 #define MASK_SFENCE_VM 0xfff07fff
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402 #define MATCH_WFI 0x10500073
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403 #define MASK_WFI 0xffffffff
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404 #define MATCH_CSRRW 0x1073
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405 #define MASK_CSRRW 0x707f
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406 #define MATCH_CSRRS 0x2073
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407 #define MASK_CSRRS 0x707f
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408 #define MATCH_CSRRC 0x3073
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409 #define MASK_CSRRC 0x707f
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410 #define MATCH_CSRRWI 0x5073
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411 #define MASK_CSRRWI 0x707f
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412 #define MATCH_CSRRSI 0x6073
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413 #define MASK_CSRRSI 0x707f
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414 #define MATCH_CSRRCI 0x7073
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415 #define MASK_CSRRCI 0x707f
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416 #define MATCH_FADD_S 0x53
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417 #define MASK_FADD_S 0xfe00007f
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418 #define MATCH_FSUB_S 0x8000053
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419 #define MASK_FSUB_S 0xfe00007f
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420 #define MATCH_FMUL_S 0x10000053
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421 #define MASK_FMUL_S 0xfe00007f
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422 #define MATCH_FDIV_S 0x18000053
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423 #define MASK_FDIV_S 0xfe00007f
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424 #define MATCH_FSGNJ_S 0x20000053
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425 #define MASK_FSGNJ_S 0xfe00707f
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426 #define MATCH_FSGNJN_S 0x20001053
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427 #define MASK_FSGNJN_S 0xfe00707f
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428 #define MATCH_FSGNJX_S 0x20002053
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429 #define MASK_FSGNJX_S 0xfe00707f
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430 #define MATCH_FMIN_S 0x28000053
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431 #define MASK_FMIN_S 0xfe00707f
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432 #define MATCH_FMAX_S 0x28001053
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433 #define MASK_FMAX_S 0xfe00707f
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434 #define MATCH_FSQRT_S 0x58000053
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435 #define MASK_FSQRT_S 0xfff0007f
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436 #define MATCH_FADD_D 0x2000053
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437 #define MASK_FADD_D 0xfe00007f
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438 #define MATCH_FSUB_D 0xa000053
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439 #define MASK_FSUB_D 0xfe00007f
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440 #define MATCH_FMUL_D 0x12000053
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441 #define MASK_FMUL_D 0xfe00007f
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442 #define MATCH_FDIV_D 0x1a000053
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443 #define MASK_FDIV_D 0xfe00007f
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444 #define MATCH_FSGNJ_D 0x22000053
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445 #define MASK_FSGNJ_D 0xfe00707f
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446 #define MATCH_FSGNJN_D 0x22001053
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447 #define MASK_FSGNJN_D 0xfe00707f
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448 #define MATCH_FSGNJX_D 0x22002053
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449 #define MASK_FSGNJX_D 0xfe00707f
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450 #define MATCH_FMIN_D 0x2a000053
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451 #define MASK_FMIN_D 0xfe00707f
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452 #define MATCH_FMAX_D 0x2a001053
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453 #define MASK_FMAX_D 0xfe00707f
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454 #define MATCH_FCVT_S_D 0x40100053
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455 #define MASK_FCVT_S_D 0xfff0007f
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456 #define MATCH_FCVT_D_S 0x42000053
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457 #define MASK_FCVT_D_S 0xfff0007f
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458 #define MATCH_FSQRT_D 0x5a000053
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459 #define MASK_FSQRT_D 0xfff0007f
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460 #define MATCH_FLE_S 0xa0000053
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461 #define MASK_FLE_S 0xfe00707f
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462 #define MATCH_FLT_S 0xa0001053
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463 #define MASK_FLT_S 0xfe00707f
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464 #define MATCH_FEQ_S 0xa0002053
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465 #define MASK_FEQ_S 0xfe00707f
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466 #define MATCH_FLE_D 0xa2000053
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467 #define MASK_FLE_D 0xfe00707f
\r
468 #define MATCH_FLT_D 0xa2001053
\r
469 #define MASK_FLT_D 0xfe00707f
\r
470 #define MATCH_FEQ_D 0xa2002053
\r
471 #define MASK_FEQ_D 0xfe00707f
\r
472 #define MATCH_FCVT_W_S 0xc0000053
\r
473 #define MASK_FCVT_W_S 0xfff0007f
\r
474 #define MATCH_FCVT_WU_S 0xc0100053
\r
475 #define MASK_FCVT_WU_S 0xfff0007f
\r
476 #define MATCH_FCVT_L_S 0xc0200053
\r
477 #define MASK_FCVT_L_S 0xfff0007f
\r
478 #define MATCH_FCVT_LU_S 0xc0300053
\r
479 #define MASK_FCVT_LU_S 0xfff0007f
\r
480 #define MATCH_FMV_X_S 0xe0000053
\r
481 #define MASK_FMV_X_S 0xfff0707f
\r
482 #define MATCH_FCLASS_S 0xe0001053
\r
483 #define MASK_FCLASS_S 0xfff0707f
\r
484 #define MATCH_FCVT_W_D 0xc2000053
\r
485 #define MASK_FCVT_W_D 0xfff0007f
\r
486 #define MATCH_FCVT_WU_D 0xc2100053
\r
487 #define MASK_FCVT_WU_D 0xfff0007f
\r
488 #define MATCH_FCVT_L_D 0xc2200053
\r
489 #define MASK_FCVT_L_D 0xfff0007f
\r
490 #define MATCH_FCVT_LU_D 0xc2300053
\r
491 #define MASK_FCVT_LU_D 0xfff0007f
\r
492 #define MATCH_FMV_X_D 0xe2000053
\r
493 #define MASK_FMV_X_D 0xfff0707f
\r
494 #define MATCH_FCLASS_D 0xe2001053
\r
495 #define MASK_FCLASS_D 0xfff0707f
\r
496 #define MATCH_FCVT_S_W 0xd0000053
\r
497 #define MASK_FCVT_S_W 0xfff0007f
\r
498 #define MATCH_FCVT_S_WU 0xd0100053
\r
499 #define MASK_FCVT_S_WU 0xfff0007f
\r
500 #define MATCH_FCVT_S_L 0xd0200053
\r
501 #define MASK_FCVT_S_L 0xfff0007f
\r
502 #define MATCH_FCVT_S_LU 0xd0300053
\r
503 #define MASK_FCVT_S_LU 0xfff0007f
\r
504 #define MATCH_FMV_S_X 0xf0000053
\r
505 #define MASK_FMV_S_X 0xfff0707f
\r
506 #define MATCH_FCVT_D_W 0xd2000053
\r
507 #define MASK_FCVT_D_W 0xfff0007f
\r
508 #define MATCH_FCVT_D_WU 0xd2100053
\r
509 #define MASK_FCVT_D_WU 0xfff0007f
\r
510 #define MATCH_FCVT_D_L 0xd2200053
\r
511 #define MASK_FCVT_D_L 0xfff0007f
\r
512 #define MATCH_FCVT_D_LU 0xd2300053
\r
513 #define MASK_FCVT_D_LU 0xfff0007f
\r
514 #define MATCH_FMV_D_X 0xf2000053
\r
515 #define MASK_FMV_D_X 0xfff0707f
\r
516 #define MATCH_FLW 0x2007
\r
517 #define MASK_FLW 0x707f
\r
518 #define MATCH_FLD 0x3007
\r
519 #define MASK_FLD 0x707f
\r
520 #define MATCH_FSW 0x2027
\r
521 #define MASK_FSW 0x707f
\r
522 #define MATCH_FSD 0x3027
\r
523 #define MASK_FSD 0x707f
\r
524 #define MATCH_FMADD_S 0x43
\r
525 #define MASK_FMADD_S 0x600007f
\r
526 #define MATCH_FMSUB_S 0x47
\r
527 #define MASK_FMSUB_S 0x600007f
\r
528 #define MATCH_FNMSUB_S 0x4b
\r
529 #define MASK_FNMSUB_S 0x600007f
\r
530 #define MATCH_FNMADD_S 0x4f
\r
531 #define MASK_FNMADD_S 0x600007f
\r
532 #define MATCH_FMADD_D 0x2000043
\r
533 #define MASK_FMADD_D 0x600007f
\r
534 #define MATCH_FMSUB_D 0x2000047
\r
535 #define MASK_FMSUB_D 0x600007f
\r
536 #define MATCH_FNMSUB_D 0x200004b
\r
537 #define MASK_FNMSUB_D 0x600007f
\r
538 #define MATCH_FNMADD_D 0x200004f
\r
539 #define MASK_FNMADD_D 0x600007f
\r
540 #define MATCH_C_NOP 0x1
\r
541 #define MASK_C_NOP 0xffff
\r
542 #define MATCH_C_ADDI16SP 0x6101
\r
543 #define MASK_C_ADDI16SP 0xef83
\r
544 #define MATCH_C_JR 0x8002
\r
545 #define MASK_C_JR 0xf07f
\r
546 #define MATCH_C_JALR 0x9002
\r
547 #define MASK_C_JALR 0xf07f
\r
548 #define MATCH_C_EBREAK 0x9002
\r
549 #define MASK_C_EBREAK 0xffff
\r
550 #define MATCH_C_LD 0x6000
\r
551 #define MASK_C_LD 0xe003
\r
552 #define MATCH_C_SD 0xe000
\r
553 #define MASK_C_SD 0xe003
\r
554 #define MATCH_C_ADDIW 0x2001
\r
555 #define MASK_C_ADDIW 0xe003
\r
556 #define MATCH_C_LDSP 0x6002
\r
557 #define MASK_C_LDSP 0xe003
\r
558 #define MATCH_C_SDSP 0xe002
\r
559 #define MASK_C_SDSP 0xe003
\r
560 #define MATCH_C_ADDI4SPN 0x0
\r
561 #define MASK_C_ADDI4SPN 0xe003
\r
562 #define MATCH_C_FLD 0x2000
\r
563 #define MASK_C_FLD 0xe003
\r
564 #define MATCH_C_LW 0x4000
\r
565 #define MASK_C_LW 0xe003
\r
566 #define MATCH_C_FLW 0x6000
\r
567 #define MASK_C_FLW 0xe003
\r
568 #define MATCH_C_FSD 0xa000
\r
569 #define MASK_C_FSD 0xe003
\r
570 #define MATCH_C_SW 0xc000
\r
571 #define MASK_C_SW 0xe003
\r
572 #define MATCH_C_FSW 0xe000
\r
573 #define MASK_C_FSW 0xe003
\r
574 #define MATCH_C_ADDI 0x1
\r
575 #define MASK_C_ADDI 0xe003
\r
576 #define MATCH_C_JAL 0x2001
\r
577 #define MASK_C_JAL 0xe003
\r
578 #define MATCH_C_LI 0x4001
\r
579 #define MASK_C_LI 0xe003
\r
580 #define MATCH_C_LUI 0x6001
\r
581 #define MASK_C_LUI 0xe003
\r
582 #define MATCH_C_SRLI 0x8001
\r
583 #define MASK_C_SRLI 0xec03
\r
584 #define MATCH_C_SRAI 0x8401
\r
585 #define MASK_C_SRAI 0xec03
\r
586 #define MATCH_C_ANDI 0x8801
\r
587 #define MASK_C_ANDI 0xec03
\r
588 #define MATCH_C_SUB 0x8c01
\r
589 #define MASK_C_SUB 0xfc63
\r
590 #define MATCH_C_XOR 0x8c21
\r
591 #define MASK_C_XOR 0xfc63
\r
592 #define MATCH_C_OR 0x8c41
\r
593 #define MASK_C_OR 0xfc63
\r
594 #define MATCH_C_AND 0x8c61
\r
595 #define MASK_C_AND 0xfc63
\r
596 #define MATCH_C_SUBW 0x9c01
\r
597 #define MASK_C_SUBW 0xfc63
\r
598 #define MATCH_C_ADDW 0x9c21
\r
599 #define MASK_C_ADDW 0xfc63
\r
600 #define MATCH_C_J 0xa001
\r
601 #define MASK_C_J 0xe003
\r
602 #define MATCH_C_BEQZ 0xc001
\r
603 #define MASK_C_BEQZ 0xe003
\r
604 #define MATCH_C_BNEZ 0xe001
\r
605 #define MASK_C_BNEZ 0xe003
\r
606 #define MATCH_C_SLLI 0x2
\r
607 #define MASK_C_SLLI 0xe003
\r
608 #define MATCH_C_FLDSP 0x2002
\r
609 #define MASK_C_FLDSP 0xe003
\r
610 #define MATCH_C_LWSP 0x4002
\r
611 #define MASK_C_LWSP 0xe003
\r
612 #define MATCH_C_FLWSP 0x6002
\r
613 #define MASK_C_FLWSP 0xe003
\r
614 #define MATCH_C_MV 0x8002
\r
615 #define MASK_C_MV 0xf003
\r
616 #define MATCH_C_ADD 0x9002
\r
617 #define MASK_C_ADD 0xf003
\r
618 #define MATCH_C_FSDSP 0xa002
\r
619 #define MASK_C_FSDSP 0xe003
\r
620 #define MATCH_C_SWSP 0xc002
\r
621 #define MASK_C_SWSP 0xe003
\r
622 #define MATCH_C_FSWSP 0xe002
\r
623 #define MASK_C_FSWSP 0xe003
\r
624 #define MATCH_CUSTOM0 0xb
\r
625 #define MASK_CUSTOM0 0x707f
\r
626 #define MATCH_CUSTOM0_RS1 0x200b
\r
627 #define MASK_CUSTOM0_RS1 0x707f
\r
628 #define MATCH_CUSTOM0_RS1_RS2 0x300b
\r
629 #define MASK_CUSTOM0_RS1_RS2 0x707f
\r
630 #define MATCH_CUSTOM0_RD 0x400b
\r
631 #define MASK_CUSTOM0_RD 0x707f
\r
632 #define MATCH_CUSTOM0_RD_RS1 0x600b
\r
633 #define MASK_CUSTOM0_RD_RS1 0x707f
\r
634 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
\r
635 #define MASK_CUSTOM0_RD_RS1_RS2 0x707f
\r
636 #define MATCH_CUSTOM1 0x2b
\r
637 #define MASK_CUSTOM1 0x707f
\r
638 #define MATCH_CUSTOM1_RS1 0x202b
\r
639 #define MASK_CUSTOM1_RS1 0x707f
\r
640 #define MATCH_CUSTOM1_RS1_RS2 0x302b
\r
641 #define MASK_CUSTOM1_RS1_RS2 0x707f
\r
642 #define MATCH_CUSTOM1_RD 0x402b
\r
643 #define MASK_CUSTOM1_RD 0x707f
\r
644 #define MATCH_CUSTOM1_RD_RS1 0x602b
\r
645 #define MASK_CUSTOM1_RD_RS1 0x707f
\r
646 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
\r
647 #define MASK_CUSTOM1_RD_RS1_RS2 0x707f
\r
648 #define MATCH_CUSTOM2 0x5b
\r
649 #define MASK_CUSTOM2 0x707f
\r
650 #define MATCH_CUSTOM2_RS1 0x205b
\r
651 #define MASK_CUSTOM2_RS1 0x707f
\r
652 #define MATCH_CUSTOM2_RS1_RS2 0x305b
\r
653 #define MASK_CUSTOM2_RS1_RS2 0x707f
\r
654 #define MATCH_CUSTOM2_RD 0x405b
\r
655 #define MASK_CUSTOM2_RD 0x707f
\r
656 #define MATCH_CUSTOM2_RD_RS1 0x605b
\r
657 #define MASK_CUSTOM2_RD_RS1 0x707f
\r
658 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
\r
659 #define MASK_CUSTOM2_RD_RS1_RS2 0x707f
\r
660 #define MATCH_CUSTOM3 0x7b
\r
661 #define MASK_CUSTOM3 0x707f
\r
662 #define MATCH_CUSTOM3_RS1 0x207b
\r
663 #define MASK_CUSTOM3_RS1 0x707f
\r
664 #define MATCH_CUSTOM3_RS1_RS2 0x307b
\r
665 #define MASK_CUSTOM3_RS1_RS2 0x707f
\r
666 #define MATCH_CUSTOM3_RD 0x407b
\r
667 #define MASK_CUSTOM3_RD 0x707f
\r
668 #define MATCH_CUSTOM3_RD_RS1 0x607b
\r
669 #define MASK_CUSTOM3_RD_RS1 0x707f
\r
670 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
\r
671 #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
\r
672 #define CSR_FFLAGS 0x1
\r
673 #define CSR_FRM 0x2
\r
674 #define CSR_FCSR 0x3
\r
675 #define CSR_CYCLE 0xc00
\r
676 #define CSR_TIME 0xc01
\r
677 #define CSR_INSTRET 0xc02
\r
678 #define CSR_HPMCOUNTER3 0xc03
\r
679 #define CSR_HPMCOUNTER4 0xc04
\r
680 #define CSR_HPMCOUNTER5 0xc05
\r
681 #define CSR_HPMCOUNTER6 0xc06
\r
682 #define CSR_HPMCOUNTER7 0xc07
\r
683 #define CSR_HPMCOUNTER8 0xc08
\r
684 #define CSR_HPMCOUNTER9 0xc09
\r
685 #define CSR_HPMCOUNTER10 0xc0a
\r
686 #define CSR_HPMCOUNTER11 0xc0b
\r
687 #define CSR_HPMCOUNTER12 0xc0c
\r
688 #define CSR_HPMCOUNTER13 0xc0d
\r
689 #define CSR_HPMCOUNTER14 0xc0e
\r
690 #define CSR_HPMCOUNTER15 0xc0f
\r
691 #define CSR_HPMCOUNTER16 0xc10
\r
692 #define CSR_HPMCOUNTER17 0xc11
\r
693 #define CSR_HPMCOUNTER18 0xc12
\r
694 #define CSR_HPMCOUNTER19 0xc13
\r
695 #define CSR_HPMCOUNTER20 0xc14
\r
696 #define CSR_HPMCOUNTER21 0xc15
\r
697 #define CSR_HPMCOUNTER22 0xc16
\r
698 #define CSR_HPMCOUNTER23 0xc17
\r
699 #define CSR_HPMCOUNTER24 0xc18
\r
700 #define CSR_HPMCOUNTER25 0xc19
\r
701 #define CSR_HPMCOUNTER26 0xc1a
\r
702 #define CSR_HPMCOUNTER27 0xc1b
\r
703 #define CSR_HPMCOUNTER28 0xc1c
\r
704 #define CSR_HPMCOUNTER29 0xc1d
\r
705 #define CSR_HPMCOUNTER30 0xc1e
\r
706 #define CSR_HPMCOUNTER31 0xc1f
\r
707 #define CSR_SSTATUS 0x100
\r
708 #define CSR_SIE 0x104
\r
709 #define CSR_STVEC 0x105
\r
710 #define CSR_SSCRATCH 0x140
\r
711 #define CSR_SEPC 0x141
\r
712 #define CSR_SCAUSE 0x142
\r
713 #define CSR_SBADADDR 0x143
\r
714 #define CSR_SIP 0x144
\r
715 #define CSR_SPTBR 0x180
\r
716 #define CSR_MSTATUS 0x300
\r
717 #define CSR_MISA 0x301
\r
718 #define CSR_MEDELEG 0x302
\r
719 #define CSR_MIDELEG 0x303
\r
720 #define CSR_MIE 0x304
\r
721 #define CSR_MTVEC 0x305
\r
722 #define CSR_MSCRATCH 0x340
\r
723 #define CSR_MEPC 0x341
\r
724 #define CSR_MCAUSE 0x342
\r
725 #define CSR_MBADADDR 0x343
\r
726 #define CSR_MIP 0x344
\r
727 #define CSR_TSELECT 0x7a0
\r
728 #define CSR_TDATA1 0x7a1
\r
729 #define CSR_TDATA2 0x7a2
\r
730 #define CSR_TDATA3 0x7a3
\r
731 #define CSR_DCSR 0x7b0
\r
732 #define CSR_DPC 0x7b1
\r
733 #define CSR_DSCRATCH 0x7b2
\r
734 #define CSR_MCYCLE 0xb00
\r
735 #define CSR_MINSTRET 0xb02
\r
736 #define CSR_MHPMCOUNTER3 0xb03
\r
737 #define CSR_MHPMCOUNTER4 0xb04
\r
738 #define CSR_MHPMCOUNTER5 0xb05
\r
739 #define CSR_MHPMCOUNTER6 0xb06
\r
740 #define CSR_MHPMCOUNTER7 0xb07
\r
741 #define CSR_MHPMCOUNTER8 0xb08
\r
742 #define CSR_MHPMCOUNTER9 0xb09
\r
743 #define CSR_MHPMCOUNTER10 0xb0a
\r
744 #define CSR_MHPMCOUNTER11 0xb0b
\r
745 #define CSR_MHPMCOUNTER12 0xb0c
\r
746 #define CSR_MHPMCOUNTER13 0xb0d
\r
747 #define CSR_MHPMCOUNTER14 0xb0e
\r
748 #define CSR_MHPMCOUNTER15 0xb0f
\r
749 #define CSR_MHPMCOUNTER16 0xb10
\r
750 #define CSR_MHPMCOUNTER17 0xb11
\r
751 #define CSR_MHPMCOUNTER18 0xb12
\r
752 #define CSR_MHPMCOUNTER19 0xb13
\r
753 #define CSR_MHPMCOUNTER20 0xb14
\r
754 #define CSR_MHPMCOUNTER21 0xb15
\r
755 #define CSR_MHPMCOUNTER22 0xb16
\r
756 #define CSR_MHPMCOUNTER23 0xb17
\r
757 #define CSR_MHPMCOUNTER24 0xb18
\r
758 #define CSR_MHPMCOUNTER25 0xb19
\r
759 #define CSR_MHPMCOUNTER26 0xb1a
\r
760 #define CSR_MHPMCOUNTER27 0xb1b
\r
761 #define CSR_MHPMCOUNTER28 0xb1c
\r
762 #define CSR_MHPMCOUNTER29 0xb1d
\r
763 #define CSR_MHPMCOUNTER30 0xb1e
\r
764 #define CSR_MHPMCOUNTER31 0xb1f
\r
765 #define CSR_MUCOUNTEREN 0x320
\r
766 #define CSR_MSCOUNTEREN 0x321
\r
767 #define CSR_MHPMEVENT3 0x323
\r
768 #define CSR_MHPMEVENT4 0x324
\r
769 #define CSR_MHPMEVENT5 0x325
\r
770 #define CSR_MHPMEVENT6 0x326
\r
771 #define CSR_MHPMEVENT7 0x327
\r
772 #define CSR_MHPMEVENT8 0x328
\r
773 #define CSR_MHPMEVENT9 0x329
\r
774 #define CSR_MHPMEVENT10 0x32a
\r
775 #define CSR_MHPMEVENT11 0x32b
\r
776 #define CSR_MHPMEVENT12 0x32c
\r
777 #define CSR_MHPMEVENT13 0x32d
\r
778 #define CSR_MHPMEVENT14 0x32e
\r
779 #define CSR_MHPMEVENT15 0x32f
\r
780 #define CSR_MHPMEVENT16 0x330
\r
781 #define CSR_MHPMEVENT17 0x331
\r
782 #define CSR_MHPMEVENT18 0x332
\r
783 #define CSR_MHPMEVENT19 0x333
\r
784 #define CSR_MHPMEVENT20 0x334
\r
785 #define CSR_MHPMEVENT21 0x335
\r
786 #define CSR_MHPMEVENT22 0x336
\r
787 #define CSR_MHPMEVENT23 0x337
\r
788 #define CSR_MHPMEVENT24 0x338
\r
789 #define CSR_MHPMEVENT25 0x339
\r
790 #define CSR_MHPMEVENT26 0x33a
\r
791 #define CSR_MHPMEVENT27 0x33b
\r
792 #define CSR_MHPMEVENT28 0x33c
\r
793 #define CSR_MHPMEVENT29 0x33d
\r
794 #define CSR_MHPMEVENT30 0x33e
\r
795 #define CSR_MHPMEVENT31 0x33f
\r
796 #define CSR_MVENDORID 0xf11
\r
797 #define CSR_MARCHID 0xf12
\r
798 #define CSR_MIMPID 0xf13
\r
799 #define CSR_MHARTID 0xf14
\r
800 #define CSR_CYCLEH 0xc80
\r
801 #define CSR_TIMEH 0xc81
\r
802 #define CSR_INSTRETH 0xc82
\r
803 #define CSR_HPMCOUNTER3H 0xc83
\r
804 #define CSR_HPMCOUNTER4H 0xc84
\r
805 #define CSR_HPMCOUNTER5H 0xc85
\r
806 #define CSR_HPMCOUNTER6H 0xc86
\r
807 #define CSR_HPMCOUNTER7H 0xc87
\r
808 #define CSR_HPMCOUNTER8H 0xc88
\r
809 #define CSR_HPMCOUNTER9H 0xc89
\r
810 #define CSR_HPMCOUNTER10H 0xc8a
\r
811 #define CSR_HPMCOUNTER11H 0xc8b
\r
812 #define CSR_HPMCOUNTER12H 0xc8c
\r
813 #define CSR_HPMCOUNTER13H 0xc8d
\r
814 #define CSR_HPMCOUNTER14H 0xc8e
\r
815 #define CSR_HPMCOUNTER15H 0xc8f
\r
816 #define CSR_HPMCOUNTER16H 0xc90
\r
817 #define CSR_HPMCOUNTER17H 0xc91
\r
818 #define CSR_HPMCOUNTER18H 0xc92
\r
819 #define CSR_HPMCOUNTER19H 0xc93
\r
820 #define CSR_HPMCOUNTER20H 0xc94
\r
821 #define CSR_HPMCOUNTER21H 0xc95
\r
822 #define CSR_HPMCOUNTER22H 0xc96
\r
823 #define CSR_HPMCOUNTER23H 0xc97
\r
824 #define CSR_HPMCOUNTER24H 0xc98
\r
825 #define CSR_HPMCOUNTER25H 0xc99
\r
826 #define CSR_HPMCOUNTER26H 0xc9a
\r
827 #define CSR_HPMCOUNTER27H 0xc9b
\r
828 #define CSR_HPMCOUNTER28H 0xc9c
\r
829 #define CSR_HPMCOUNTER29H 0xc9d
\r
830 #define CSR_HPMCOUNTER30H 0xc9e
\r
831 #define CSR_HPMCOUNTER31H 0xc9f
\r
832 #define CSR_MCYCLEH 0xb80
\r
833 #define CSR_MINSTRETH 0xb82
\r
834 #define CSR_MHPMCOUNTER3H 0xb83
\r
835 #define CSR_MHPMCOUNTER4H 0xb84
\r
836 #define CSR_MHPMCOUNTER5H 0xb85
\r
837 #define CSR_MHPMCOUNTER6H 0xb86
\r
838 #define CSR_MHPMCOUNTER7H 0xb87
\r
839 #define CSR_MHPMCOUNTER8H 0xb88
\r
840 #define CSR_MHPMCOUNTER9H 0xb89
\r
841 #define CSR_MHPMCOUNTER10H 0xb8a
\r
842 #define CSR_MHPMCOUNTER11H 0xb8b
\r
843 #define CSR_MHPMCOUNTER12H 0xb8c
\r
844 #define CSR_MHPMCOUNTER13H 0xb8d
\r
845 #define CSR_MHPMCOUNTER14H 0xb8e
\r
846 #define CSR_MHPMCOUNTER15H 0xb8f
\r
847 #define CSR_MHPMCOUNTER16H 0xb90
\r
848 #define CSR_MHPMCOUNTER17H 0xb91
\r
849 #define CSR_MHPMCOUNTER18H 0xb92
\r
850 #define CSR_MHPMCOUNTER19H 0xb93
\r
851 #define CSR_MHPMCOUNTER20H 0xb94
\r
852 #define CSR_MHPMCOUNTER21H 0xb95
\r
853 #define CSR_MHPMCOUNTER22H 0xb96
\r
854 #define CSR_MHPMCOUNTER23H 0xb97
\r
855 #define CSR_MHPMCOUNTER24H 0xb98
\r
856 #define CSR_MHPMCOUNTER25H 0xb99
\r
857 #define CSR_MHPMCOUNTER26H 0xb9a
\r
858 #define CSR_MHPMCOUNTER27H 0xb9b
\r
859 #define CSR_MHPMCOUNTER28H 0xb9c
\r
860 #define CSR_MHPMCOUNTER29H 0xb9d
\r
861 #define CSR_MHPMCOUNTER30H 0xb9e
\r
862 #define CSR_MHPMCOUNTER31H 0xb9f
\r
863 #define CAUSE_MISALIGNED_FETCH 0x0
\r
864 #define CAUSE_FAULT_FETCH 0x1
\r
865 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
\r
866 #define CAUSE_BREAKPOINT 0x3
\r
867 #define CAUSE_MISALIGNED_LOAD 0x4
\r
868 #define CAUSE_FAULT_LOAD 0x5
\r
869 #define CAUSE_MISALIGNED_STORE 0x6
\r
870 #define CAUSE_FAULT_STORE 0x7
\r
871 #define CAUSE_USER_ECALL 0x8
\r
872 #define CAUSE_SUPERVISOR_ECALL 0x9
\r
873 #define CAUSE_HYPERVISOR_ECALL 0xa
\r
874 #define CAUSE_MACHINE_ECALL 0xb
\r
876 #ifdef DECLARE_INSN
\r
877 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
\r
878 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
\r
879 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
\r
880 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
\r
881 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
\r
882 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
\r
883 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
\r
884 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
\r
885 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
\r
886 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
\r
887 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
\r
888 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
\r
889 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
\r
890 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
\r
891 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
\r
892 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
\r
893 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
\r
894 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
\r
895 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
\r
896 DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
\r
897 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
\r
898 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
\r
899 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
\r
900 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
\r
901 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
\r
902 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
\r
903 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
\r
904 DECLARE_INSN(or, MATCH_OR, MASK_OR)
\r
905 DECLARE_INSN(and, MATCH_AND, MASK_AND)
\r
906 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
\r
907 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
\r
908 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
\r
909 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
\r
910 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
\r
911 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
\r
912 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
\r
913 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
\r
914 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
\r
915 DECLARE_INSN(lb, MATCH_LB, MASK_LB)
\r
916 DECLARE_INSN(lh, MATCH_LH, MASK_LH)
\r
917 DECLARE_INSN(lw, MATCH_LW, MASK_LW)
\r
918 DECLARE_INSN(ld, MATCH_LD, MASK_LD)
\r
919 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
\r
920 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
\r
921 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
\r
922 DECLARE_INSN(sb, MATCH_SB, MASK_SB)
\r
923 DECLARE_INSN(sh, MATCH_SH, MASK_SH)
\r
924 DECLARE_INSN(sw, MATCH_SW, MASK_SW)
\r
925 DECLARE_INSN(sd, MATCH_SD, MASK_SD)
\r
926 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
\r
927 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
\r
928 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
\r
929 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
\r
930 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
\r
931 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
\r
932 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
\r
933 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
\r
934 DECLARE_INSN(rem, MATCH_REM, MASK_REM)
\r
935 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
\r
936 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
\r
937 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
\r
938 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
\r
939 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
\r
940 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
\r
941 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
\r
942 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
\r
943 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
\r
944 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
\r
945 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
\r
946 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
\r
947 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
\r
948 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
\r
949 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
\r
950 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
\r
951 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
\r
952 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
\r
953 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
\r
954 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
\r
955 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
\r
956 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
\r
957 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
\r
958 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
\r
959 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
\r
960 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
\r
961 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
\r
962 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
\r
963 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
\r
964 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
\r
965 DECLARE_INSN(uret, MATCH_URET, MASK_URET)
\r
966 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
\r
967 DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
\r
968 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
\r
969 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
\r
970 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
\r
971 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
\r
972 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
\r
973 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
\r
974 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
\r
975 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
\r
976 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
\r
977 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
\r
978 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
\r
979 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
\r
980 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
\r
981 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
\r
982 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
\r
983 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
\r
984 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
\r
985 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
\r
986 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
\r
987 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
\r
988 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
\r
989 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
\r
990 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
\r
991 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
\r
992 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
\r
993 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
\r
994 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
\r
995 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
\r
996 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
\r
997 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
\r
998 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
\r
999 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
\r
1000 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
\r
1001 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
\r
1002 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
\r
1003 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
\r
1004 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
\r
1005 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
\r
1006 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
\r
1007 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
\r
1008 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
\r
1009 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
\r
1010 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
\r
1011 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
\r
1012 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
\r
1013 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
\r
1014 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
\r
1015 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
\r
1016 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
\r
1017 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
\r
1018 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
\r
1019 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
\r
1020 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
\r
1021 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
\r
1022 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
\r
1023 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
\r
1024 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
\r
1025 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
\r
1026 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
\r
1027 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
\r
1028 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
\r
1029 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
\r
1030 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
\r
1031 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
\r
1032 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
\r
1033 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
\r
1034 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
\r
1035 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
\r
1036 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
\r
1037 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
\r
1038 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
\r
1039 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
\r
1040 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
\r
1041 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
\r
1042 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
\r
1043 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
\r
1044 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
\r
1045 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
\r
1046 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
\r
1047 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
\r
1048 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
\r
1049 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
\r
1050 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
\r
1051 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
\r
1052 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
\r
1053 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
\r
1054 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
\r
1055 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
\r
1056 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
\r
1057 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
\r
1058 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
\r
1059 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
\r
1060 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
\r
1061 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
\r
1062 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
\r
1063 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
\r
1064 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
\r
1065 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
\r
1066 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
\r
1067 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
\r
1068 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
\r
1069 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
\r
1070 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
\r
1071 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
\r
1072 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
\r
1073 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
\r
1074 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
\r
1075 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
\r
1076 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
\r
1077 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
\r
1078 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
\r
1079 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
\r
1080 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
\r
1081 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
\r
1082 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
\r
1083 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
\r
1084 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
\r
1085 DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
\r
1086 DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
\r
1087 DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
\r
1088 DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
\r
1089 DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
\r
1090 DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
\r
1091 DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
\r
1092 DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
\r
1093 DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
\r
1094 DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
\r
1095 DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
\r
1096 DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
\r
1097 DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
\r
1098 DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
\r
1099 DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
\r
1100 DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
\r
1101 DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
\r
1102 DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
\r
1103 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
\r
1104 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
\r
1105 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
\r
1107 #ifdef DECLARE_CSR
\r
1108 DECLARE_CSR(fflags, CSR_FFLAGS)
\r
1109 DECLARE_CSR(frm, CSR_FRM)
\r
1110 DECLARE_CSR(fcsr, CSR_FCSR)
\r
1111 DECLARE_CSR(cycle, CSR_CYCLE)
\r
1112 DECLARE_CSR(time, CSR_TIME)
\r
1113 DECLARE_CSR(instret, CSR_INSTRET)
\r
1114 DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
\r
1115 DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
\r
1116 DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
\r
1117 DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
\r
1118 DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
\r
1119 DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
\r
1120 DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
\r
1121 DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
\r
1122 DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
\r
1123 DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
\r
1124 DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
\r
1125 DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
\r
1126 DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
\r
1127 DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
\r
1128 DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
\r
1129 DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
\r
1130 DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
\r
1131 DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
\r
1132 DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
\r
1133 DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
\r
1134 DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
\r
1135 DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
\r
1136 DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
\r
1137 DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
\r
1138 DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
\r
1139 DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
\r
1140 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
\r
1141 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
\r
1142 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
\r
1143 DECLARE_CSR(sstatus, CSR_SSTATUS)
\r
1144 DECLARE_CSR(sie, CSR_SIE)
\r
1145 DECLARE_CSR(stvec, CSR_STVEC)
\r
1146 DECLARE_CSR(sscratch, CSR_SSCRATCH)
\r
1147 DECLARE_CSR(sepc, CSR_SEPC)
\r
1148 DECLARE_CSR(scause, CSR_SCAUSE)
\r
1149 DECLARE_CSR(sbadaddr, CSR_SBADADDR)
\r
1150 DECLARE_CSR(sip, CSR_SIP)
\r
1151 DECLARE_CSR(sptbr, CSR_SPTBR)
\r
1152 DECLARE_CSR(mstatus, CSR_MSTATUS)
\r
1153 DECLARE_CSR(misa, CSR_MISA)
\r
1154 DECLARE_CSR(medeleg, CSR_MEDELEG)
\r
1155 DECLARE_CSR(mideleg, CSR_MIDELEG)
\r
1156 DECLARE_CSR(mie, CSR_MIE)
\r
1157 DECLARE_CSR(mtvec, CSR_MTVEC)
\r
1158 DECLARE_CSR(mscratch, CSR_MSCRATCH)
\r
1159 DECLARE_CSR(mepc, CSR_MEPC)
\r
1160 DECLARE_CSR(mcause, CSR_MCAUSE)
\r
1161 DECLARE_CSR(mbadaddr, CSR_MBADADDR)
\r
1162 DECLARE_CSR(mip, CSR_MIP)
\r
1163 DECLARE_CSR(tselect, CSR_TSELECT)
\r
1164 DECLARE_CSR(tdata1, CSR_TDATA1)
\r
1165 DECLARE_CSR(tdata2, CSR_TDATA2)
\r
1166 DECLARE_CSR(tdata3, CSR_TDATA3)
\r
1167 DECLARE_CSR(dcsr, CSR_DCSR)
\r
1168 DECLARE_CSR(dpc, CSR_DPC)
\r
1169 DECLARE_CSR(dscratch, CSR_DSCRATCH)
\r
1170 DECLARE_CSR(mcycle, CSR_MCYCLE)
\r
1171 DECLARE_CSR(minstret, CSR_MINSTRET)
\r
1172 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
\r
1173 DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
\r
1174 DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
\r
1175 DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
\r
1176 DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
\r
1177 DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
\r
1178 DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
\r
1179 DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
\r
1180 DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
\r
1181 DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
\r
1182 DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
\r
1183 DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
\r
1184 DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
\r
1185 DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
\r
1186 DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
\r
1187 DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
\r
1188 DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
\r
1189 DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
\r
1190 DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
\r
1191 DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
\r
1192 DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
\r
1193 DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
\r
1194 DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
\r
1195 DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
\r
1196 DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
\r
1197 DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
\r
1198 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
\r
1199 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
\r
1200 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
\r
1201 DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
\r
1202 DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
\r
1203 DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
\r
1204 DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
\r
1205 DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
\r
1206 DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
\r
1207 DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
\r
1208 DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
\r
1209 DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
\r
1210 DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
\r
1211 DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
\r
1212 DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
\r
1213 DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
\r
1214 DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
\r
1215 DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
\r
1216 DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
\r
1217 DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
\r
1218 DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
\r
1219 DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
\r
1220 DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
\r
1221 DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
\r
1222 DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
\r
1223 DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
\r
1224 DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
\r
1225 DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
\r
1226 DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
\r
1227 DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
\r
1228 DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
\r
1229 DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
\r
1230 DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
\r
1231 DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
\r
1232 DECLARE_CSR(mvendorid, CSR_MVENDORID)
\r
1233 DECLARE_CSR(marchid, CSR_MARCHID)
\r
1234 DECLARE_CSR(mimpid, CSR_MIMPID)
\r
1235 DECLARE_CSR(mhartid, CSR_MHARTID)
\r
1236 DECLARE_CSR(cycleh, CSR_CYCLEH)
\r
1237 DECLARE_CSR(timeh, CSR_TIMEH)
\r
1238 DECLARE_CSR(instreth, CSR_INSTRETH)
\r
1239 DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
\r
1240 DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
\r
1241 DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
\r
1242 DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
\r
1243 DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
\r
1244 DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
\r
1245 DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
\r
1246 DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
\r
1247 DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
\r
1248 DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
\r
1249 DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
\r
1250 DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
\r
1251 DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
\r
1252 DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
\r
1253 DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
\r
1254 DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
\r
1255 DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
\r
1256 DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
\r
1257 DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
\r
1258 DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
\r
1259 DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
\r
1260 DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
\r
1261 DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
\r
1262 DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
\r
1263 DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
\r
1264 DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
\r
1265 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
\r
1266 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
\r
1267 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
\r
1268 DECLARE_CSR(mcycleh, CSR_MCYCLEH)
\r
1269 DECLARE_CSR(minstreth, CSR_MINSTRETH)
\r
1270 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
\r
1271 DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
\r
1272 DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
\r
1273 DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
\r
1274 DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
\r
1275 DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
\r
1276 DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
\r
1277 DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
\r
1278 DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
\r
1279 DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
\r
1280 DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
\r
1281 DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
\r
1282 DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
\r
1283 DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
\r
1284 DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
\r
1285 DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
\r
1286 DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
\r
1287 DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
\r
1288 DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
\r
1289 DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
\r
1290 DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
\r
1291 DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
\r
1292 DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
\r
1293 DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
\r
1294 DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
\r
1295 DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
\r
1296 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
\r
1297 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
\r
1298 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
\r
1300 #ifdef DECLARE_CAUSE
\r
1301 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
\r
1302 DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
\r
1303 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
\r
1304 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
\r
1305 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
\r
1306 DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
\r
1307 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
\r
1308 DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
\r
1309 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
\r
1310 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
\r
1311 DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
\r
1312 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
\r
projects / freertos / blob