git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/settings/RTOSDemo.dnx

   1 <?xml version="1.0"?>\r
   2 <settings>\r
   3     <Stack>\r
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   6         <WarningThreshold>90</WarningThreshold>\r
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  10         <TriggerName>main</TriggerName>\r
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  12         <ByteLimit>50</ByteLimit>\r
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  14     <DebugChecksum>\r
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  16     </DebugChecksum>\r
  17     <Disassembly>\r
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  20     </Disassembly>\r
  21     <CodeCoverage>\r
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  29     <DataAlign>\r
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  33     <Jet>\r
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  35         <JetConnFoundProbes />\r
  36         <PrevWtdReset>Hardware</PrevWtdReset>\r
  37         <OnlineReset>Software</OnlineReset>\r
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  39         <LeaveRunning>1</LeaveRunning>\r
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  41     </Jet>\r
  42     <PlDriver>\r
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  44         <MemConfigValue>C:\devtools\IAR Systems\Embedded Workbench 8.3\riscv\config\debugger\SiFive\hifive1.ddf</MemConfigValue>\r
  45     </PlDriver>\r
  46     <RiscvDriver>\r
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  48     </RiscvDriver>\r
  49     <Trace1>\r
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  73     <DataLog>\r
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  80     <Interrupts>\r
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  82     </Interrupts>\r
  83     <MemConfig>\r
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  86         <Ddf>1</Ddf>\r
  87         <TypeViol>0</TypeViol>\r
  88         <Stop>1</Stop>\r
  89     </MemConfig>\r
  90     <Simulator>\r
  91         <Freq>50000000</Freq>\r
  92         <FreqHi>0</FreqHi>\r
  93         <MultiCoreRunAll>1</MultiCoreRunAll>\r
  94     </Simulator>\r
  95     <SfrWindow>\r
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  98     </SfrWindow>\r
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 107     </LogFile>\r
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 118     </Aliases>\r
 119 </settings>\r