git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c

   1 /*\r
   2     FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
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   6 \r
   7     ***************************************************************************\r
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  23      *                                                                       *\r
  24     ***************************************************************************\r
  25 \r
  26 \r
  27     This file is part of the FreeRTOS distribution.\r
  28 \r
  29     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  30     the terms of the GNU General Public License (version 2) as published by the\r
  31     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  32 \r
  33     >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
  34     distribute a combined work that includes FreeRTOS without being obliged to\r
  35     provide the source code for proprietary components outside of the FreeRTOS\r
  36     kernel.\r
  37 \r
  38     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  39     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  40     FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
  41     details. You should have received a copy of the GNU General Public License\r
  42     and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
  43     viewed here: http://www.freertos.org/a00114.html and also obtained by\r
  44     writing to Real Time Engineers Ltd., contact details for whom are available\r
  45     on the FreeRTOS WEB site.\r
  46 \r
  47     1 tab == 4 spaces!\r
  48 \r
  49     ***************************************************************************\r
  50      *                                                                       *\r
  51      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  52      *    not run, what could be wrong?"                                     *\r
  53      *                                                                       *\r
  54      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  55      *                                                                       *\r
  56     ***************************************************************************\r
  57 \r
  58 \r
  59     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  60     license and Real Time Engineers Ltd. contact details.\r
  61 \r
  62     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  63     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
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  65 \r
  66     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  67     Integrity Systems, who sell the code with commercial support,\r
  68     indemnification and middleware, under the OpenRTOS brand.\r
  69 \r
  70     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  71     engineered and independently SIL3 certified version for use in safety and\r
  72     mission critical applications that require provable dependability.\r
  73 */\r
  74 \r
  75 /*-----------------------------------------------------------\r
  76  * Implementation of functions defined in portable.h for the ARM CM4F port.\r
  77  *----------------------------------------------------------*/\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "task.h"\r
  82 \r
  83 #ifndef __VFP_FP__\r
  84         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  85 #endif\r
  86 \r
  87 #ifndef configSYSTICK_CLOCK_HZ\r
  88         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  89 #endif\r
  90 \r
  91 /* Constants required to manipulate the core.  Registers first... */\r
  92 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  93 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  95 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  96 /* ...then bits in the registers. */\r
  97 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
  98 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  99 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
 100 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 101 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 102 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 103 \r
 104 #define portNVIC_PENDSV_PRI                             ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 105 #define portNVIC_SYSTICK_PRI                    ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 106 \r
 107 /* Constants required to manipulate the VFP. */\r
 108 #define portFPCCR                                       ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
 109 #define portASPEN_AND_LSPEN_BITS        ( 0x3UL << 30UL )\r
 110 \r
 111 /* Constants required to set up the initial stack. */\r
 112 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 113 #define portINITIAL_EXEC_RETURN         ( 0xfffffffd )\r
 114 \r
 115 /* The priority used by the kernel is assigned to a variable to make access\r
 116 from inline assembler easier. */\r
 117 const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
 118 \r
 119 /* Each task maintains its own interrupt status in the critical nesting\r
 120 variable. */\r
 121 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 122 \r
 123 /*\r
 124  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 125  * file is weak to allow application writers to change the timer used to\r
 126  * generate the tick interrupt.\r
 127  */\r
 128 void vPortSetupTimerInterrupt( void );\r
 129 \r
 130 /*\r
 131  * Exception handlers.\r
 132  */\r
 133 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 134 void xPortSysTickHandler( void );\r
 135 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 136 \r
 137 /*\r
 138  * Start first task is a separate function so it can be tested in isolation.\r
 139  */\r
 140 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 141 \r
 142 /*\r
 143  * Function to enable the VFP.\r
 144  */\r
 145  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 146 \r
 147 /*-----------------------------------------------------------*/\r
 148 \r
 149 /*\r
 150  * The number of SysTick increments that make up one tick period.\r
 151  */\r
 152 #if configUSE_TICKLESS_IDLE == 1\r
 153         static unsigned long ulTimerReloadValueForOneTick = 0;\r
 154 #endif\r
 155 \r
 156 /*\r
 157  * The maximum number of tick periods that can be suppressed is limited by the\r
 158  * 24 bit resolution of the SysTick timer.\r
 159  */\r
 160 #if configUSE_TICKLESS_IDLE == 1\r
 161         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 162 #endif /* configUSE_TICKLESS_IDLE */\r
 163 \r
 164 /*\r
 165  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 166  * power functionality only.\r
 167  */\r
 168 #if configUSE_TICKLESS_IDLE == 1\r
 169         static unsigned long ulStoppedTimerCompensation = 0;\r
 170 #endif /* configUSE_TICKLESS_IDLE */\r
 171 \r
 172 /*-----------------------------------------------------------*/\r
 173 \r
 174 /*\r
 175  * See header file for description.\r
 176  */\r
 177 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 178 {\r
 179         /* Simulate the stack frame as it would be created by a context switch\r
 180         interrupt. */\r
 181 \r
 182         /* Offset added to account for the way the MCU uses the stack on entry/exit\r
 183         of interrupts, and to ensure alignment. */\r
 184         pxTopOfStack--;\r
 185 \r
 186         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 187         pxTopOfStack--;\r
 188         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 189         pxTopOfStack--;\r
 190         *pxTopOfStack = 0;      /* LR */\r
 191 \r
 192         /* Save code space by skipping register initialisation. */\r
 193         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 194         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 195 \r
 196         /* A save method is being used that requires each task to maintain its\r
 197         own exec return value. */\r
 198         pxTopOfStack--;\r
 199         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 200 \r
 201         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 202 \r
 203         return pxTopOfStack;\r
 204 }\r
 205 /*-----------------------------------------------------------*/\r
 206 \r
 207 void vPortSVCHandler( void )\r
 208 {\r
 209         __asm volatile (\r
 210                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 211                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 212                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 213                                         "       ldmia r0!, {r4-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 214                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 215                                         "       mov r0, #0                                              \n"\r
 216                                         "       msr     basepri, r0                                     \n"\r
 217                                         "       bx r14                                                  \n"\r
 218                                         "                                                                       \n"\r
 219                                         "       .align 2                                                \n"\r
 220                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 221                                 );\r
 222 }\r
 223 /*-----------------------------------------------------------*/\r
 224 \r
 225 static void prvPortStartFirstTask( void )\r
 226 {\r
 227         __asm volatile(\r
 228                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 229                                         " ldr r0, [r0]                  \n"\r
 230                                         " ldr r0, [r0]                  \n"\r
 231                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 232                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 233                                         " svc 0                                 \n" /* System call to start first task. */\r
 234                                         " nop                                   \n"\r
 235                                 );\r
 236 }\r
 237 /*-----------------------------------------------------------*/\r
 238 \r
 239 /*\r
 240  * See header file for description.\r
 241  */\r
 242 portBASE_TYPE xPortStartScheduler( void )\r
 243 {\r
 244         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 245         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 246         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 247 \r
 248         /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
 249         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 250         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 251 \r
 252         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 253         here already. */\r
 254         vPortSetupTimerInterrupt();\r
 255 \r
 256         /* Initialise the critical nesting count ready for the first task. */\r
 257         uxCriticalNesting = 0;\r
 258 \r
 259         /* Ensure the VFP is enabled - it should be anyway. */\r
 260         vPortEnableVFP();\r
 261 \r
 262         /* Lazy save always. */\r
 263         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 264 \r
 265         /* Start the first task. */\r
 266         prvPortStartFirstTask();\r
 267 \r
 268         /* Should not get here! */\r
 269         return 0;\r
 270 }\r
 271 /*-----------------------------------------------------------*/\r
 272 \r
 273 void vPortEndScheduler( void )\r
 274 {\r
 275         /* It is unlikely that the CM4F port will require this function as there\r
 276         is nothing to return to.  */\r
 277 }\r
 278 /*-----------------------------------------------------------*/\r
 279 \r
 280 void vPortYield( void )\r
 281 {\r
 282         /* Set a PendSV to request a context switch. */\r
 283         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 284 \r
 285         /* Barriers are normally not required but do ensure the code is completely\r
 286         within the specified behaviour for the architecture. */\r
 287         __asm volatile( "dsb" );\r
 288         __asm volatile( "isb" );\r
 289 }\r
 290 /*-----------------------------------------------------------*/\r
 291 \r
 292 void vPortEnterCritical( void )\r
 293 {\r
 294         portDISABLE_INTERRUPTS();\r
 295         uxCriticalNesting++;\r
 296         __asm volatile( "dsb" );\r
 297         __asm volatile( "isb" );\r
 298 }\r
 299 /*-----------------------------------------------------------*/\r
 300 \r
 301 void vPortExitCritical( void )\r
 302 {\r
 303         uxCriticalNesting--;\r
 304         if( uxCriticalNesting == 0 )\r
 305         {\r
 306                 portENABLE_INTERRUPTS();\r
 307         }\r
 308 }\r
 309 /*-----------------------------------------------------------*/\r
 310 \r
 311 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 312 {\r
 313         __asm volatile                                                                                                          \\r
 314         (                                                                                                                                       \\r
 315                 "       mrs r0, basepri                                                                                 \n" \\r
 316                 "       mov r1, %0                                                                                              \n"     \\r
 317                 "       msr basepri, r1                                                                                 \n" \\r
 318                 "       bx lr                                                                                                   \n" \\r
 319                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 320         );\r
 321 \r
 322         /* This return will not be reached but is necessary to prevent compiler\r
 323         warnings. */\r
 324         return 0;\r
 325 }\r
 326 /*-----------------------------------------------------------*/\r
 327 \r
 328 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 329 {\r
 330         __asm volatile                                                                                                  \\r
 331         (                                                                                                                               \\r
 332                 "       msr basepri, r0                                                                         \n"     \\r
 333                 "       bx lr                                                                                           \n" \\r
 334                 :::"r0"                                                                                                         \\r
 335         );\r
 336 \r
 337         /* Just to avoid compiler warnings. */\r
 338         ( void ) ulNewMaskValue;\r
 339 }\r
 340 /*-----------------------------------------------------------*/\r
 341 \r
 342 void xPortPendSVHandler( void )\r
 343 {\r
 344         /* This is a naked function. */\r
 345 \r
 346         __asm volatile\r
 347         (\r
 348         "       mrs r0, psp                                                     \n"\r
 349         "                                                                               \n"\r
 350         "       ldr     r3, pxCurrentTCBConst                           \n" /* Get the location of the current TCB. */\r
 351         "       ldr     r2, [r3]                                                \n"\r
 352         "                                                                               \n"\r
 353         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 354         "       it eq                                                           \n"\r
 355         "       vstmdbeq r0!, {s16-s31}                         \n"\r
 356         "                                                                               \n"\r
 357         "       stmdb r0!, {r4-r11, r14}                        \n" /* Save the core registers. */\r
 358         "                                                                               \n"\r
 359         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 360         "                                                                               \n"\r
 361         "       stmdb sp!, {r3, r14}                            \n"\r
 362         "       mov r0, %0                                                      \n"\r
 363         "       msr basepri, r0                                         \n"\r
 364         "       bl vTaskSwitchContext                           \n"\r
 365         "       mov r0, #0                                                      \n"\r
 366         "       msr basepri, r0                                         \n"\r
 367         "       ldmia sp!, {r3, r14}                            \n"\r
 368         "                                                                               \n"\r
 369         "       ldr r1, [r3]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 370         "       ldr r0, [r1]                                            \n"\r
 371         "                                                                               \n"\r
 372         "       ldmia r0!, {r4-r11, r14}                        \n" /* Pop the core registers. */\r
 373         "                                                                               \n"\r
 374         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 375         "       it eq                                                           \n"\r
 376         "       vldmiaeq r0!, {s16-s31}                         \n"\r
 377         "                                                                               \n"\r
 378         "       msr psp, r0                                                     \n"\r
 379         "       bx r14                                                          \n"\r
 380         "                                                                               \n"\r
 381         "       .align 2                                                        \n"\r
 382         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 383         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 384         );\r
 385 }\r
 386 /*-----------------------------------------------------------*/\r
 387 \r
 388 void xPortSysTickHandler( void )\r
 389 {\r
 390         /* If using preemption, also force a context switch. */\r
 391         #if configUSE_PREEMPTION == 1\r
 392                 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 393         #endif\r
 394 \r
 395         /* Only reset the systick load register if configUSE_TICKLESS_IDLE is set to\r
 396         1.  If it is set to 0 tickless idle is not being used.  If it is set to a\r
 397         value other than 0 or 1 then a timer other than the SysTick is being used\r
 398         to generate the tick interrupt. */\r
 399         #if configUSE_TICKLESS_IDLE == 1\r
 400                 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
 401         #endif\r
 402 \r
 403         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 404         {\r
 405                 vTaskIncrementTick();\r
 406         }\r
 407         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 408 }\r
 409 /*-----------------------------------------------------------*/\r
 410 \r
 411 #if configUSE_TICKLESS_IDLE == 1\r
 412 \r
 413         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 414         {\r
 415         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;\r
 416         portTickType xModifiableIdleTime;\r
 417 \r
 418                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 419                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 420                 {\r
 421                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 422                 }\r
 423 \r
 424                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 425                 tick periods.  -1 is used because this code will execute part way\r
 426                 through one of the tick periods, and the fraction of a tick period is\r
 427                 accounted for later. */\r
 428                 ulReloadValue = ( ulTimerReloadValueForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 429                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 430                 {\r
 431                         ulReloadValue -= ulStoppedTimerCompensation;\r
 432                 }\r
 433 \r
 434                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 435                 is accounted for as best it can be, but using the tickless mode will\r
 436                 inevitably result in some tiny drift of the time maintained by the\r
 437                 kernel with respect to calendar time. */\r
 438                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 439 \r
 440                 /* Adjust the reload value to take into account that the current time\r
 441                 slice is already partially complete. */\r
 442                 ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
 443 \r
 444                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 445                 method as that will mask interrupts that should exit sleep mode. */\r
 446                 __asm volatile( "cpsid i" );\r
 447 \r
 448                 /* If a context switch is pending or a task is waiting for the scheduler\r
 449                 to be unsuspended then abandon the low power entry. */\r
 450                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 451                 {\r
 452                         /* Restart SysTick. */\r
 453                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 454 \r
 455                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 456                         above. */\r
 457                         __asm volatile( "cpsie i" );\r
 458                 }\r
 459                 else\r
 460                 {\r
 461                         /* Set the new reload value. */\r
 462                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 463 \r
 464                         /* Clear the SysTick count flag and set the count value back to\r
 465                         zero. */\r
 466                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 467 \r
 468                         /* Restart SysTick. */\r
 469                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 470 \r
 471                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 472                         set its parameter to 0 to indicate that its implementation contains\r
 473                         its own wait for interrupt or wait for event instruction, and so wfi\r
 474                         should not be executed again.  However, the original expected idle\r
 475                         time variable must remain unmodified, so a copy is taken. */\r
 476                         xModifiableIdleTime = xExpectedIdleTime;\r
 477                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 478                         if( xModifiableIdleTime > 0 )\r
 479                         {\r
 480                                 __asm volatile( "wfi" );\r
 481                                 __asm volatile( "dsb" );\r
 482                                 __asm volatile( "isb" );\r
 483                         }\r
 484                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 485 \r
 486                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 487                         accounted for as best it can be, but using the tickless mode will\r
 488                         inevitably result in some tiny drift of the time maintained by the\r
 489                         kernel with respect to calendar time. */\r
 490                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 491 \r
 492                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 493                         above. */\r
 494                         __asm volatile( "cpsie i" );\r
 495 \r
 496                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 497                         {\r
 498                                 /* The tick interrupt has already executed, and the SysTick\r
 499                                 count reloaded with the portNVIC_SYSTICK_LOAD_REG value.\r
 500                                 Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of\r
 501                                 this tick period. */\r
 502                                 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 503 \r
 504                                 /* The tick interrupt handler will already have pended the tick\r
 505                                 processing in the kernel.  As the pending tick will be\r
 506                                 processed as soon as this function exits, the tick value\r
 507                                 maintained by the tick is stepped forward by one less than the\r
 508                                 time spent waiting. */\r
 509                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 510                         }\r
 511                         else\r
 512                         {\r
 513                                 /* Something other than the tick interrupt ended the sleep.\r
 514                                 Work out how long the sleep lasted. */\r
 515                                 ulCompletedSysTickIncrements = ( xExpectedIdleTime * ulTimerReloadValueForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 516 \r
 517                                 /* How many complete tick periods passed while the processor\r
 518                                 was waiting? */\r
 519                                 ulCompleteTickPeriods = ulCompletedSysTickIncrements / ulTimerReloadValueForOneTick;\r
 520 \r
 521                                 /* The reload value is set to whatever fraction of a single tick\r
 522                                 period remains. */\r
 523                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerReloadValueForOneTick ) - ulCompletedSysTickIncrements;\r
 524                         }\r
 525 \r
 526                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 527                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 528                         value. */\r
 529                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 530                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 531 \r
 532                         vTaskStepTick( ulCompleteTickPeriods );\r
 533                 }\r
 534         }\r
 535 \r
 536 #endif /* #if configUSE_TICKLESS_IDLE */\r
 537 /*-----------------------------------------------------------*/\r
 538 \r
 539 /*\r
 540  * Setup the systick timer to generate the tick interrupts at the required\r
 541  * frequency.\r
 542  */\r
 543 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 544 {\r
 545         /* Calculate the constants required to configure the tick interrupt. */\r
 546         #if configUSE_TICKLESS_IDLE == 1\r
 547         {\r
 548                 ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 549                 xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );\r
 550                 ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 551         }\r
 552         #endif /* configUSE_TICKLESS_IDLE */\r
 553 \r
 554         /* Configure SysTick to interrupt at the requested rate. */\r
 555         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 556         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 557 }\r
 558 /*-----------------------------------------------------------*/\r
 559 \r
 560 /* This is a naked function. */\r
 561 static void vPortEnableVFP( void )\r
 562 {\r
 563         __asm volatile\r
 564         (\r
 565                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 566                 "       ldr r1, [r0]                            \n"\r
 567                 "                                                               \n"\r
 568                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 569                 "       str r1, [r0]                            \n"\r
 570                 "       bx r14                                          "\r
 571         );\r
 572 }\r
 573 \r