git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c

   1 /*\r
   2     FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  28     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  29     >>! the source code for proprietary components outside of the FreeRTOS\r
  30     >>! kernel.\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /*-----------------------------------------------------------\r
  67  * Implementation of functions defined in portable.h for the ARM CM4F port.\r
  68  *----------------------------------------------------------*/\r
  69 \r
  70 /* Scheduler includes. */\r
  71 #include "FreeRTOS.h"\r
  72 #include "task.h"\r
  73 \r
  74 #ifndef __VFP_FP__\r
  75         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  76 #endif\r
  77 \r
  78 #ifndef configSYSTICK_CLOCK_HZ\r
  79         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  80         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  81         #define portNVIC_SYSTICK_CLK_BIT        ( 1UL << 2UL )\r
  82 #else\r
  83         /* The way the SysTick is clocked is not modified in case it is not the same\r
  84         as the core. */\r
  85         #define portNVIC_SYSTICK_CLK_BIT        ( 0 )\r
  86 #endif\r
  87 \r
  88 /* Constants required to manipulate the core.  Registers first... */\r
  89 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  90 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  91 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  92 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  93 /* ...then bits in the registers. */\r
  94 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  95 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  96 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
  97 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
  98 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
  99 \r
 100 #define portNVIC_PENDSV_PRI                                     ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 101 #define portNVIC_SYSTICK_PRI                            ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 102 \r
 103 /* Constants required to check the validity of an interrupt priority. */\r
 104 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 105 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 106 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 107 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 108 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 109 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 110 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 111 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 112 \r
 113 /* Constants required to manipulate the VFP. */\r
 114 #define portFPCCR                                       ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\r
 115 #define portASPEN_AND_LSPEN_BITS        ( 0x3UL << 30UL )\r
 116 \r
 117 /* Constants required to set up the initial stack. */\r
 118 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 119 #define portINITIAL_EXEC_RETURN         ( 0xfffffffd )\r
 120 \r
 121 /* The systick is a 24-bit counter. */\r
 122 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 123 \r
 124 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 125 occurred while the SysTick counter is stopped during tickless idle\r
 126 calculations. */\r
 127 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 128 \r
 129 /* Let the user override the pre-loading of the initial LR with the address of\r
 130 prvTaskExitError() in case is messes up unwinding of the stack in the\r
 131 debugger. */\r
 132 #ifdef configTASK_RETURN_ADDRESS\r
 133         #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
 134 #else\r
 135         #define portTASK_RETURN_ADDRESS prvTaskExitError\r
 136 #endif\r
 137 \r
 138 /* Each task maintains its own interrupt status in the critical nesting\r
 139 variable. */\r
 140 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 141 \r
 142 /*\r
 143  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 144  * file is weak to allow application writers to change the timer used to\r
 145  * generate the tick interrupt.\r
 146  */\r
 147 void vPortSetupTimerInterrupt( void );\r
 148 \r
 149 /*\r
 150  * Exception handlers.\r
 151  */\r
 152 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 153 void xPortSysTickHandler( void );\r
 154 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 155 \r
 156 /*\r
 157  * Start first task is a separate function so it can be tested in isolation.\r
 158  */\r
 159 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 160 \r
 161 /*\r
 162  * Function to enable the VFP.\r
 163  */\r
 164  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 165 \r
 166 /*\r
 167  * Used to catch tasks that attempt to return from their implementing function.\r
 168  */\r
 169 static void prvTaskExitError( void );\r
 170 \r
 171 /*-----------------------------------------------------------*/\r
 172 \r
 173 /*\r
 174  * The number of SysTick increments that make up one tick period.\r
 175  */\r
 176 #if configUSE_TICKLESS_IDLE == 1\r
 177         static uint32_t ulTimerCountsForOneTick = 0;\r
 178 #endif /* configUSE_TICKLESS_IDLE */\r
 179 \r
 180 /*\r
 181  * The maximum number of tick periods that can be suppressed is limited by the\r
 182  * 24 bit resolution of the SysTick timer.\r
 183  */\r
 184 #if configUSE_TICKLESS_IDLE == 1\r
 185         static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
 186 #endif /* configUSE_TICKLESS_IDLE */\r
 187 \r
 188 /*\r
 189  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 190  * power functionality only.\r
 191  */\r
 192 #if configUSE_TICKLESS_IDLE == 1\r
 193         static uint32_t ulStoppedTimerCompensation = 0;\r
 194 #endif /* configUSE_TICKLESS_IDLE */\r
 195 \r
 196 /*\r
 197  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 198  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 199  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 200  */\r
 201 #if ( configASSERT_DEFINED == 1 )\r
 202          static uint8_t ucMaxSysCallPriority = 0;\r
 203          static uint32_t ulMaxPRIGROUPValue = 0;\r
 204          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 205 #endif /* configASSERT_DEFINED */\r
 206 \r
 207 /*-----------------------------------------------------------*/\r
 208 \r
 209 /*\r
 210  * See header file for description.\r
 211  */\r
 212 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 213 {\r
 214         /* Simulate the stack frame as it would be created by a context switch\r
 215         interrupt. */\r
 216 \r
 217         /* Offset added to account for the way the MCU uses the stack on entry/exit\r
 218         of interrupts, and to ensure alignment. */\r
 219         pxTopOfStack--;\r
 220 \r
 221         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 222         pxTopOfStack--;\r
 223         *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
 224         pxTopOfStack--;\r
 225         *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 226 \r
 227         /* Save code space by skipping register initialisation. */\r
 228         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 229         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 230 \r
 231         /* A save method is being used that requires each task to maintain its\r
 232         own exec return value. */\r
 233         pxTopOfStack--;\r
 234         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 235 \r
 236         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 237 \r
 238         return pxTopOfStack;\r
 239 }\r
 240 /*-----------------------------------------------------------*/\r
 241 \r
 242 static void prvTaskExitError( void )\r
 243 {\r
 244         /* A function that implements a task must not exit or attempt to return to\r
 245         its caller as there is nothing to return to.  If a task wants to exit it\r
 246         should instead call vTaskDelete( NULL ).\r
 247 \r
 248         Artificially force an assert() to be triggered if configASSERT() is\r
 249         defined, then stop here so application writers can catch the error. */\r
 250         configASSERT( uxCriticalNesting == ~0UL );\r
 251         portDISABLE_INTERRUPTS();\r
 252         for( ;; );\r
 253 }\r
 254 /*-----------------------------------------------------------*/\r
 255 \r
 256 void vPortSVCHandler( void )\r
 257 {\r
 258         __asm volatile (\r
 259                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 260                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 261                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 262                                         "       ldmia r0!, {r4-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 263                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 264                                         "       isb                                                             \n"\r
 265                                         "       mov r0, #0                                              \n"\r
 266                                         "       msr     basepri, r0                                     \n"\r
 267                                         "       bx r14                                                  \n"\r
 268                                         "                                                                       \n"\r
 269                                         "       .align 2                                                \n"\r
 270                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 271                                 );\r
 272 }\r
 273 /*-----------------------------------------------------------*/\r
 274 \r
 275 static void prvPortStartFirstTask( void )\r
 276 {\r
 277         __asm volatile(\r
 278                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 279                                         " ldr r0, [r0]                  \n"\r
 280                                         " ldr r0, [r0]                  \n"\r
 281                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 282                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 283                                         " dsb                                   \n"\r
 284                                         " isb                                   \n"\r
 285                                         " svc 0                                 \n" /* System call to start first task. */\r
 286                                         " nop                                   \n"\r
 287                                 );\r
 288 }\r
 289 /*-----------------------------------------------------------*/\r
 290 \r
 291 /*\r
 292  * See header file for description.\r
 293  */\r
 294 BaseType_t xPortStartScheduler( void )\r
 295 {\r
 296         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 297         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 298         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 299 \r
 300         #if( configASSERT_DEFINED == 1 )\r
 301         {\r
 302                 volatile uint32_t ulOriginalPriority;\r
 303                 volatile int8_t * const pcFirstUserPriorityRegister = ( volatile int8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 304                 volatile uint8_t ucMaxPriorityValue;\r
 305 \r
 306                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 307                 functions can be called.  ISR safe functions are those that end in\r
 308                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 309                 ensure interrupt entry is as fast and simple as possible.\r
 310 \r
 311                 Save the interrupt priority value that is about to be clobbered. */\r
 312                 ulOriginalPriority = *pcFirstUserPriorityRegister;\r
 313 \r
 314                 /* Determine the number of priority bits available.  First write to all\r
 315                 possible bits. */\r
 316                 *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 317 \r
 318                 /* Read the value back to see how many bits stuck. */\r
 319                 ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
 320 \r
 321                 /* Use the same mask on the maximum system call priority. */\r
 322                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 323 \r
 324                 /* Calculate the maximum acceptable priority group value for the number\r
 325                 of bits read back. */\r
 326                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 327                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 328                 {\r
 329                         ulMaxPRIGROUPValue--;\r
 330                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 331                 }\r
 332 \r
 333                 /* Shift the priority group value back to its position within the AIRCR\r
 334                 register. */\r
 335                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 336                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 337 \r
 338                 /* Restore the clobbered interrupt priority register to its original\r
 339                 value. */\r
 340                 *pcFirstUserPriorityRegister = ulOriginalPriority;\r
 341         }\r
 342         #endif /* conifgASSERT_DEFINED */\r
 343 \r
 344         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 345         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 346         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 347 \r
 348         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 349         here already. */\r
 350         vPortSetupTimerInterrupt();\r
 351 \r
 352         /* Initialise the critical nesting count ready for the first task. */\r
 353         uxCriticalNesting = 0;\r
 354 \r
 355         /* Ensure the VFP is enabled - it should be anyway. */\r
 356         vPortEnableVFP();\r
 357 \r
 358         /* Lazy save always. */\r
 359         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 360 \r
 361         /* Start the first task. */\r
 362         prvPortStartFirstTask();\r
 363 \r
 364         /* Should never get here as the tasks will now be executing!  Call the task\r
 365         exit error function to prevent compiler warnings about a static function\r
 366         not being called in the case that the application writer overrides this\r
 367         functionality by defining configTASK_RETURN_ADDRESS. */\r
 368         prvTaskExitError();\r
 369 \r
 370         /* Should not get here! */\r
 371         return 0;\r
 372 }\r
 373 /*-----------------------------------------------------------*/\r
 374 \r
 375 void vPortEndScheduler( void )\r
 376 {\r
 377         /* Not implemented in ports where there is nothing to return to.\r
 378         Artificially force an assert. */\r
 379         configASSERT( uxCriticalNesting == 1000UL );\r
 380 }\r
 381 /*-----------------------------------------------------------*/\r
 382 \r
 383 void vPortYield( void )\r
 384 {\r
 385         /* Set a PendSV to request a context switch. */\r
 386         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 387 \r
 388         /* Barriers are normally not required but do ensure the code is completely\r
 389         within the specified behaviour for the architecture. */\r
 390         __asm volatile( "dsb" );\r
 391         __asm volatile( "isb" );\r
 392 }\r
 393 /*-----------------------------------------------------------*/\r
 394 \r
 395 void vPortEnterCritical( void )\r
 396 {\r
 397         portDISABLE_INTERRUPTS();\r
 398         uxCriticalNesting++;\r
 399         __asm volatile( "dsb" );\r
 400         __asm volatile( "isb" );\r
 401 }\r
 402 /*-----------------------------------------------------------*/\r
 403 \r
 404 void vPortExitCritical( void )\r
 405 {\r
 406         configASSERT( uxCriticalNesting );\r
 407         uxCriticalNesting--;\r
 408         if( uxCriticalNesting == 0 )\r
 409         {\r
 410                 portENABLE_INTERRUPTS();\r
 411         }\r
 412 }\r
 413 /*-----------------------------------------------------------*/\r
 414 \r
 415 __attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )\r
 416 {\r
 417         __asm volatile                                                                                                          \\r
 418         (                                                                                                                                       \\r
 419                 "       mrs r0, basepri                                                                                 \n" \\r
 420                 "       mov r1, %0                                                                                              \n"     \\r
 421                 "       msr basepri, r1                                                                                 \n" \\r
 422                 "       bx lr                                                                                                   \n" \\r
 423                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 424         );\r
 425 \r
 426         /* This return will not be reached but is necessary to prevent compiler\r
 427         warnings. */\r
 428         return 0;\r
 429 }\r
 430 /*-----------------------------------------------------------*/\r
 431 \r
 432 __attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
 433 {\r
 434         __asm volatile                                                                                                  \\r
 435         (                                                                                                                               \\r
 436                 "       msr basepri, r0                                                                         \n"     \\r
 437                 "       bx lr                                                                                           \n" \\r
 438                 :::"r0"                                                                                                         \\r
 439         );\r
 440 \r
 441         /* Just to avoid compiler warnings. */\r
 442         ( void ) ulNewMaskValue;\r
 443 }\r
 444 /*-----------------------------------------------------------*/\r
 445 \r
 446 void xPortPendSVHandler( void )\r
 447 {\r
 448         /* This is a naked function. */\r
 449 \r
 450         __asm volatile\r
 451         (\r
 452         "       mrs r0, psp                                                     \n"\r
 453         "       isb                                                                     \n"\r
 454         "                                                                               \n"\r
 455         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 456         "       ldr     r2, [r3]                                                \n"\r
 457         "                                                                               \n"\r
 458         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 459         "       it eq                                                           \n"\r
 460         "       vstmdbeq r0!, {s16-s31}                         \n"\r
 461         "                                                                               \n"\r
 462         "       stmdb r0!, {r4-r11, r14}                        \n" /* Save the core registers. */\r
 463         "                                                                               \n"\r
 464         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 465         "                                                                               \n"\r
 466         "       stmdb sp!, {r3}                                         \n"\r
 467         "       mov r0, %0                                                      \n"\r
 468         "       msr basepri, r0                                         \n"\r
 469         "       bl vTaskSwitchContext                           \n"\r
 470         "       mov r0, #0                                                      \n"\r
 471         "       msr basepri, r0                                         \n"\r
 472         "       ldmia sp!, {r3}                                         \n"\r
 473         "                                                                               \n"\r
 474         "       ldr r1, [r3]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 475         "       ldr r0, [r1]                                            \n"\r
 476         "                                                                               \n"\r
 477         "       ldmia r0!, {r4-r11, r14}                        \n" /* Pop the core registers. */\r
 478         "                                                                               \n"\r
 479         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 480         "       it eq                                                           \n"\r
 481         "       vldmiaeq r0!, {s16-s31}                         \n"\r
 482         "                                                                               \n"\r
 483         "       msr psp, r0                                                     \n"\r
 484         "       isb                                                                     \n"\r
 485         "                                                                               \n"\r
 486         #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\r
 487                 #if WORKAROUND_PMU_CM001 == 1\r
 488         "                       push { r14 }                            \n"\r
 489         "                       pop { pc }                                      \n"\r
 490                 #endif\r
 491         #endif\r
 492         "                                                                               \n"\r
 493         "       bx r14                                                          \n"\r
 494         "                                                                               \n"\r
 495         "       .align 2                                                        \n"\r
 496         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 497         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 498         );\r
 499 }\r
 500 /*-----------------------------------------------------------*/\r
 501 \r
 502 void xPortSysTickHandler( void )\r
 503 {\r
 504         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 505         executes all interrupts must be unmasked.  There is therefore no need to\r
 506         save and then restore the interrupt mask value as its value is already\r
 507         known. */\r
 508         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 509         {\r
 510                 /* Increment the RTOS tick. */\r
 511                 if( xTaskIncrementTick() != pdFALSE )\r
 512                 {\r
 513                         /* A context switch is required.  Context switching is performed in\r
 514                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 515                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 516                 }\r
 517         }\r
 518         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 519 }\r
 520 /*-----------------------------------------------------------*/\r
 521 \r
 522 #if configUSE_TICKLESS_IDLE == 1\r
 523 \r
 524         __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
 525         {\r
 526         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
 527         TickType_t xModifiableIdleTime;\r
 528 \r
 529                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 530                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 531                 {\r
 532                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 533                 }\r
 534 \r
 535                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 536                 is accounted for as best it can be, but using the tickless mode will\r
 537                 inevitably result in some tiny drift of the time maintained by the\r
 538                 kernel with respect to calendar time. */\r
 539                 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
 540 \r
 541                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 542                 tick periods.  -1 is used because this code will execute part way\r
 543                 through one of the tick periods. */\r
 544                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 545                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 546                 {\r
 547                         ulReloadValue -= ulStoppedTimerCompensation;\r
 548                 }\r
 549 \r
 550                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 551                 method as that will mask interrupts that should exit sleep mode. */\r
 552                 __asm volatile( "cpsid i" );\r
 553 \r
 554                 /* If a context switch is pending or a task is waiting for the scheduler\r
 555                 to be unsuspended then abandon the low power entry. */\r
 556                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 557                 {\r
 558                         /* Restart from whatever is left in the count register to complete\r
 559                         this tick period. */\r
 560                         portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 561 \r
 562                         /* Restart SysTick. */\r
 563                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 564 \r
 565                         /* Reset the reload register to the value required for normal tick\r
 566                         periods. */\r
 567                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 568 \r
 569                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 570                         above. */\r
 571                         __asm volatile( "cpsie i" );\r
 572                 }\r
 573                 else\r
 574                 {\r
 575                         /* Set the new reload value. */\r
 576                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 577 \r
 578                         /* Clear the SysTick count flag and set the count value back to\r
 579                         zero. */\r
 580                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 581 \r
 582                         /* Restart SysTick. */\r
 583                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 584 \r
 585                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 586                         set its parameter to 0 to indicate that its implementation contains\r
 587                         its own wait for interrupt or wait for event instruction, and so wfi\r
 588                         should not be executed again.  However, the original expected idle\r
 589                         time variable must remain unmodified, so a copy is taken. */\r
 590                         xModifiableIdleTime = xExpectedIdleTime;\r
 591                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 592                         if( xModifiableIdleTime > 0 )\r
 593                         {\r
 594                                 __asm volatile( "dsb" );\r
 595                                 __asm volatile( "wfi" );\r
 596                                 __asm volatile( "isb" );\r
 597                         }\r
 598                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 599 \r
 600                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 601                         accounted for as best it can be, but using the tickless mode will\r
 602                         inevitably result in some tiny drift of the time maintained by the\r
 603                         kernel with respect to calendar time. */\r
 604                         ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
 605                         portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
 606 \r
 607                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 608                         above. */\r
 609                         __asm volatile( "cpsie i" );\r
 610 \r
 611                         if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 612                         {\r
 613                                 uint32_t ulCalculatedLoadValue;\r
 614 \r
 615                                 /* The tick interrupt has already executed, and the SysTick\r
 616                                 count reloaded with ulReloadValue.  Reset the\r
 617                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 618                                 period. */\r
 619                                 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 620 \r
 621                                 /* Don't allow a tiny value, or values that have somehow\r
 622                                 underflowed because the post sleep hook did something\r
 623                                 that took too long. */\r
 624                                 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
 625                                 {\r
 626                                         ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
 627                                 }\r
 628 \r
 629                                 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
 630 \r
 631                                 /* The tick interrupt handler will already have pended the tick\r
 632                                 processing in the kernel.  As the pending tick will be\r
 633                                 processed as soon as this function exits, the tick value\r
 634                                 maintained by the tick is stepped forward by one less than the\r
 635                                 time spent waiting. */\r
 636                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 637                         }\r
 638                         else\r
 639                         {\r
 640                                 /* Something other than the tick interrupt ended the sleep.\r
 641                                 Work out how long the sleep lasted rounded to complete tick\r
 642                                 periods (not the ulReload value which accounted for part\r
 643                                 ticks). */\r
 644                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 645 \r
 646                                 /* How many complete tick periods passed while the processor\r
 647                                 was waiting? */\r
 648                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 649 \r
 650                                 /* The reload value is set to whatever fraction of a single tick\r
 651                                 period remains. */\r
 652                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 653                         }\r
 654 \r
 655                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 656                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 657                         value.  The critical section is used to ensure the tick interrupt\r
 658                         can only execute once in the case that the reload register is near\r
 659                         zero. */\r
 660                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 661                         portENTER_CRITICAL();\r
 662                         {\r
 663                                 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 664                                 vTaskStepTick( ulCompleteTickPeriods );\r
 665                                 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 666                         }\r
 667                         portEXIT_CRITICAL();\r
 668                 }\r
 669         }\r
 670 \r
 671 #endif /* #if configUSE_TICKLESS_IDLE */\r
 672 /*-----------------------------------------------------------*/\r
 673 \r
 674 /*\r
 675  * Setup the systick timer to generate the tick interrupts at the required\r
 676  * frequency.\r
 677  */\r
 678 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 679 {\r
 680         /* Calculate the constants required to configure the tick interrupt. */\r
 681         #if configUSE_TICKLESS_IDLE == 1\r
 682         {\r
 683                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 684                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 685                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 686         }\r
 687         #endif /* configUSE_TICKLESS_IDLE */\r
 688 \r
 689         /* Configure SysTick to interrupt at the requested rate. */\r
 690         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 691         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
 692 }\r
 693 /*-----------------------------------------------------------*/\r
 694 \r
 695 /* This is a naked function. */\r
 696 static void vPortEnableVFP( void )\r
 697 {\r
 698         __asm volatile\r
 699         (\r
 700                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 701                 "       ldr r1, [r0]                            \n"\r
 702                 "                                                               \n"\r
 703                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 704                 "       str r1, [r0]                            \n"\r
 705                 "       bx r14                                          "\r
 706         );\r
 707 }\r
 708 /*-----------------------------------------------------------*/\r
 709 \r
 710 #if( configASSERT_DEFINED == 1 )\r
 711 \r
 712         void vPortValidateInterruptPriority( void )\r
 713         {\r
 714         uint32_t ulCurrentInterrupt;\r
 715         uint8_t ucCurrentPriority;\r
 716 \r
 717                 /* Obtain the number of the currently executing interrupt. */\r
 718                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 719 \r
 720                 /* Is the interrupt number a user defined interrupt? */\r
 721                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 722                 {\r
 723                         /* Look up the interrupt's priority. */\r
 724                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 725 \r
 726                         /* The following assertion will fail if a service routine (ISR) for\r
 727                         an interrupt that has been assigned a priority above\r
 728                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 729                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 730                         from interrupts that have been assigned a priority at or below\r
 731                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 732 \r
 733                         Numerically low interrupt priority numbers represent logically high\r
 734                         interrupt priorities, therefore the priority of the interrupt must\r
 735                         be set to a value equal to or numerically *higher* than\r
 736                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 737 \r
 738                         Interrupts that use the FreeRTOS API must not be left at their\r
 739                         default priority of     zero as that is the highest possible priority,\r
 740                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 741                         and     therefore also guaranteed to be invalid.\r
 742 \r
 743                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 744                         interrupt entry is as fast and simple as possible.\r
 745 \r
 746                         The following links provide detailed information:\r
 747                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 748                         http://www.freertos.org/FAQHelp.html */\r
 749                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 750                 }\r
 751 \r
 752                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 753                 that define each interrupt's priority to be split between bits that\r
 754                 define the interrupt's pre-emption priority bits and bits that define\r
 755                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 756                 to be pre-emption priority bits.  The following assertion will fail if\r
 757                 this is not the case (if some bits represent a sub-priority).\r
 758 \r
 759                 If the application only uses CMSIS libraries for interrupt\r
 760                 configuration then the correct setting can be achieved on all Cortex-M\r
 761                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 762                 scheduler.  Note however that some vendor specific peripheral libraries\r
 763                 assume a non-zero priority group setting, in which cases using a value\r
 764                 of zero will result in unpredicable behaviour. */\r
 765                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 766         }\r
 767 \r
 768 #endif /* configASSERT_DEFINED */\r
 769 \r
 770 \r