git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c

   1 /*\r
   2     FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
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   6 \r
   7     ***************************************************************************\r
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  23      *                                                                       *\r
  24     ***************************************************************************\r
  25 \r
  26 \r
  27     This file is part of the FreeRTOS distribution.\r
  28 \r
  29     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  30     the terms of the GNU General Public License (version 2) as published by the\r
  31     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  32 \r
  33     >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
  34     distribute a combined work that includes FreeRTOS without being obliged to\r
  35     provide the source code for proprietary components outside of the FreeRTOS\r
  36     kernel.\r
  37 \r
  38     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  39     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  40     FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
  41     details. You should have received a copy of the GNU General Public License\r
  42     and the FreeRTOS license exception along with FreeRTOS; if not it can be\r
  43     viewed here: http://www.freertos.org/a00114.html and also obtained by\r
  44     writing to Real Time Engineers Ltd., contact details for whom are available\r
  45     on the FreeRTOS WEB site.\r
  46 \r
  47     1 tab == 4 spaces!\r
  48 \r
  49     ***************************************************************************\r
  50      *                                                                       *\r
  51      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  52      *    not run, what could be wrong?"                                     *\r
  53      *                                                                       *\r
  54      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  55      *                                                                       *\r
  56     ***************************************************************************\r
  57 \r
  58 \r
  59     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  60     license and Real Time Engineers Ltd. contact details.\r
  61 \r
  62     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  63     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
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  65 \r
  66     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  67     Integrity Systems, who sell the code with commercial support,\r
  68     indemnification and middleware, under the OpenRTOS brand.\r
  69 \r
  70     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  71     engineered and independently SIL3 certified version for use in safety and\r
  72     mission critical applications that require provable dependability.\r
  73 */\r
  74 \r
  75 /*-----------------------------------------------------------\r
  76  * Implementation of functions defined in portable.h for the ARM CM4F port.\r
  77  *----------------------------------------------------------*/\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "task.h"\r
  82 \r
  83 #ifndef __VFP_FP__\r
  84         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  85 #endif\r
  86 \r
  87 #ifndef configSYSTICK_CLOCK_HZ\r
  88         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  89 #endif\r
  90 \r
  91 /* Constants required to manipulate the core.  Registers first... */\r
  92 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  93 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  95 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  96 /* ...then bits in the registers. */\r
  97 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
  98 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  99 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
 100 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 101 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 102 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 103 \r
 104 #define portNVIC_PENDSV_PRI                                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 105 #define portNVIC_SYSTICK_PRI                            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 106 \r
 107 /* Constants required to manipulate the VFP. */\r
 108 #define portFPCCR                                       ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
 109 #define portASPEN_AND_LSPEN_BITS        ( 0x3UL << 30UL )\r
 110 \r
 111 /* Constants required to set up the initial stack. */\r
 112 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 113 #define portINITIAL_EXEC_RETURN         ( 0xfffffffd )\r
 114 \r
 115 /* The systick is a 24-bit counter. */\r
 116 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 117 \r
 118 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 119 occurred while the SysTick counter is stopped during tickless idle\r
 120 calculations. */\r
 121 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 122 \r
 123 /* Each task maintains its own interrupt status in the critical nesting\r
 124 variable. */\r
 125 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 126 \r
 127 /*\r
 128  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 129  * file is weak to allow application writers to change the timer used to\r
 130  * generate the tick interrupt.\r
 131  */\r
 132 void vPortSetupTimerInterrupt( void );\r
 133 \r
 134 /*\r
 135  * Exception handlers.\r
 136  */\r
 137 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 138 void xPortSysTickHandler( void );\r
 139 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 140 \r
 141 /*\r
 142  * Start first task is a separate function so it can be tested in isolation.\r
 143  */\r
 144 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 145 \r
 146 /*\r
 147  * Function to enable the VFP.\r
 148  */\r
 149  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 150 \r
 151 /*-----------------------------------------------------------*/\r
 152 \r
 153 /*\r
 154  * The number of SysTick increments that make up one tick period.\r
 155  */\r
 156 #if configUSE_TICKLESS_IDLE == 1\r
 157         static unsigned long ulTimerCountsForOneTick = 0;\r
 158 #endif /* configUSE_TICKLESS_IDLE */\r
 159 \r
 160 /*\r
 161  * The maximum number of tick periods that can be suppressed is limited by the\r
 162  * 24 bit resolution of the SysTick timer.\r
 163  */\r
 164 #if configUSE_TICKLESS_IDLE == 1\r
 165         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 166 #endif /* configUSE_TICKLESS_IDLE */\r
 167 \r
 168 /*\r
 169  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 170  * power functionality only.\r
 171  */\r
 172 #if configUSE_TICKLESS_IDLE == 1\r
 173         static unsigned long ulStoppedTimerCompensation = 0;\r
 174 #endif /* configUSE_TICKLESS_IDLE */\r
 175 \r
 176 /*-----------------------------------------------------------*/\r
 177 \r
 178 /*\r
 179  * See header file for description.\r
 180  */\r
 181 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 182 {\r
 183         /* Simulate the stack frame as it would be created by a context switch\r
 184         interrupt. */\r
 185 \r
 186         /* Offset added to account for the way the MCU uses the stack on entry/exit\r
 187         of interrupts, and to ensure alignment. */\r
 188         pxTopOfStack--;\r
 189 \r
 190         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 191         pxTopOfStack--;\r
 192         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 193         pxTopOfStack--;\r
 194         *pxTopOfStack = 0;      /* LR */\r
 195 \r
 196         /* Save code space by skipping register initialisation. */\r
 197         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 198         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 199 \r
 200         /* A save method is being used that requires each task to maintain its\r
 201         own exec return value. */\r
 202         pxTopOfStack--;\r
 203         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 204 \r
 205         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 206 \r
 207         return pxTopOfStack;\r
 208 }\r
 209 /*-----------------------------------------------------------*/\r
 210 \r
 211 void vPortSVCHandler( void )\r
 212 {\r
 213         __asm volatile (\r
 214                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 215                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 216                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 217                                         "       ldmia r0!, {r4-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 218                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 219                                         "       mov r0, #0                                              \n"\r
 220                                         "       msr     basepri, r0                                     \n"\r
 221                                         "       bx r14                                                  \n"\r
 222                                         "                                                                       \n"\r
 223                                         "       .align 2                                                \n"\r
 224                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 225                                 );\r
 226 }\r
 227 /*-----------------------------------------------------------*/\r
 228 \r
 229 static void prvPortStartFirstTask( void )\r
 230 {\r
 231         __asm volatile(\r
 232                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 233                                         " ldr r0, [r0]                  \n"\r
 234                                         " ldr r0, [r0]                  \n"\r
 235                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 236                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 237                                         " svc 0                                 \n" /* System call to start first task. */\r
 238                                         " nop                                   \n"\r
 239                                 );\r
 240 }\r
 241 /*-----------------------------------------------------------*/\r
 242 \r
 243 /*\r
 244  * See header file for description.\r
 245  */\r
 246 portBASE_TYPE xPortStartScheduler( void )\r
 247 {\r
 248         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 249         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 250         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 251 \r
 252         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 253         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 254         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 255 \r
 256         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 257         here already. */\r
 258         vPortSetupTimerInterrupt();\r
 259 \r
 260         /* Initialise the critical nesting count ready for the first task. */\r
 261         uxCriticalNesting = 0;\r
 262 \r
 263         /* Ensure the VFP is enabled - it should be anyway. */\r
 264         vPortEnableVFP();\r
 265 \r
 266         /* Lazy save always. */\r
 267         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 268 \r
 269         /* Start the first task. */\r
 270         prvPortStartFirstTask();\r
 271 \r
 272         /* Should not get here! */\r
 273         return 0;\r
 274 }\r
 275 /*-----------------------------------------------------------*/\r
 276 \r
 277 void vPortEndScheduler( void )\r
 278 {\r
 279         /* It is unlikely that the CM4F port will require this function as there\r
 280         is nothing to return to.  */\r
 281 }\r
 282 /*-----------------------------------------------------------*/\r
 283 \r
 284 void vPortYield( void )\r
 285 {\r
 286         /* Set a PendSV to request a context switch. */\r
 287         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 288 \r
 289         /* Barriers are normally not required but do ensure the code is completely\r
 290         within the specified behaviour for the architecture. */\r
 291         __asm volatile( "dsb" );\r
 292         __asm volatile( "isb" );\r
 293 }\r
 294 /*-----------------------------------------------------------*/\r
 295 \r
 296 void vPortEnterCritical( void )\r
 297 {\r
 298         portDISABLE_INTERRUPTS();\r
 299         uxCriticalNesting++;\r
 300         __asm volatile( "dsb" );\r
 301         __asm volatile( "isb" );\r
 302 }\r
 303 /*-----------------------------------------------------------*/\r
 304 \r
 305 void vPortExitCritical( void )\r
 306 {\r
 307         uxCriticalNesting--;\r
 308         if( uxCriticalNesting == 0 )\r
 309         {\r
 310                 portENABLE_INTERRUPTS();\r
 311         }\r
 312 }\r
 313 /*-----------------------------------------------------------*/\r
 314 \r
 315 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 316 {\r
 317         __asm volatile                                                                                                          \\r
 318         (                                                                                                                                       \\r
 319                 "       mrs r0, basepri                                                                                 \n" \\r
 320                 "       mov r1, %0                                                                                              \n"     \\r
 321                 "       msr basepri, r1                                                                                 \n" \\r
 322                 "       bx lr                                                                                                   \n" \\r
 323                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 324         );\r
 325 \r
 326         /* This return will not be reached but is necessary to prevent compiler\r
 327         warnings. */\r
 328         return 0;\r
 329 }\r
 330 /*-----------------------------------------------------------*/\r
 331 \r
 332 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 333 {\r
 334         __asm volatile                                                                                                  \\r
 335         (                                                                                                                               \\r
 336                 "       msr basepri, r0                                                                         \n"     \\r
 337                 "       bx lr                                                                                           \n" \\r
 338                 :::"r0"                                                                                                         \\r
 339         );\r
 340 \r
 341         /* Just to avoid compiler warnings. */\r
 342         ( void ) ulNewMaskValue;\r
 343 }\r
 344 /*-----------------------------------------------------------*/\r
 345 \r
 346 void xPortPendSVHandler( void )\r
 347 {\r
 348         /* This is a naked function. */\r
 349 \r
 350         __asm volatile\r
 351         (\r
 352         "       mrs r0, psp                                                     \n"\r
 353         "                                                                               \n"\r
 354         "       ldr     r3, pxCurrentTCBConst                           \n" /* Get the location of the current TCB. */\r
 355         "       ldr     r2, [r3]                                                \n"\r
 356         "                                                                               \n"\r
 357         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 358         "       it eq                                                           \n"\r
 359         "       vstmdbeq r0!, {s16-s31}                         \n"\r
 360         "                                                                               \n"\r
 361         "       stmdb r0!, {r4-r11, r14}                        \n" /* Save the core registers. */\r
 362         "                                                                               \n"\r
 363         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 364         "                                                                               \n"\r
 365         "       stmdb sp!, {r3, r14}                            \n"\r
 366         "       mov r0, %0                                                      \n"\r
 367         "       msr basepri, r0                                         \n"\r
 368         "       bl vTaskSwitchContext                           \n"\r
 369         "       mov r0, #0                                                      \n"\r
 370         "       msr basepri, r0                                         \n"\r
 371         "       ldmia sp!, {r3, r14}                            \n"\r
 372         "                                                                               \n"\r
 373         "       ldr r1, [r3]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 374         "       ldr r0, [r1]                                            \n"\r
 375         "                                                                               \n"\r
 376         "       ldmia r0!, {r4-r11, r14}                        \n" /* Pop the core registers. */\r
 377         "                                                                               \n"\r
 378         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 379         "       it eq                                                           \n"\r
 380         "       vldmiaeq r0!, {s16-s31}                         \n"\r
 381         "                                                                               \n"\r
 382         "       msr psp, r0                                                     \n"\r
 383         "       bx r14                                                          \n"\r
 384         "                                                                               \n"\r
 385         "       .align 2                                                        \n"\r
 386         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 387         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 388         );\r
 389 }\r
 390 /*-----------------------------------------------------------*/\r
 391 \r
 392 void xPortSysTickHandler( void )\r
 393 {\r
 394         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 395         executes all interrupts must be unmasked.  There is therefore no need to\r
 396         save and then restore the interrupt mask value as its value is already\r
 397         known. */\r
 398         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 399         {\r
 400                 /* Increment the RTOS tick. */\r
 401                 if( xTaskIncrementTick() != pdFALSE )\r
 402                 {\r
 403                         /* A context switch is required.  Context switching is performed in\r
 404                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 405                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 406                 }\r
 407         }\r
 408         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 409 }\r
 410 /*-----------------------------------------------------------*/\r
 411 \r
 412 #if configUSE_TICKLESS_IDLE == 1\r
 413 \r
 414         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 415         {\r
 416         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 417         portTickType xModifiableIdleTime;\r
 418 \r
 419                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 420                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 421                 {\r
 422                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 423                 }\r
 424 \r
 425                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 426                 is accounted for as best it can be, but using the tickless mode will\r
 427                 inevitably result in some tiny drift of the time maintained by the\r
 428                 kernel with respect to calendar time. */\r
 429                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 430 \r
 431                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 432                 tick periods.  -1 is used because this code will execute part way\r
 433                 through one of the tick periods. */\r
 434                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 435                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 436                 {\r
 437                         ulReloadValue -= ulStoppedTimerCompensation;\r
 438                 }\r
 439 \r
 440                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 441                 method as that will mask interrupts that should exit sleep mode. */\r
 442                 __asm volatile( "cpsid i" );\r
 443 \r
 444                 /* If a context switch is pending or a task is waiting for the scheduler\r
 445                 to be unsuspended then abandon the low power entry. */\r
 446                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 447                 {\r
 448                         /* Restart SysTick. */\r
 449                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 450 \r
 451                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 452                         above. */\r
 453                         __asm volatile( "cpsie i" );\r
 454                 }\r
 455                 else\r
 456                 {\r
 457                         /* Set the new reload value. */\r
 458                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 459 \r
 460                         /* Clear the SysTick count flag and set the count value back to\r
 461                         zero. */\r
 462                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 463 \r
 464                         /* Restart SysTick. */\r
 465                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 466 \r
 467                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 468                         set its parameter to 0 to indicate that its implementation contains\r
 469                         its own wait for interrupt or wait for event instruction, and so wfi\r
 470                         should not be executed again.  However, the original expected idle\r
 471                         time variable must remain unmodified, so a copy is taken. */\r
 472                         xModifiableIdleTime = xExpectedIdleTime;\r
 473                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 474                         if( xModifiableIdleTime > 0 )\r
 475                         {\r
 476                                 __asm volatile( "dsb" );\r
 477                                 __asm volatile( "wfi" );\r
 478                                 __asm volatile( "isb" );\r
 479                         }\r
 480                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 481 \r
 482                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 483                         accounted for as best it can be, but using the tickless mode will\r
 484                         inevitably result in some tiny drift of the time maintained by the\r
 485                         kernel with respect to calendar time. */\r
 486                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 487 \r
 488                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 489                         above. */\r
 490                         __asm volatile( "cpsie i" );\r
 491 \r
 492                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 493                         {\r
 494                                 /* The tick interrupt has already executed, and the SysTick\r
 495                                 count reloaded with ulReloadValue.  Reset the\r
 496                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 497                                 period. */\r
 498                                 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 499 \r
 500                                 /* The tick interrupt handler will already have pended the tick\r
 501                                 processing in the kernel.  As the pending tick will be\r
 502                                 processed as soon as this function exits, the tick value\r
 503                                 maintained by the tick is stepped forward by one less than the\r
 504                                 time spent waiting. */\r
 505                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 506                         }\r
 507                         else\r
 508                         {\r
 509                                 /* Something other than the tick interrupt ended the sleep.\r
 510                                 Work out how long the sleep lasted rounded to complete tick\r
 511                                 periods (not the ulReload value which accounted for part\r
 512                                 ticks). */\r
 513                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 514 \r
 515                                 /* How many complete tick periods passed while the processor\r
 516                                 was waiting? */\r
 517                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 518 \r
 519                                 /* The reload value is set to whatever fraction of a single tick\r
 520                                 period remains. */\r
 521                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 522                         }\r
 523 \r
 524                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 525                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 526                         value. */\r
 527                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 528                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 529 \r
 530                         vTaskStepTick( ulCompleteTickPeriods );\r
 531 \r
 532                         /* The counter must start by the time the reload value is reset. */\r
 533                         configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 534                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 535                 }\r
 536         }\r
 537 \r
 538 #endif /* #if configUSE_TICKLESS_IDLE */\r
 539 /*-----------------------------------------------------------*/\r
 540 \r
 541 /*\r
 542  * Setup the systick timer to generate the tick interrupts at the required\r
 543  * frequency.\r
 544  */\r
 545 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 546 {\r
 547         /* Calculate the constants required to configure the tick interrupt. */\r
 548         #if configUSE_TICKLESS_IDLE == 1\r
 549         {\r
 550                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 551                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 552                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 553         }\r
 554         #endif /* configUSE_TICKLESS_IDLE */\r
 555 \r
 556         /* Configure SysTick to interrupt at the requested rate. */\r
 557         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 558         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 559 }\r
 560 /*-----------------------------------------------------------*/\r
 561 \r
 562 /* This is a naked function. */\r
 563 static void vPortEnableVFP( void )\r
 564 {\r
 565         __asm volatile\r
 566         (\r
 567                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 568                 "       ldr r1, [r0]                            \n"\r
 569                 "                                                               \n"\r
 570                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 571                 "       str r1, [r0]                            \n"\r
 572                 "       bx r14                                          "\r
 573         );\r
 574 }\r
 575 \r