git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c

   1 /*\r
   2     FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
   3 \r
   4 \r
   5     ***************************************************************************\r
   6      *                                                                       *\r
   7      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
   8      *    Complete, revised, and edited pdf reference manuals are also       *\r
   9      *    available.                                                         *\r
  10      *                                                                       *\r
  11      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
  12      *    ensuring you get running as quickly as possible and with an        *\r
  13      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
  14      *    the FreeRTOS project to continue with its mission of providing     *\r
  15      *    professional grade, cross platform, de facto standard solutions    *\r
  16      *    for microcontrollers - completely free of charge!                  *\r
  17      *                                                                       *\r
  18      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
  19      *                                                                       *\r
  20      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
  21      *                                                                       *\r
  22     ***************************************************************************\r
  23 \r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  30     >>>NOTE<<< The modification to the GPL is included to allow you to\r
  31     distribute a combined work that includes FreeRTOS without being obliged to\r
  32     provide the source code for proprietary components outside of the FreeRTOS\r
  33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public\r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
  42     1 tab == 4 spaces!\r
  43     \r
  44     ***************************************************************************\r
  45      *                                                                       *\r
  46      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  47      *    not run, what could be wrong?                                      *\r
  48      *                                                                       *\r
  49      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  50      *                                                                       *\r
  51     ***************************************************************************\r
  52 \r
  53     \r
  54     http://www.FreeRTOS.org - Documentation, training, latest information, \r
  55     license and contact details.\r
  56     \r
  57     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  58     including FreeRTOS+Trace - an indispensable productivity tool.\r
  59 \r
  60     Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
  61     the code with commercial support, indemnification, and middleware, under \r
  62     the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also\r
  63     provide a safety engineered and independently SIL3 certified version under \r
  64     the SafeRTOS brand: http://www.SafeRTOS.com.\r
  65 */\r
  66 \r
  67 /*-----------------------------------------------------------\r
  68  * Implementation of functions defined in portable.h for the ARM CM4F port.\r
  69  *----------------------------------------------------------*/\r
  70 \r
  71 /* Scheduler includes. */\r
  72 #include "FreeRTOS.h"\r
  73 #include "task.h"\r
  74 \r
  75 #ifndef __VFP_FP__\r
  76         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  77 #endif\r
  78 \r
  79 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\r
  80         #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\r
  81 #endif\r
  82 \r
  83 /* Constants required to manipulate the NVIC. */\r
  84 #define portNVIC_SYSTICK_CTRL           ( ( volatile unsigned long * ) 0xe000e010 )\r
  85 #define portNVIC_SYSTICK_LOAD           ( ( volatile unsigned long * ) 0xe000e014 )\r
  86 #define portNVIC_INT_CTRL                       ( ( volatile unsigned long * ) 0xe000ed04 )\r
  87 #define portNVIC_SYSPRI2                        ( ( volatile unsigned long * ) 0xe000ed20 )\r
  88 #define portNVIC_SYSTICK_CLK            0x00000004\r
  89 #define portNVIC_SYSTICK_INT            0x00000002\r
  90 #define portNVIC_SYSTICK_ENABLE         0x00000001\r
  91 #define portNVIC_PENDSVSET                      0x10000000\r
  92 #define portNVIC_PENDSV_PRI                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
  93 #define portNVIC_SYSTICK_PRI            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
  94 \r
  95 /* Constants required to manipulate the VFP. */\r
  96 #define portFPCCR                                       ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */\r
  97 #define portASPEN_AND_LSPEN_BITS        ( 0x3UL << 30UL )\r
  98 \r
  99 /* Constants required to set up the initial stack. */\r
 100 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 101 #define portINITIAL_EXEC_RETURN         ( 0xfffffffd )\r
 102 \r
 103 /* The priority used by the kernel is assigned to a variable to make access\r
 104 from inline assembler easier. */\r
 105 const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
 106 \r
 107 /* Each task maintains its own interrupt status in the critical nesting\r
 108 variable. */\r
 109 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 110 \r
 111 /*\r
 112  * Setup the timer to generate the tick interrupts.\r
 113  */\r
 114 static void prvSetupTimerInterrupt( void );\r
 115 \r
 116 /*\r
 117  * Exception handlers.\r
 118  */\r
 119 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 120 void xPortSysTickHandler( void );\r
 121 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 122 \r
 123 /*\r
 124  * Start first task is a separate function so it can be tested in isolation.\r
 125  */\r
 126 static void vPortStartFirstTask( void ) __attribute__ (( naked ));\r
 127 \r
 128 /*\r
 129  * Function to enable the VFP.\r
 130  */\r
 131  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 132 \r
 133 \r
 134 /*-----------------------------------------------------------*/\r
 135 \r
 136 /*\r
 137  * See header file for description.\r
 138  */\r
 139 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 140 {\r
 141         /* Simulate the stack frame as it would be created by a context switch\r
 142         interrupt. */\r
 143 \r
 144         /* Offset added to account for the way the MCU uses the stack on entry/exit\r
 145         of interrupts, and to ensure alignment. */\r
 146         pxTopOfStack--;\r
 147 \r
 148         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 149         pxTopOfStack--;\r
 150         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 151         pxTopOfStack--;\r
 152         *pxTopOfStack = 0;      /* LR */\r
 153 \r
 154         /* Save code space by skipping register initialisation. */\r
 155         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 156         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 157 \r
 158         /* A save method is being used that requires each task to maintain its\r
 159         own exec return value. */\r
 160         pxTopOfStack--;\r
 161         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 162 \r
 163         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 164 \r
 165         return pxTopOfStack;\r
 166 }\r
 167 /*-----------------------------------------------------------*/\r
 168 \r
 169 void vPortSVCHandler( void )\r
 170 {\r
 171         __asm volatile (\r
 172                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 173                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 174                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 175                                         "       ldmia r0!, {r4-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 176                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 177                                         "       mov r0, #0                                              \n"\r
 178                                         "       msr     basepri, r0                                     \n"\r
 179                                         "       bx r14                                                  \n"\r
 180                                         "                                                                       \n"\r
 181                                         "       .align 2                                                \n"\r
 182                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 183                                 );\r
 184 }\r
 185 /*-----------------------------------------------------------*/\r
 186 \r
 187 static void vPortStartFirstTask( void )\r
 188 {\r
 189         __asm volatile(\r
 190                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 191                                         " ldr r0, [r0]                  \n"\r
 192                                         " ldr r0, [r0]                  \n"\r
 193                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 194                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 195                                         " svc 0                                 \n" /* System call to start first task. */\r
 196                                         " nop                                   \n"\r
 197                                 );\r
 198 }\r
 199 /*-----------------------------------------------------------*/\r
 200 \r
 201 /*\r
 202  * See header file for description.\r
 203  */\r
 204 portBASE_TYPE xPortStartScheduler( void )\r
 205 {\r
 206         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 207         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 208         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 209 \r
 210         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 211         here already. */\r
 212         prvSetupTimerInterrupt();\r
 213 \r
 214         /* Initialise the critical nesting count ready for the first task. */\r
 215         uxCriticalNesting = 0;\r
 216 \r
 217         /* Ensure the VFP is enabled - it should be anyway. */\r
 218         vPortEnableVFP();\r
 219 \r
 220         /* Lazy save always. */\r
 221         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 222 \r
 223         /* Start the first task. */\r
 224         vPortStartFirstTask();\r
 225 \r
 226         /* Should not get here! */\r
 227         return 0;\r
 228 }\r
 229 /*-----------------------------------------------------------*/\r
 230 \r
 231 void vPortEndScheduler( void )\r
 232 {\r
 233         /* It is unlikely that the CM4F port will require this function as there\r
 234         is nothing to return to.  */\r
 235 }\r
 236 /*-----------------------------------------------------------*/\r
 237 \r
 238 void vPortYieldFromISR( void )\r
 239 {\r
 240         /* Set a PendSV to request a context switch. */\r
 241         *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 242 }\r
 243 /*-----------------------------------------------------------*/\r
 244 \r
 245 void vPortEnterCritical( void )\r
 246 {\r
 247         portDISABLE_INTERRUPTS();\r
 248         uxCriticalNesting++;\r
 249 }\r
 250 /*-----------------------------------------------------------*/\r
 251 \r
 252 void vPortExitCritical( void )\r
 253 {\r
 254         uxCriticalNesting--;\r
 255         if( uxCriticalNesting == 0 )\r
 256         {\r
 257                 portENABLE_INTERRUPTS();\r
 258         }\r
 259 }\r
 260 /*-----------------------------------------------------------*/\r
 261 \r
 262 void xPortPendSVHandler( void )\r
 263 {\r
 264         /* This is a naked function. */\r
 265 \r
 266         __asm volatile\r
 267         (\r
 268         "       mrs r0, psp                                                     \n"\r
 269         "                                                                               \n"\r
 270         "       ldr     r3, pxCurrentTCBConst                           \n" /* Get the location of the current TCB. */\r
 271         "       ldr     r2, [r3]                                                \n"\r
 272         "                                                                               \n"\r
 273         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 274         "       it eq                                                           \n"\r
 275         "       vstmdbeq r0!, {s16-s31}                         \n"\r
 276         "                                                                               \n"\r
 277         "       stmdb r0!, {r4-r11, r14}                        \n" /* Save the core registers. */\r
 278         "                                                                               \n"\r
 279         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 280         "                                                                               \n"\r
 281         "       stmdb sp!, {r3, r14}                            \n"\r
 282         "       mov r0, %0                                                      \n"\r
 283         "       msr basepri, r0                                         \n"\r
 284         "       bl vTaskSwitchContext                           \n"\r
 285         "       mov r0, #0                                                      \n"\r
 286         "       msr basepri, r0                                         \n"\r
 287         "       ldmia sp!, {r3, r14}                            \n"\r
 288         "                                                                               \n"\r
 289         "       ldr r1, [r3]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 290         "       ldr r0, [r1]                                            \n"\r
 291         "                                                                               \n"\r
 292         "       ldmia r0!, {r4-r11, r14}                        \n" /* Pop the core registers. */\r
 293         "                                                                               \n"\r
 294         "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 295         "       it eq                                                           \n"\r
 296         "       vldmiaeq r0!, {s16-s31}                         \n"\r
 297         "                                                                               \n"\r
 298         "       msr psp, r0                                                     \n"\r
 299         "       bx r14                                                          \n"\r
 300         "                                                                               \n"\r
 301         "       .align 2                                                        \n"\r
 302         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 303         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 304         );\r
 305 }\r
 306 /*-----------------------------------------------------------*/\r
 307 \r
 308 void xPortSysTickHandler( void )\r
 309 {\r
 310 unsigned long ulDummy;\r
 311 \r
 312         /* If using preemption, also force a context switch. */\r
 313         #if configUSE_PREEMPTION == 1\r
 314                 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 315         #endif\r
 316 \r
 317         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 318         {\r
 319                 vTaskIncrementTick();\r
 320         }\r
 321         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 322 }\r
 323 /*-----------------------------------------------------------*/\r
 324 \r
 325 /*\r
 326  * Setup the systick timer to generate the tick interrupts at the required\r
 327  * frequency.\r
 328  */\r
 329 void prvSetupTimerInterrupt( void )\r
 330 {\r
 331         /* Configure SysTick to interrupt at the requested rate. */\r
 332         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 333         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 334 }\r
 335 /*-----------------------------------------------------------*/\r
 336 \r
 337 /* This is a naked function. */\r
 338 static void vPortEnableVFP( void )\r
 339 {\r
 340         __asm volatile\r
 341         (\r
 342                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 343                 "       ldr r1, [r0]                            \n"\r
 344                 "                                                               \n"\r
 345                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 346                 "       str r1, [r0]                            \n"\r
 347                 "       bx r14                                          "\r
 348         );\r
 349 }\r
 350 \r